update adi_library to vivado 2024.1
compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
@@ -0,0 +1,44 @@
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####################################################################################
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## Copyright (c) 2018 - 2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := i3c_controller_host_interface
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GENERIC_DEPS += ../../common/ad_mem_dual.v
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GENERIC_DEPS += ../../common/ad_rst.v
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GENERIC_DEPS += ../../common/up_axi.v
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GENERIC_DEPS += i3c_controller_cmd_parser.v
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GENERIC_DEPS += i3c_controller_host_interface.v
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GENERIC_DEPS += i3c_controller_pack.v
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GENERIC_DEPS += i3c_controller_regmap.v
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GENERIC_DEPS += i3c_controller_regmap.vh
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GENERIC_DEPS += i3c_controller_unpack.v
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GENERIC_DEPS += i3c_controller_write_ibi.v
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XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += i3c_controller_host_interface_constr.ttcl
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XILINX_DEPS += i3c_controller_host_interface_ip.tcl
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XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_cmdp.xml
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XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_cmdp_rtl.xml
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XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_rmap.xml
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XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_rmap_rtl.xml
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XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_sdio.xml
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XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_sdio_rtl.xml
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XILINX_LIB_DEPS += util_axis_fifo
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XILINX_LIB_DEPS += util_cdc
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XILINX_INTERFACE_DEPS += i3c_controller/interfaces
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INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
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INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo_address_generator.v
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INTEL_DEPS += ../../util_cdc/sync_bits.v
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INTEL_DEPS += ../../util_cdc/sync_gray.v
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INTEL_DEPS += i3c_controller_host_interface_constr.sdc
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INTEL_DEPS += i3c_controller_host_interface_hw.tcl
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include ../../scripts/library.mk
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,237 @@
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// ***************************************************************************
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||||
// ***************************************************************************
|
||||
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
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||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
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||||
//
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||||
// ***************************************************************************
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// ***************************************************************************
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/**
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* Parse commands.
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* When the first command indicates a pair command (e.g. CCC), await next
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* command to complete request (e.g. add CCC ID to parsed CCC command).
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* If it is a simple command (e.g. private transfer), their is no pair command.
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* Command receipts (cmdr) are transferred at the end of a transfer, with
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* updated length field indicating the number of bytes actually transferred,
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* since the peripheral shall cancel the transfer.
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*/
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`timescale 1ns/100ps
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module i3c_controller_cmd_parser (
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input clk,
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input reset_n,
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// Command FIFO
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output cmd_ready,
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input cmd_valid,
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input [31:0] cmd,
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input cmdr_ready,
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output cmdr_valid,
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output [31:0] cmdr,
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// Command parsed
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input cmdp_ready,
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output cmdp_valid,
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output [30:0] cmdp,
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input [2:0] cmdp_error,
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output rd_bytes_stop,
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input [11:0] rd_bytes_lvl,
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input wr_bytes_stop,
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input [11:0] wr_bytes_lvl
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);
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// Check bit 3 for any type of NACK (CE2_ERROR + NACK_RESP).
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// Check bit 4 for unknown address.
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// CE1_ERROR and CE3_ERROR are not implemented.
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localparam [3:0] NO_ERROR = 4'd0;
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localparam [3:0] CE0_ERROR = 4'd1;
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localparam [3:0] CE2_ERROR = 4'd4;
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localparam [3:0] NACK_RESP = 4'd6;
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localparam [3:0] UDA_ERROR = 4'd8;
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localparam [6:0] CCC_ENTDAA = 'h07;
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localparam [2:0] SM_RECEIVE = 0;
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localparam [2:0] SM_XFER_WAIT = 1;
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localparam [2:0] SM_XFER_WAIT_READY = 2;
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localparam [2:0] SM_CCC_WAIT = 3;
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localparam [2:0] SM_PRE_RECEIPT = 4;
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localparam [2:0] SM_RECEIPT = 5;
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reg [31:0] cmdr1;
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reg [7:0] cmdr2;
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reg [3:0] cmdr_error;
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reg [7:0] cmdr_sync;
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reg error_nack_bcast_reg;
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reg error_nack_resp_reg;
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reg error_unknown_da_reg;
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reg [2:0] sm;
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reg wr_bytes_stop_reg;
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reg [11:0] wr_bytes_lvl_reg;
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wire cmdp_rnw;
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wire [11:0] cmdp_buffer_len;
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wire cmdp_ccc;
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wire [6:0] cmdp_ccc_id;
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wire error_nack_bcast;
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wire error_unknown_da;
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wire error_nack_resp;
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wire [11:0] cmdr1_len;
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always @(posedge clk) begin
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if (!reset_n) begin
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sm <= SM_RECEIVE;
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cmdr_error <= NO_ERROR;
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cmdr_sync <= 8'd0;
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end else begin
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case (sm)
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SM_RECEIVE: begin
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cmdr_error <= NO_ERROR;
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cmdr2 <= 8'd0;
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if (cmd_valid) begin
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cmdr1 <= cmd;
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/* cmd[22] is cmdp_ccc */
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sm <= cmd[22] ? SM_CCC_WAIT : SM_XFER_WAIT;
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end else begin
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sm <= SM_RECEIVE;
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end
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error_nack_bcast_reg <= 1'b0;
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error_unknown_da_reg <= 1'b0;
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error_nack_resp_reg <= 1'b0;
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end
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SM_XFER_WAIT: begin
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sm <= cmdp_ready ? SM_XFER_WAIT_READY : sm;
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end
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SM_XFER_WAIT_READY: begin
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if (cmdp_ready) begin
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sm <= SM_PRE_RECEIPT;
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end
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if (error_nack_bcast) begin
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error_nack_bcast_reg <= error_nack_bcast;
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end
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if (error_unknown_da) begin
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error_unknown_da_reg <= error_unknown_da;
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end
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if (error_nack_resp) begin
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error_nack_resp_reg <= error_nack_resp;
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end
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end
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SM_CCC_WAIT: begin
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cmdr2 <= cmd[7:0];
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if (cmd_valid) begin
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sm <= SM_XFER_WAIT;
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end
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end
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SM_PRE_RECEIPT: begin
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// CE1_ERROR and CE3_ERROR not implemented.
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if (cmdp_ccc & |wr_bytes_lvl) begin
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cmdr_error <= CE0_ERROR;
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end else if (error_nack_bcast_reg) begin
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cmdr_error <= CE2_ERROR;
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end else if (error_unknown_da_reg) begin
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cmdr_error <= UDA_ERROR;
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end else if (error_nack_resp_reg) begin
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cmdr_error <= NACK_RESP;
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end
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// Ensure all receipt content is ok
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sm <= SM_RECEIPT;
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end
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SM_RECEIPT: begin
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if (cmdr_ready) begin
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sm <= SM_RECEIVE;
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cmdr_sync <= cmdr_sync + 1;
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end
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end
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default: begin
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sm <= SM_RECEIVE;
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end
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endcase
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end
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end
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// Lock on last sdi_bytes_lvl for the cmd
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// Since level increment on get state and is cleared by last on put phase,
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// delay i clock cycle.
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// Clear when cmr is read, since some RX transfer might get NACKed at
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// 0 bytes (no sdi_last).
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always @(posedge clk) begin
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wr_bytes_stop_reg <= wr_bytes_stop;
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if (cmdr_valid & cmdr_ready) begin
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wr_bytes_lvl_reg <= 0;
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end else if (wr_bytes_stop_reg) begin
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wr_bytes_lvl_reg <= wr_bytes_lvl;
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end
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end
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assign cmd_ready = (sm == SM_RECEIVE || sm == SM_CCC_WAIT) & reset_n;
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assign cmdp_valid = (sm == SM_XFER_WAIT & reset_n);
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assign cmdr = {8'd0, cmdr_error, cmdr1_len, cmdr_sync};
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assign cmdr_valid = sm == SM_RECEIPT;
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// For read bytes (write to peripheral), it is either all transferred or none,
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// since the peripheral can only reject during the address ACK.
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// For write bytes (read from peripheral), the peripheral shall cancel
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// before finishing the transfer.
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assign cmdr1_len = cmdp_rnw ?
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wr_bytes_lvl_reg :
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(error_nack_bcast_reg | error_nack_resp_reg ?
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12'd0 : cmdp_buffer_len
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);
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assign rd_bytes_stop = (cmdp_buffer_len == rd_bytes_lvl) & |rd_bytes_lvl;
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assign cmdp_rnw = cmdr1[0];
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assign cmdp_ccc = cmdr1[22];
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// The Linux implementation sets ENTDAA buffer length to 0,
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// but we need with 1 to contiguously fetch the DAs.
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assign cmdp_buffer_len = cmdp_ccc_id == CCC_ENTDAA ? 1 : cmdr1[19:08];
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assign cmdp_ccc_id = cmdr2[6:0];
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assign error_nack_bcast = cmdp_error[0];
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assign error_unknown_da = cmdp_error[1];
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assign error_nack_resp = cmdp_error[2];
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// Remove reserved bits.
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assign cmdp = {
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cmdr2[7:0],
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cmdr1[22:0]
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};
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endmodule
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+253
@@ -0,0 +1,253 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module i3c_controller_host_interface #(
|
||||
parameter ID = 0,
|
||||
parameter ASYNC_CLK = 0,
|
||||
parameter OFFLOAD = 1
|
||||
) (
|
||||
input clk,
|
||||
output reset_n,
|
||||
|
||||
// Slave AXI interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [15:0] s_axi_awaddr,
|
||||
output s_axi_awready,
|
||||
input [2:0] s_axi_awprot,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
output s_axi_arready,
|
||||
input [2:0] s_axi_arprot,
|
||||
output s_axi_rvalid,
|
||||
input s_axi_rready,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
|
||||
output irq,
|
||||
input offload_trigger,
|
||||
|
||||
// Command parsed
|
||||
|
||||
input cmdp_ready,
|
||||
output cmdp_valid,
|
||||
output [30:0] cmdp,
|
||||
input [2:0] cmdp_error,
|
||||
input cmdp_nop,
|
||||
input cmdp_daa_trigger,
|
||||
|
||||
// Byte stream
|
||||
|
||||
input sdo_ready,
|
||||
output sdo_valid,
|
||||
output [7:0] sdo,
|
||||
|
||||
output sdi_ready,
|
||||
input sdi_valid,
|
||||
input sdi_last,
|
||||
input [7:0] sdi,
|
||||
|
||||
output ibi_ready,
|
||||
input ibi_valid,
|
||||
input [14:0] ibi,
|
||||
|
||||
input offload_sdi_ready,
|
||||
output offload_sdi_valid,
|
||||
output [31:0] offload_sdi,
|
||||
|
||||
// uP accessible info
|
||||
|
||||
output [1:0] rmap_ibi_config,
|
||||
output [1:0] rmap_pp_sg,
|
||||
input [6:0] rmap_dev_char_addr,
|
||||
output [3:0] rmap_dev_char_data
|
||||
);
|
||||
|
||||
wire rd_bytes_stop;
|
||||
wire [11:0] rd_bytes_lvl;
|
||||
wire [11:0] wr_bytes_lvl;
|
||||
|
||||
wire cmd_ready;
|
||||
wire cmd_valid;
|
||||
wire [31:0] cmd;
|
||||
|
||||
wire cmdr_ready;
|
||||
wire cmdr_valid;
|
||||
wire [31:0] cmdr;
|
||||
|
||||
wire sdo_ready_w;
|
||||
wire sdo_valid_w;
|
||||
wire [31:0] sdo_w;
|
||||
|
||||
wire sdi_ready_w;
|
||||
wire sdi_valid_w;
|
||||
wire [31:0] sdi_w;
|
||||
|
||||
wire ibi_ready_w;
|
||||
wire ibi_valid_w;
|
||||
wire [31:0] ibi_w;
|
||||
|
||||
wire clk_w;
|
||||
|
||||
generate if (ASYNC_CLK) begin
|
||||
assign clk_w = clk;
|
||||
end else begin
|
||||
assign clk_w = s_axi_aclk;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
i3c_controller_regmap #(
|
||||
.ID(ID),
|
||||
.OFFLOAD(OFFLOAD),
|
||||
.ASYNC_CLK(ASYNC_CLK)
|
||||
) i_i3c_controller_regmap (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.irq(irq),
|
||||
.clk(clk),
|
||||
.a_reset_n(reset_n),
|
||||
.cmd_nop(cmdp_nop),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd(cmd),
|
||||
.cmdr_ready(cmdr_ready),
|
||||
.cmdr_valid(cmdr_valid),
|
||||
.cmdr(cmdr),
|
||||
.sdo_ready(sdo_ready_w),
|
||||
.sdo_valid(sdo_valid_w),
|
||||
.sdo(sdo_w),
|
||||
.sdi_ready(sdi_ready_w),
|
||||
.sdi_valid(sdi_valid_w),
|
||||
.sdi(sdi_w),
|
||||
.offload_sdi_ready(offload_sdi_ready),
|
||||
.offload_sdi_valid(offload_sdi_valid),
|
||||
.offload_sdi(offload_sdi),
|
||||
.ibi_ready(ibi_ready_w),
|
||||
.ibi_valid(ibi_valid_w),
|
||||
.ibi(ibi_w),
|
||||
.daa_trigger(cmdp_daa_trigger),
|
||||
.offload_trigger(offload_trigger),
|
||||
.rmap_ibi_config(rmap_ibi_config),
|
||||
.rmap_pp_sg(rmap_pp_sg),
|
||||
.rmap_dev_char_addr(rmap_dev_char_addr),
|
||||
.rmap_dev_char_data(rmap_dev_char_data));
|
||||
|
||||
i3c_controller_unpack
|
||||
i_i3c_controller_unpack (
|
||||
.clk(clk_w),
|
||||
.reset_n(reset_n),
|
||||
.stop(rd_bytes_stop),
|
||||
.u32_ready(sdo_ready_w),
|
||||
.u32_valid(sdo_valid_w),
|
||||
.u32(sdo_w),
|
||||
.u8_lvl(rd_bytes_lvl),
|
||||
.u8_ready(sdo_ready),
|
||||
.u8_valid(sdo_valid),
|
||||
.u8(sdo));
|
||||
|
||||
i3c_controller_pack
|
||||
i_i3c_controller_pack (
|
||||
.clk(clk_w),
|
||||
.reset_n(reset_n),
|
||||
.u32_ready(sdi_ready_w),
|
||||
.u32_valid(sdi_valid_w),
|
||||
.u32(sdi_w),
|
||||
.u8_lvl(wr_bytes_lvl),
|
||||
.u8_ready(sdi_ready),
|
||||
.u8_valid(sdi_valid),
|
||||
.u8_last(sdi_last),
|
||||
.u8(sdi));
|
||||
|
||||
i3c_controller_write_ibi
|
||||
i_i3c_controller_write_ibi (
|
||||
.clk(clk_w),
|
||||
.reset_n(reset_n),
|
||||
.out_ready(ibi_ready_w),
|
||||
.out_valid(ibi_valid_w),
|
||||
.out(ibi_w),
|
||||
.in_ready(ibi_ready),
|
||||
.in_valid(ibi_valid),
|
||||
.in(ibi));
|
||||
|
||||
i3c_controller_cmd_parser
|
||||
i_i3c_controller_cmd_parser (
|
||||
.clk(clk_w),
|
||||
.reset_n(reset_n),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd(cmd),
|
||||
.cmdr_ready(cmdr_ready),
|
||||
.cmdr_valid(cmdr_valid),
|
||||
.cmdr(cmdr),
|
||||
.cmdp_valid(cmdp_valid),
|
||||
.cmdp_ready(cmdp_ready),
|
||||
.cmdp(cmdp),
|
||||
.cmdp_error(cmdp_error),
|
||||
.rd_bytes_stop(rd_bytes_stop),
|
||||
.rd_bytes_lvl(rd_bytes_lvl),
|
||||
.wr_bytes_stop(sdi_last),
|
||||
.wr_bytes_lvl(wr_bytes_lvl));
|
||||
|
||||
endmodule
|
||||
+468
@@ -0,0 +1,468 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2024.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="67aaba48adfd41f9a5dcea643187b0ce"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../common/ad_mem_dual.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i3c_controller_cmd_parser.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i3c_controller_pack.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i3c_controller_regmap.vh">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
<Attr Name="IsVisible" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i3c_controller_regmap.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i3c_controller_unpack.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i3c_controller_write_ibi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i3c_controller_host_interface.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i3c_controller_host_interface_constr.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="i3c_controller_host_interface"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../xilinx/common/ad_rst_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="22">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
+4
@@ -0,0 +1,4 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2014 Analog Devices, Inc. All rights reserved.
|
||||
# SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
<: set async_clk [getBooleanValue "ASYNC_CLK"] :>
|
||||
|
||||
<: if { $async_clk } { :>
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
|
||||
|
||||
set_false_path -quiet \
|
||||
-from [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_fifo_status/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
<: } :>
|
||||
+137
@@ -0,0 +1,137 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create i3c_controller_host_interface {I3C Controller Host Interface}
|
||||
set_module_property ELABORATION_CALLBACK p_elaboration
|
||||
ad_ip_files i3c_controller_host_interface [list \
|
||||
$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v \
|
||||
$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo_address_generator.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_gray.v \
|
||||
$ad_hdl_dir/library/common/ad_mem_dual.v \
|
||||
$ad_hdl_dir/library/common/ad_rst.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
|
||||
i3c_controller_host_interface_constr.sdc \
|
||||
i3c_controller_host_interface.v \
|
||||
i3c_controller_regmap.v \
|
||||
i3c_controller_regmap.vh \
|
||||
i3c_controller_cmd_parser.v \
|
||||
i3c_controller_pack.v \
|
||||
i3c_controller_unpack.v \
|
||||
i3c_controller_write_ibi.v \
|
||||
]
|
||||
|
||||
# Parameters
|
||||
|
||||
ad_ip_parameter ID INTEGER 0
|
||||
ad_ip_parameter ASYNC_CLK INTEGER 0
|
||||
ad_ip_parameter OFFLOAD INTEGER 0
|
||||
|
||||
proc p_elaboration {} {
|
||||
|
||||
set disabled_intfs {}
|
||||
|
||||
# Read parameters
|
||||
|
||||
set id [get_parameter_value "ID"]
|
||||
set async_clk [get_parameter_value "ASYNC_CLK"]
|
||||
set offload [get_parameter_value "OFFLOAD"]
|
||||
|
||||
# Interrupt
|
||||
|
||||
add_interface interrupt_sender interrupt end
|
||||
add_interface_port interrupt_sender irq irq Output 1
|
||||
|
||||
# AXI Memory Mapped interface
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16
|
||||
|
||||
set_interface_property interrupt_sender associatedAddressablePoint s_axi
|
||||
set_interface_property interrupt_sender associatedClock s_axi_clock
|
||||
set_interface_property interrupt_sender associatedReset s_axi_reset
|
||||
set_interface_property interrupt_sender ENABLED true
|
||||
|
||||
ad_interface clock clk input 1
|
||||
|
||||
if {!($async_clk)} {
|
||||
set if_clk s_axi_clock
|
||||
} else {
|
||||
set if_clk if_clk
|
||||
}
|
||||
|
||||
ad_interface reset reset_n output 1 $if_clk
|
||||
|
||||
ad_interface signal offload_trigger input 1 if_pwm
|
||||
|
||||
add_interface sdo axi4stream start
|
||||
add_interface_port sdo sdo_ready tready input 1
|
||||
add_interface_port sdo sdo_valid tvalid output 1
|
||||
add_interface_port sdo sdo tdata output 8
|
||||
|
||||
set_interface_property sdo associatedClock $if_clk
|
||||
set_interface_property sdo associatedReset if_reset_n
|
||||
|
||||
add_interface sdi axi4stream end
|
||||
add_interface_port sdi sdi_ready tready output 1
|
||||
add_interface_port sdi sdi_valid tvalid input 1
|
||||
add_interface_port sdi sdi_last tlast input 1
|
||||
add_interface_port sdi sdi tdata input 8
|
||||
|
||||
set_interface_property sdi associatedClock $if_clk
|
||||
set_interface_property sdi associatedReset if_reset_n
|
||||
|
||||
add_interface ibi axi4stream end
|
||||
add_interface_port ibi ibi_ready tready output 1
|
||||
add_interface_port ibi ibi_valid tvalid input 1
|
||||
add_interface_port ibi ibi tdata input 15
|
||||
|
||||
set_interface_property ibi associatedClock $if_clk
|
||||
set_interface_property ibi associatedReset if_reset_n
|
||||
|
||||
add_interface offload_sdi axi4stream start
|
||||
add_interface_port offload_sdi offload_sdi_ready tready input 1
|
||||
add_interface_port offload_sdi offload_sdi_valid tvalid output 1
|
||||
add_interface_port offload_sdi offload_sdi tdata output 32
|
||||
|
||||
set_interface_property offload_sdi associatedClock $if_clk
|
||||
set_interface_property offload_sdi associatedReset if_reset_n
|
||||
|
||||
add_interface cmdp conduit start
|
||||
add_interface_port cmdp cmdp_ready cready input 1
|
||||
add_interface_port cmdp cmdp_valid cvalid output 1
|
||||
add_interface_port cmdp cmdp cdata output 31
|
||||
add_interface_port cmdp cmdp_error error input 3
|
||||
add_interface_port cmdp cmdp_nop nop input 1
|
||||
add_interface_port cmdp cmdp_daa_trigger daa_trigger input 1
|
||||
|
||||
set_interface_property cmdp associatedClock $if_clk
|
||||
set_interface_property cmdp associatedReset if_reset_n
|
||||
|
||||
add_interface rmap conduit start
|
||||
add_interface_port rmap rmap_ibi_config ibi_config output 2
|
||||
add_interface_port rmap rmap_pp_sg pp_sg output 2
|
||||
add_interface_port rmap rmap_dev_char_addr dev_char_addr input 7
|
||||
add_interface_port rmap rmap_dev_char_data dev_char_data output 4
|
||||
|
||||
set_interface_property rmap associatedClock $if_clk
|
||||
set_interface_property rmap associatedReset if_reset_n
|
||||
|
||||
if {!($offload)} {
|
||||
lappend disabled_intfs offload_sdi if_offload_trigger
|
||||
}
|
||||
|
||||
if {!($async_clk)} {
|
||||
lappend disabled_intfs if_clk
|
||||
}
|
||||
|
||||
foreach interface $disabled_intfs {
|
||||
set_interface_property $interface ENABLED false
|
||||
}
|
||||
}
|
||||
+156
@@ -0,0 +1,156 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create i3c_controller_host_interface
|
||||
adi_ip_files i3c_controller_host_interface [list \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/ad_mem_dual.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"i3c_controller_host_interface_constr.ttcl" \
|
||||
"i3c_controller_host_interface.v" \
|
||||
"i3c_controller_regmap.v" \
|
||||
"i3c_controller_regmap.vh" \
|
||||
"i3c_controller_cmd_parser.v" \
|
||||
"i3c_controller_pack.v" \
|
||||
"i3c_controller_unpack.v" \
|
||||
"i3c_controller_write_ibi.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties i3c_controller_host_interface
|
||||
adi_ip_ttcl i3c_controller_host_interface "i3c_controller_host_interface_constr.ttcl"
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
]
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/i3c_controller/host_interface} [ipx::current_core]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "sdio" "master" \
|
||||
"analog.com:interface:i3c_controller_sdio_rtl:1.0" \
|
||||
"analog.com:interface:i3c_controller_sdio:1.0" \
|
||||
{
|
||||
{"sdo_ready" "sdo_ready"} \
|
||||
{"sdo_valid" "sdo_valid"} \
|
||||
{"sdo" "sdo"} \
|
||||
{"sdi_ready" "sdi_ready"} \
|
||||
{"sdi_valid" "sdi_valid"} \
|
||||
{"sdi_last" "sdi_last"} \
|
||||
{"sdi" "sdi"} \
|
||||
{"ibi_ready" "ibi_ready"} \
|
||||
{"ibi_valid" "ibi_valid"} \
|
||||
{"ibi" "ibi"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "sdio" "reset_n"
|
||||
|
||||
adi_add_bus "offload_sdi" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{
|
||||
{"offload_sdi_ready" "TREADY"} \
|
||||
{"offload_sdi_valid" "TVALID"} \
|
||||
{"offload_sdi" "TDATA"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "offload_sdi" "reset_n" "master"
|
||||
|
||||
adi_add_bus "cmdp" "master" \
|
||||
"analog.com:interface:i3c_controller_cmdp_rtl:1.0" \
|
||||
"analog.com:interface:i3c_controller_cmdp:1.0" \
|
||||
{
|
||||
{"cmdp_valid" "cmdp_valid"} \
|
||||
{"cmdp_ready" "cmdp_ready"} \
|
||||
{"cmdp" "cmdp"} \
|
||||
{"cmdp_error" "cmdp_error"} \
|
||||
{"cmdp_nop" "cmdp_nop"} \
|
||||
{"cmdp_daa_trigger" "cmdp_daa_trigger"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "cmdp" "reset_n"
|
||||
|
||||
adi_add_bus "rmap" "master" \
|
||||
"analog.com:interface:i3c_controller_rmap_rtl:1.0" \
|
||||
"analog.com:interface:i3c_controller_rmap:1.0" \
|
||||
{
|
||||
{"rmap_ibi_config" "rmap_ibi_config"} \
|
||||
{"rmap_pp_sg" "rmap_pp_sg"} \
|
||||
{"rmap_dev_char_addr" "rmap_dev_char_addr"} \
|
||||
{"rmap_dev_char_data" "rmap_dev_char_data"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "rmap" "reset_n" "master"
|
||||
|
||||
adi_set_ports_dependency "clk" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK')) = 1)"
|
||||
|
||||
adi_set_bus_dependency "offload_sdi" "offload_sdi" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.OFFLOAD')) = 1)"
|
||||
adi_set_ports_dependency "offload_trigger" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.OFFLOAD')) = 1)" 0
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
## ID
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "255" \
|
||||
] \
|
||||
[ipx::get_user_parameters ID -of_objects $cc]
|
||||
|
||||
foreach {k v} { \
|
||||
"ASYNC_CLK" "false" \
|
||||
"OFFLOAD" "false" \
|
||||
} { \
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" $v \
|
||||
] \
|
||||
[ipx::get_user_parameters $k -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" $v \
|
||||
] \
|
||||
[ipx::get_hdl_parameters $k -of_objects $cc]
|
||||
}
|
||||
|
||||
## Customize IP Layout
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create general configuration page
|
||||
ipgui::add_page -name {I3C Controller Host Interface} -component [ipx::current_core] -display_name {AXI I3C Controller Host Interface}
|
||||
set page0 [ipgui::get_pagespec -name "I3C Controller Host Interface" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration" ]
|
||||
|
||||
ipgui::add_param -name "ID" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Core ID" \
|
||||
"tooltip" "\[ID\] Core instance ID" \
|
||||
] [ipgui::get_guiparamspec -name "ID" -component $cc]
|
||||
|
||||
ipgui::add_param -name "ASYNC_CLK" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Asynchronous core clock" \
|
||||
"tooltip" "\[ASYNC_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \
|
||||
] [ipgui::get_guiparamspec -name "ASYNC_CLK" -component $cc]
|
||||
|
||||
ipgui::add_param -name "OFFLOAD" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Offload engine" \
|
||||
"tooltip" "\[OFFLOAD\] Allows to offload output data to a external receiver, like a DMA" \
|
||||
] [ipgui::get_guiparamspec -name "OFFLOAD" -component $cc]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files $cc
|
||||
ipx::save_core $cc
|
||||
@@ -0,0 +1,111 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
/**
|
||||
* Packs u8 stream into u32.
|
||||
* Restrictions:
|
||||
* At partial payload, e.g. 3-bytes, the remaining byte value is unknown.
|
||||
*/
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module i3c_controller_pack (
|
||||
input clk,
|
||||
input reset_n,
|
||||
|
||||
input u32_ready,
|
||||
output u32_valid,
|
||||
output [31:0] u32,
|
||||
|
||||
output [11:0] u8_lvl,
|
||||
|
||||
output u8_ready,
|
||||
input u8_valid,
|
||||
input u8_last,
|
||||
input [7:0] u8
|
||||
);
|
||||
|
||||
localparam [0:0] SM_GET = 0;
|
||||
localparam [0:0] SM_PUT = 1;
|
||||
|
||||
reg [0:0] sm;
|
||||
reg [1:0] c;
|
||||
reg [7:0] u32_reg [3:0];
|
||||
reg [11:0] u8_lvl_reg;
|
||||
reg u8_last_reg;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!reset_n) begin
|
||||
sm <= SM_GET;
|
||||
c <= 2'b00;
|
||||
u8_last_reg <= 1'b0;
|
||||
u8_lvl_reg <= 0;
|
||||
end else begin
|
||||
case (sm)
|
||||
SM_GET: begin
|
||||
u8_last_reg <= u8_last;
|
||||
if (u8_valid) begin // tick
|
||||
u32_reg[3-c] <= u8;
|
||||
u8_lvl_reg <= u8_lvl_reg + 1;
|
||||
c <= c + 1;
|
||||
if (c == 2'b11 | u8_last) begin
|
||||
c <= 2'b00;
|
||||
sm <= SM_PUT;
|
||||
end
|
||||
end
|
||||
end
|
||||
SM_PUT: begin
|
||||
if (u32_ready) begin
|
||||
sm <= SM_GET;
|
||||
if (u8_last_reg) begin
|
||||
u8_lvl_reg <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign u8_ready = sm == SM_GET & reset_n;
|
||||
assign u32_valid = sm == SM_PUT;
|
||||
assign u8_lvl = u8_lvl_reg;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i=0; i<4; i=i+1) begin: gen_u32
|
||||
assign u32[8*i+7:8*i] = u32_reg[3-i];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,747 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
`include "i3c_controller_regmap.vh"
|
||||
|
||||
`define ADDRESS_WIDTH 8
|
||||
|
||||
module i3c_controller_regmap #(
|
||||
parameter ID = 0,
|
||||
parameter ASYNC_CLK = 0,
|
||||
parameter OFFLOAD = 1,
|
||||
parameter DATA_WIDTH = 32
|
||||
) (
|
||||
|
||||
// Slave AXI interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [15:0] s_axi_awaddr,
|
||||
output s_axi_awready,
|
||||
input [2:0] s_axi_awprot,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
output s_axi_arready,
|
||||
input [2:0] s_axi_arprot,
|
||||
output s_axi_rvalid,
|
||||
input s_axi_rready,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
|
||||
output reg irq,
|
||||
|
||||
// Core basic signals
|
||||
|
||||
input clk,
|
||||
output a_reset_n,
|
||||
|
||||
// I3C control signals
|
||||
|
||||
input cmd_ready,
|
||||
input cmd_nop,
|
||||
output cmd_valid,
|
||||
output [DATA_WIDTH-1:0] cmd,
|
||||
|
||||
output cmdr_ready,
|
||||
input cmdr_valid,
|
||||
input [DATA_WIDTH-1:0] cmdr,
|
||||
|
||||
input sdo_ready,
|
||||
output sdo_valid,
|
||||
output [DATA_WIDTH-1:0] sdo,
|
||||
|
||||
output sdi_ready,
|
||||
input sdi_valid,
|
||||
input [DATA_WIDTH-1:0] sdi,
|
||||
|
||||
input offload_sdi_ready,
|
||||
output offload_sdi_valid,
|
||||
output [DATA_WIDTH-1:0] offload_sdi,
|
||||
|
||||
output ibi_ready,
|
||||
input ibi_valid,
|
||||
input [DATA_WIDTH-1:0] ibi,
|
||||
|
||||
input daa_trigger,
|
||||
input offload_trigger,
|
||||
|
||||
// uP accessible info
|
||||
|
||||
output reg [1:0] rmap_ibi_config,
|
||||
output [1:0] rmap_pp_sg,
|
||||
input [6:0] rmap_dev_char_addr,
|
||||
output [3:0] rmap_dev_char_data
|
||||
);
|
||||
|
||||
localparam PCORE_VERSION = 'h00000100;
|
||||
|
||||
reg [31:0] up_scratch = 32'h00; // Scratch register
|
||||
reg up_sw_reset = 1'b1;
|
||||
reg [31:0] up_rdata_ff = 32'd0;
|
||||
reg up_wack_ff = 1'b0;
|
||||
reg up_rack_ff = 1'b0;
|
||||
|
||||
// Holds DAA trigger High until sdo_fifo_empty goes Low,
|
||||
// meaning DA got written.
|
||||
reg daa_trigger_lock;
|
||||
|
||||
reg daa_pending;
|
||||
reg cmdr_pending;
|
||||
reg ibi_pending;
|
||||
|
||||
reg [`I3C_REGMAP_IRQ_WIDTH:0] up_irq_mask = 8'h0;
|
||||
reg [6:0] ops;
|
||||
reg [6:0] ops_candidate;
|
||||
reg [6:0] dev_char_addr_reg;
|
||||
|
||||
// CMD FIFO
|
||||
|
||||
wire [`ADDRESS_WIDTH-1:0] cmd_fifo_room;
|
||||
wire cmd_fifo_almost_empty;
|
||||
wire up_cmd_fifo_almost_empty;
|
||||
|
||||
wire [DATA_WIDTH-1:0] cmd_fifo_data;
|
||||
wire cmd_fifo_ready;
|
||||
wire cmd_fifo_valid;
|
||||
|
||||
// CMDR FIFO
|
||||
|
||||
wire cmdr_fifo_data_msb_s;
|
||||
wire [`ADDRESS_WIDTH-1:0] cmdr_fifo_level;
|
||||
wire cmdr_fifo_almost_full;
|
||||
wire up_cmdr_fifo_almost_full;
|
||||
|
||||
wire [DATA_WIDTH-1:0] cmdr_fifo_data;
|
||||
wire cmdr_fifo_ready;
|
||||
wire cmdr_fifo_valid;
|
||||
wire cmdr_fifo_empty;
|
||||
|
||||
// SDO FIFO
|
||||
|
||||
wire [`ADDRESS_WIDTH-1:0] sdo_fifo_room;
|
||||
wire sdo_fifo_almost_empty;
|
||||
wire up_sdo_fifo_almost_empty;
|
||||
|
||||
wire [DATA_WIDTH-1:0] sdo_fifo_data;
|
||||
wire sdo_fifo_ready;
|
||||
wire sdo_fifo_valid;
|
||||
wire sdo_fifo_empty;
|
||||
|
||||
// SDI FIFO
|
||||
|
||||
wire sdi_fifo_data_msb_s;
|
||||
wire [`ADDRESS_WIDTH-1:0] sdi_fifo_level;
|
||||
wire sdi_fifo_almost_full;
|
||||
wire up_sdi_fifo_almost_full;
|
||||
|
||||
wire [DATA_WIDTH-1:0] sdi_fifo_data;
|
||||
wire sdi_fifo_ready;
|
||||
wire sdi_fifo_valid;
|
||||
wire sdi_fifo_empty;
|
||||
|
||||
// IBI FIFO
|
||||
|
||||
wire ibi_fifo_data_msb_s;
|
||||
wire [`ADDRESS_WIDTH-1:0] ibi_fifo_level;
|
||||
wire ibi_fifo_almost_full;
|
||||
wire up_ibi_fifo_almost_full;
|
||||
|
||||
wire [DATA_WIDTH-1:0] ibi_fifo_data;
|
||||
wire ibi_fifo_ready;
|
||||
wire ibi_fifo_valid;
|
||||
wire ibi_fifo_empty;
|
||||
|
||||
wire up_sw_resetn = ~up_sw_reset;
|
||||
|
||||
wire [31:0] up_rdata_ff_w;
|
||||
wire up_wreq_s;
|
||||
wire up_rreq_s;
|
||||
wire [31:0] up_wdata_s;
|
||||
wire [13:0] up_waddr_s;
|
||||
wire [13:0] up_raddr_s;
|
||||
wire up_cmd_nop;
|
||||
|
||||
// IRQ handling
|
||||
|
||||
wire [`I3C_REGMAP_IRQ_WIDTH:0] up_irq_source;
|
||||
wire [`I3C_REGMAP_IRQ_WIDTH:0] up_irq_pending;
|
||||
|
||||
wire ops_mode;
|
||||
wire [3:0] ops_offload_len;
|
||||
wire [1:0] ops_sg;
|
||||
wire offload_idle;
|
||||
|
||||
wire [31:0] cmd_w;
|
||||
wire cmd_valid_w;
|
||||
wire cmd_ready_w;
|
||||
|
||||
wire [6:0] dev_char_addr;
|
||||
wire dev_char_w;
|
||||
wire dev_char_wea;
|
||||
wire dev_char_rea;
|
||||
wire dev_char_ea;
|
||||
wire [3:0] dev_char_wdata;
|
||||
wire [3:0] dev_char_rdata;
|
||||
|
||||
// Offload mode
|
||||
|
||||
wire [31:0] offload_douta;
|
||||
wire [31:0] offload_cmd;
|
||||
wire [31:0] offload_sdo;
|
||||
wire offload_cmd_valid;
|
||||
wire offload_sdo_valid;
|
||||
|
||||
wire clk_1;
|
||||
|
||||
wire cmdr_valid_w;
|
||||
wire cmdr_ready_w;
|
||||
|
||||
wire [31:0] sdo_w;
|
||||
wire sdo_valid_w;
|
||||
wire sdo_ready_w;
|
||||
|
||||
// Interface wrapper
|
||||
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH (16)
|
||||
) i_up_axi (
|
||||
.up_rstn(s_axi_aresetn),
|
||||
.up_clk(s_axi_aclk),
|
||||
.up_axi_awvalid(s_axi_awvalid),
|
||||
.up_axi_awaddr(s_axi_awaddr),
|
||||
.up_axi_awready(s_axi_awready),
|
||||
.up_axi_wvalid(s_axi_wvalid),
|
||||
.up_axi_wdata(s_axi_wdata),
|
||||
.up_axi_wstrb(s_axi_wstrb),
|
||||
.up_axi_wready(s_axi_wready),
|
||||
.up_axi_bvalid(s_axi_bvalid),
|
||||
.up_axi_bresp(s_axi_bresp),
|
||||
.up_axi_bready(s_axi_bready),
|
||||
.up_axi_arvalid(s_axi_arvalid),
|
||||
.up_axi_araddr(s_axi_araddr),
|
||||
.up_axi_arready(s_axi_arready),
|
||||
.up_axi_rvalid(s_axi_rvalid),
|
||||
.up_axi_rresp(s_axi_rresp),
|
||||
.up_axi_rdata(s_axi_rdata),
|
||||
.up_axi_rready(s_axi_rready),
|
||||
.up_wreq(up_wreq_s),
|
||||
.up_waddr(up_waddr_s),
|
||||
.up_wdata(up_wdata_s),
|
||||
.up_wack(up_wack_ff),
|
||||
.up_rreq(up_rreq_s),
|
||||
.up_raddr(up_raddr_s),
|
||||
.up_rdata(up_rdata_ff_w),
|
||||
.up_rack(up_rack_ff));
|
||||
|
||||
assign up_irq_source = {
|
||||
daa_pending,
|
||||
ibi_pending,
|
||||
cmdr_pending,
|
||||
up_ibi_fifo_almost_full,
|
||||
up_sdi_fifo_almost_full,
|
||||
up_sdo_fifo_almost_empty,
|
||||
up_cmdr_fifo_almost_full,
|
||||
up_cmd_fifo_almost_empty
|
||||
};
|
||||
|
||||
assign up_irq_pending = up_irq_mask & up_irq_source;
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (s_axi_aresetn == 1'b0) begin
|
||||
irq <= 1'b0;
|
||||
end else begin
|
||||
irq <= |up_irq_pending;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (s_axi_aresetn == 1'b0) begin
|
||||
up_wack_ff <= 1'b0;
|
||||
up_scratch <= 32'h0;
|
||||
up_sw_reset <= 1'b1;
|
||||
end else begin
|
||||
up_wack_ff <= up_wreq_s;
|
||||
if (up_wreq_s) begin
|
||||
case (up_waddr_s[7:0])
|
||||
`I3C_REGMAP_ENABLE: up_sw_reset <= up_wdata_s[0];
|
||||
`I3C_REGMAP_SCRATCH: up_scratch <= up_wdata_s;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign ops_mode = ops[0];
|
||||
assign ops_offload_len = ops[4:1];
|
||||
assign ops_sg = ops[6:5];
|
||||
assign rmap_pp_sg = ops_sg;
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (!up_sw_resetn) begin
|
||||
ops <= 7'b1100000;
|
||||
end else if (up_cmd_nop) begin
|
||||
if ((~ops_mode & ~cmd_valid_w) | (ops_mode & offload_idle)) begin
|
||||
ops <= ops_candidate;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// the software reset should reset all the registers
|
||||
integer i;
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (!up_sw_resetn) begin
|
||||
up_irq_mask <= 8'h0;
|
||||
rmap_ibi_config <= 2'h0;
|
||||
ops_candidate <= 7'd0;
|
||||
end else begin
|
||||
if (up_wreq_s) begin
|
||||
case (up_waddr_s[7:0])
|
||||
`I3C_REGMAP_IRQ_MASK: up_irq_mask <= up_wdata_s[`I3C_REGMAP_IRQ_WIDTH:0];
|
||||
`I3C_REGMAP_IBI_CONFIG: rmap_ibi_config <= up_wdata_s[1:0];
|
||||
`I3C_REGMAP_OPS: ops_candidate <= up_wdata_s[6:0];
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (s_axi_aresetn == 1'b0) begin
|
||||
up_rack_ff <= 1'd0;
|
||||
end else begin
|
||||
up_rack_ff <= up_rreq_s;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
case (up_raddr_s[7:0])
|
||||
`I3C_REGMAP_VERSION: up_rdata_ff <= PCORE_VERSION;
|
||||
`I3C_REGMAP_DEVICE_ID: up_rdata_ff <= ID;
|
||||
`I3C_REGMAP_SCRATCH: up_rdata_ff <= up_scratch;
|
||||
`I3C_REGMAP_ENABLE: up_rdata_ff <= up_sw_reset;
|
||||
`I3C_REGMAP_IRQ_MASK: up_rdata_ff <= up_irq_mask;
|
||||
`I3C_REGMAP_IRQ_PENDING: up_rdata_ff <= up_irq_pending;
|
||||
`I3C_REGMAP_IRQ_SOURCE: up_rdata_ff <= up_irq_source;
|
||||
`I3C_REGMAP_CMD_FIFO_ROOM: up_rdata_ff <= cmd_fifo_room;
|
||||
`I3C_REGMAP_CMDR_FIFO_LEVEL:up_rdata_ff <= cmdr_fifo_level;
|
||||
`I3C_REGMAP_SDO_FIFO_ROOM: up_rdata_ff <= sdo_fifo_room;
|
||||
`I3C_REGMAP_SDI_FIFO_LEVEL: up_rdata_ff <= sdi_fifo_level;
|
||||
`I3C_REGMAP_IBI_FIFO_LEVEL: up_rdata_ff <= ibi_fifo_level;
|
||||
`I3C_REGMAP_CMDR_FIFO: up_rdata_ff <= cmdr_fifo_data;
|
||||
`I3C_REGMAP_SDI_FIFO: up_rdata_ff <= sdi_fifo_data;
|
||||
`I3C_REGMAP_IBI_FIFO: up_rdata_ff <= ibi_fifo_data;
|
||||
`I3C_REGMAP_FIFO_STATUS: up_rdata_ff <= {sdi_fifo_empty, ibi_fifo_empty, cmdr_fifo_empty};
|
||||
`I3C_REGMAP_OPS: up_rdata_ff <= {cmd_nop, ops};
|
||||
default: up_rdata_ff <= 32'h0;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign up_rdata_ff_w = up_raddr_s[7:0] == `I3C_REGMAP_DEV_CHAR ? {16'b0, dev_char_addr, 5'b0, dev_char_rdata} :
|
||||
up_raddr_s[7:4] == `I3C_REGMAP_OFFLOAD_CMD_ ? offload_douta :
|
||||
up_raddr_s[7:4] == `I3C_REGMAP_OFFLOAD_SDO_ ? offload_douta :
|
||||
~|up_raddr_s[3:0] ? up_rdata_ff :
|
||||
up_rdata_ff;
|
||||
|
||||
ad_mem_dual #(
|
||||
.INITIALIZE(1),
|
||||
.DATA_WIDTH(4),
|
||||
.ADDRESS_WIDTH(7)
|
||||
) i_mem_dev_char (
|
||||
.clka(s_axi_aclk),
|
||||
.wea(dev_char_wea),
|
||||
.ea(1'b1),
|
||||
.addra(dev_char_addr),
|
||||
.dina(dev_char_wdata),
|
||||
.douta(dev_char_rdata),
|
||||
.clkb(s_axi_aclk),
|
||||
.web(1'b0),
|
||||
.eb(1'b1),
|
||||
.addrb(rmap_dev_char_addr),
|
||||
.dinb(),
|
||||
.doutb(rmap_dev_char_data));
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (dev_char_w) begin
|
||||
dev_char_addr_reg <= dev_char_addr;
|
||||
end
|
||||
end
|
||||
|
||||
assign dev_char_wdata = up_wdata_s[3:0];
|
||||
assign dev_char_addr = dev_char_w ? up_wdata_s[15:9] : dev_char_addr_reg;
|
||||
assign dev_char_rea = up_rreq_s == 1'b1 && (up_raddr_s[7:0] == `I3C_REGMAP_DEV_CHAR);
|
||||
assign dev_char_w = up_wreq_s == 1'b1 && (up_waddr_s[7:0] == `I3C_REGMAP_DEV_CHAR);
|
||||
assign dev_char_wea = dev_char_w && up_wdata_s[8];
|
||||
assign dev_char_ea = dev_char_rea | dev_char_wea;
|
||||
|
||||
generate if (OFFLOAD) begin
|
||||
localparam [1:0] SM_CMD_GET = 0;
|
||||
localparam [1:0] SM_CMD_PUT = 1;
|
||||
localparam [1:0] SM_SDO_GET = 2;
|
||||
localparam [1:0] SM_SDO_PUT = 3;
|
||||
|
||||
reg [1:0] sm;
|
||||
reg [3:0] k;
|
||||
reg [3:0] j;
|
||||
reg [9:0] offload_sdo_buffer_len;
|
||||
|
||||
wire offload_ea;
|
||||
wire offload_wea;
|
||||
wire offload_rea;
|
||||
wire [4:0] offload_addra;
|
||||
wire offload_eb;
|
||||
wire [4:0] offload_addrb;
|
||||
wire [31:0] offload_doutb;
|
||||
|
||||
ad_mem_dual #(
|
||||
.DATA_WIDTH(32),
|
||||
.ADDRESS_WIDTH(5)
|
||||
) i_mem_offload (
|
||||
.clka(s_axi_aclk),
|
||||
.wea(offload_wea),
|
||||
.ea(offload_ea),
|
||||
.addra(offload_addra),
|
||||
.dina(up_wdata_s),
|
||||
.douta(offload_douta),
|
||||
.clkb(s_axi_aclk),
|
||||
.web(1'b0),
|
||||
.eb(offload_eb),
|
||||
.addrb(offload_addrb),
|
||||
.dinb('d0),
|
||||
.doutb(offload_doutb));
|
||||
|
||||
assign offload_addra = up_wreq_s ?
|
||||
{up_waddr_s[6], up_waddr_s[3:0]} :
|
||||
{up_raddr_s[6], up_raddr_s[3:0]};
|
||||
assign offload_rea = up_rreq_s == 1'b1 &&
|
||||
(up_raddr_s[7:4] == `I3C_REGMAP_OFFLOAD_CMD_ |
|
||||
up_raddr_s[7:4] == `I3C_REGMAP_OFFLOAD_SDO_ );
|
||||
assign offload_wea = up_wreq_s == 1'b1 &&
|
||||
(up_waddr_s[7:4] == `I3C_REGMAP_OFFLOAD_CMD_ |
|
||||
up_waddr_s[7:4] == `I3C_REGMAP_OFFLOAD_SDO_ );
|
||||
assign offload_ea = offload_rea | offload_wea;
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (!a_reset_n | ~ops_mode | ops_offload_len == 0) begin
|
||||
offload_sdo_buffer_len <= 0;
|
||||
sm <= SM_CMD_GET;
|
||||
k <= 'd0;
|
||||
end else begin
|
||||
// The same BRAM provides both cmd and sdo,
|
||||
// therefore a request-like interface is used.
|
||||
if (sm[1] == 1'b0) begin
|
||||
j <= 0;
|
||||
end
|
||||
case (sm)
|
||||
SM_CMD_GET: begin
|
||||
if (offload_trigger | k != 0) begin
|
||||
sm <= SM_CMD_PUT;
|
||||
k <= k == ops_offload_len - 1 ? 0 : k + 1;
|
||||
end
|
||||
end
|
||||
SM_CMD_PUT: begin
|
||||
if (cmd_ready) begin
|
||||
sm <= SM_SDO_GET;
|
||||
if (~cmd[0]) begin
|
||||
offload_sdo_buffer_len <= cmd[19:10] + {9'd0, |cmd[9:8]};
|
||||
end
|
||||
end
|
||||
end
|
||||
SM_SDO_GET: begin
|
||||
sm <= SM_SDO_PUT;
|
||||
j <= j + 1;
|
||||
end
|
||||
SM_SDO_PUT: begin
|
||||
// New payload requested, check if is cmd or sdo.
|
||||
if (cmd_ready) begin
|
||||
sm <= SM_CMD_GET;
|
||||
end else if (sdo_ready) begin
|
||||
if (|offload_sdo_buffer_len) begin
|
||||
offload_sdo_buffer_len <= offload_sdo_buffer_len - 1;
|
||||
end
|
||||
sm <= SM_SDO_GET;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign offload_idle = sm == SM_CMD_GET & k == 0;
|
||||
assign offload_addrb = sm[1] == 1'b0 ? {1'b0,k} : {1'b1,j};
|
||||
assign offload_eb = sm[0] == 1'b0 & ops_mode;
|
||||
assign offload_cmd_valid = sm == SM_CMD_PUT;
|
||||
assign offload_sdo_valid = sm == SM_SDO_PUT & |offload_sdo_buffer_len;
|
||||
assign offload_cmd = offload_doutb;
|
||||
assign offload_sdo = offload_doutb;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
if (up_sw_resetn == 1'b0) begin
|
||||
daa_trigger_lock <= 1'b0;
|
||||
daa_pending <= 1'b0;
|
||||
cmdr_pending <= 1'b0;
|
||||
ibi_pending <= 1'b0;
|
||||
end else begin
|
||||
if (cmdr_fifo_valid == 1'b1) begin
|
||||
cmdr_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 &&
|
||||
up_waddr_s[7:0] == `I3C_REGMAP_IRQ_PENDING &&
|
||||
up_wdata_s[`I3C_REGMAP_IRQ_CMDR_PENDING] == 1'b1) begin
|
||||
cmdr_pending <= 1'b0;
|
||||
end
|
||||
if (ibi_fifo_valid == 1'b1) begin
|
||||
ibi_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 &&
|
||||
up_waddr_s[7:0] == `I3C_REGMAP_IRQ_PENDING &&
|
||||
up_wdata_s[`I3C_REGMAP_IRQ_IBI_PENDING] == 1'b1) begin
|
||||
ibi_pending <= 1'b0;
|
||||
end
|
||||
if (daa_trigger_lock == 1'b1) begin
|
||||
daa_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 &&
|
||||
up_waddr_s[7:0] == `I3C_REGMAP_IRQ_PENDING &&
|
||||
up_wdata_s[`I3C_REGMAP_IRQ_DAA_PENDING] == 1'b1) begin
|
||||
daa_pending <= 1'b0;
|
||||
end
|
||||
if (daa_trigger) begin
|
||||
daa_trigger_lock <= 1'b1;
|
||||
end else if (sdo_valid_w) begin
|
||||
daa_trigger_lock <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
generate if (ASYNC_CLK) begin
|
||||
wire a_reset;
|
||||
ad_rst i_resetn (
|
||||
.rst_async(up_sw_reset),
|
||||
.clk(clk),
|
||||
.rst(a_reset),
|
||||
.rstn());
|
||||
assign a_reset_n = ~a_reset;
|
||||
assign clk_1 = clk;
|
||||
end else begin /* ASYNC_CLK == 0 */
|
||||
assign a_reset_n = ~up_sw_reset;
|
||||
assign clk_1 = s_axi_aclk;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign cmd = ~ops_mode ? cmd_w : offload_cmd;
|
||||
assign cmd_valid = ~ops_mode ? cmd_valid_w : offload_cmd_valid;
|
||||
assign cmd_ready_w = ~ops_mode ? cmd_ready : 1'b0;
|
||||
assign cmd_fifo_valid = up_wreq_s == 1'b1 && up_waddr_s[7:0] == `I3C_REGMAP_CMD_FIFO;
|
||||
assign cmd_fifo_data = up_wdata_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ADDRESS_WIDTH(`ADDRESS_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_CLK),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(1)
|
||||
) i_cmd_fifo (
|
||||
.s_axis_aclk(s_axi_aclk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(cmd_fifo_ready),
|
||||
.s_axis_valid(cmd_fifo_valid),
|
||||
.s_axis_data(cmd_fifo_data),
|
||||
.s_axis_room(cmd_fifo_room),
|
||||
.s_axis_tlast(1'b0),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(),
|
||||
.m_axis_aclk(clk_1),
|
||||
.m_axis_aresetn(a_reset_n),
|
||||
.m_axis_ready(cmd_ready_w),
|
||||
.m_axis_valid(cmd_valid_w),
|
||||
.m_axis_data(cmd_w),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty(cmd_fifo_almost_empty),
|
||||
.m_axis_level());
|
||||
|
||||
assign cmdr_ready = ~ops_mode ? cmdr_ready_w : 1'b1; // In offload, discard cmdr
|
||||
assign cmdr_valid_w = ~ops_mode ? cmdr_valid : 1'b0;
|
||||
assign cmdr_fifo_ready = up_rreq_s == 1'b1 && up_raddr_s[7:0] == `I3C_REGMAP_CMDR_FIFO;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_CLK),
|
||||
.ADDRESS_WIDTH(`ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(31)
|
||||
) i_cmdr_fifo (
|
||||
.s_axis_aclk(clk_1),
|
||||
.s_axis_aresetn(a_reset_n),
|
||||
.s_axis_ready(cmdr_ready_w),
|
||||
.s_axis_valid(cmdr_valid_w),
|
||||
.s_axis_data(cmdr),
|
||||
.s_axis_room(),
|
||||
.s_axis_tlast(),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(cmdr_fifo_almost_full),
|
||||
.m_axis_aclk(s_axi_aclk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(cmdr_fifo_ready),
|
||||
.m_axis_valid(cmdr_fifo_valid),
|
||||
.m_axis_data(cmdr_fifo_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(cmdr_fifo_level),
|
||||
.m_axis_empty(cmdr_fifo_empty),
|
||||
.m_axis_almost_empty());
|
||||
|
||||
assign sdo = ~ops_mode ? sdo_w : offload_sdo;
|
||||
assign sdo_valid = ~ops_mode ? sdo_valid_w : offload_sdo_valid;
|
||||
assign sdo_ready_w = ~ops_mode ? sdo_ready : 1'b0;
|
||||
assign sdo_fifo_valid = up_wreq_s == 1'b1 && up_waddr_s[7:0] == `I3C_REGMAP_SDO_FIFO;
|
||||
assign sdo_fifo_data = up_wdata_s[31:0];
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_CLK),
|
||||
.ADDRESS_WIDTH(`ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(1)
|
||||
) i_sdo_fifo (
|
||||
.s_axis_aclk(s_axi_aclk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(sdo_fifo_ready),
|
||||
.s_axis_valid(sdo_fifo_valid),
|
||||
.s_axis_data(sdo_fifo_data),
|
||||
.s_axis_room(sdo_fifo_room),
|
||||
.s_axis_tlast(1'b0),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(),
|
||||
.m_axis_aclk(clk_1),
|
||||
.m_axis_aresetn(a_reset_n),
|
||||
.m_axis_ready(sdo_ready_w),
|
||||
.m_axis_valid(sdo_valid_w),
|
||||
.m_axis_data(sdo_w),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty(sdo_fifo_empty),
|
||||
.m_axis_almost_empty(sdo_fifo_almost_empty));
|
||||
|
||||
wire sdi_valid_w;
|
||||
wire sdi_ready_w;
|
||||
assign offload_sdi = sdi;
|
||||
assign offload_sdi_valid = ops_mode ? sdi_valid : 1'b0;
|
||||
assign sdi_valid_w = ~ops_mode ? sdi_valid : 1'b0;
|
||||
assign sdi_ready = ops_mode ? offload_sdi_ready : sdi_ready_w;
|
||||
assign sdi_fifo_ready = up_rreq_s == 1'b1 && up_raddr_s[7:0] == `I3C_REGMAP_SDI_FIFO;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_CLK),
|
||||
.ADDRESS_WIDTH(`ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(31)
|
||||
) i_sdi_fifo (
|
||||
.s_axis_aclk(clk_1),
|
||||
.s_axis_aresetn(a_reset_n),
|
||||
.s_axis_ready(sdi_ready_w),
|
||||
.s_axis_valid(sdi_valid_w),
|
||||
.s_axis_data(sdi),
|
||||
.s_axis_room(),
|
||||
.s_axis_tlast(),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(sdi_fifo_almost_full),
|
||||
.m_axis_aclk(s_axi_aclk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(sdi_fifo_ready),
|
||||
.m_axis_valid(sdi_fifo_valid),
|
||||
.m_axis_data(sdi_fifo_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(sdi_fifo_level),
|
||||
.m_axis_empty(sdi_fifo_empty),
|
||||
.m_axis_almost_empty());
|
||||
|
||||
assign ibi_fifo_ready = up_rreq_s == 1'b1 && up_raddr_s[7:0] == `I3C_REGMAP_IBI_FIFO;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_CLK),
|
||||
.ADDRESS_WIDTH(`ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(31)
|
||||
) i_ibi_fifo (
|
||||
.s_axis_aclk(clk_1),
|
||||
.s_axis_aresetn(a_reset_n),
|
||||
.s_axis_ready(ibi_ready),
|
||||
.s_axis_valid(ibi_valid),
|
||||
.s_axis_data(ibi),
|
||||
.s_axis_room(),
|
||||
.s_axis_tlast(),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(ibi_fifo_almost_full),
|
||||
.m_axis_aclk(s_axi_aclk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(ibi_fifo_ready),
|
||||
.m_axis_valid(ibi_fifo_valid),
|
||||
.m_axis_data(ibi_fifo_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(ibi_fifo_level),
|
||||
.m_axis_empty(ibi_fifo_empty),
|
||||
.m_axis_almost_empty());
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (6),
|
||||
.ASYNC_CLK (ASYNC_CLK)
|
||||
) i_fifo_status (
|
||||
.in_bits ({
|
||||
cmd_fifo_almost_empty, cmdr_fifo_almost_full, sdo_fifo_almost_empty,
|
||||
sdi_fifo_almost_full, ibi_fifo_almost_full, cmd_nop
|
||||
}),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (s_axi_aclk),
|
||||
.out_bits ({up_cmd_fifo_almost_empty, up_cmdr_fifo_almost_full,
|
||||
up_sdo_fifo_almost_empty, up_sdi_fifo_almost_full, up_ibi_fifo_almost_full,
|
||||
up_cmd_nop
|
||||
}));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,68 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`ifndef I3C_CONTROLLER_REGMAP_V
|
||||
`define I3C_CONTROLLER_REGMAP_V
|
||||
|
||||
`define I3C_REGMAP_VERSION 8'h00
|
||||
`define I3C_REGMAP_DEVICE_ID 8'h01
|
||||
`define I3C_REGMAP_SCRATCH 8'h02
|
||||
`define I3C_REGMAP_ENABLE 8'h10
|
||||
`define I3C_REGMAP_IRQ_MASK 8'h20
|
||||
`define I3C_REGMAP_IRQ_PENDING 8'h21
|
||||
`define I3C_REGMAP_IRQ_SOURCE 8'h22
|
||||
`define I3C_REGMAP_CMD_FIFO_ROOM 8'h30
|
||||
`define I3C_REGMAP_CMDR_FIFO_LEVEL 8'h31
|
||||
`define I3C_REGMAP_SDO_FIFO_ROOM 8'h32
|
||||
`define I3C_REGMAP_SDI_FIFO_LEVEL 8'h33
|
||||
`define I3C_REGMAP_IBI_FIFO_LEVEL 8'h34
|
||||
`define I3C_REGMAP_CMD_FIFO 8'h35
|
||||
`define I3C_REGMAP_CMDR_FIFO 8'h36
|
||||
`define I3C_REGMAP_SDO_FIFO 8'h37
|
||||
`define I3C_REGMAP_SDI_FIFO 8'h38
|
||||
`define I3C_REGMAP_IBI_FIFO 8'h39
|
||||
`define I3C_REGMAP_FIFO_STATUS 8'h3a
|
||||
`define I3C_REGMAP_OPS 8'h40
|
||||
`define I3C_REGMAP_IBI_CONFIG 8'h50
|
||||
`define I3C_REGMAP_DEV_CHAR 8'h60
|
||||
`define I3C_REGMAP_OFFLOAD_CMD_ 4'hb
|
||||
`define I3C_REGMAP_OFFLOAD_SDO_ 4'hc
|
||||
|
||||
`define I3C_REGMAP_IRQ_WIDTH 7
|
||||
`define I3C_REGMAP_IRQ_CMDR_PENDING 5
|
||||
`define I3C_REGMAP_IRQ_IBI_PENDING 6
|
||||
`define I3C_REGMAP_IRQ_DAA_PENDING 7
|
||||
|
||||
`endif
|
||||
@@ -0,0 +1,98 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
/**
|
||||
* Unpacks u32 packages into u8 stream.
|
||||
*/
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module i3c_controller_unpack (
|
||||
input clk,
|
||||
input reset_n,
|
||||
input stop,
|
||||
|
||||
output u32_ready,
|
||||
input u32_valid,
|
||||
input [31:0] u32,
|
||||
|
||||
output [11:0] u8_lvl,
|
||||
|
||||
input u8_ready,
|
||||
output u8_valid,
|
||||
output [7:0] u8
|
||||
);
|
||||
|
||||
localparam [0:0] SM_GET = 0;
|
||||
localparam [0:0] SM_PUT = 1;
|
||||
|
||||
reg [0:0] sm;
|
||||
reg [1:0] c;
|
||||
reg [11:0] u8_lvl_reg;
|
||||
reg [31:0] u32_reg;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!reset_n | stop) begin
|
||||
sm <= SM_GET;
|
||||
c <= 2'b00;
|
||||
u8_lvl_reg <= 0;
|
||||
end else begin
|
||||
case (sm)
|
||||
SM_GET: begin
|
||||
if (u32_valid) begin
|
||||
sm <= SM_PUT;
|
||||
end
|
||||
u32_reg <= u32;
|
||||
c <= 2'b00;
|
||||
end
|
||||
SM_PUT: begin
|
||||
if (u8_ready) begin // tick
|
||||
u8_lvl_reg <= u8_lvl_reg + 12'b1;
|
||||
c <= c + 1;
|
||||
if (c == 2'b11) begin
|
||||
sm <= SM_GET;
|
||||
end
|
||||
u32_reg <= u32_reg >> 8;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign u32_ready = sm == SM_GET & (reset_n | stop);
|
||||
assign u8_valid = sm == SM_PUT;
|
||||
assign u8_lvl = u8_lvl_reg;
|
||||
assign u8 = u32_reg[7:0];
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,82 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module i3c_controller_write_ibi (
|
||||
input clk,
|
||||
input reset_n,
|
||||
|
||||
input out_ready,
|
||||
output out_valid,
|
||||
output [31:0] out,
|
||||
|
||||
output in_ready,
|
||||
input in_valid,
|
||||
input [14:0] in
|
||||
);
|
||||
|
||||
reg [0:0] sm;
|
||||
|
||||
reg [6:0] da;
|
||||
reg [7:0] mdb;
|
||||
reg [7:0] sync;
|
||||
|
||||
localparam [0:0] SM_GET = 0;
|
||||
localparam [0:0] SM_PUT = 1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!reset_n) begin
|
||||
sm <= SM_GET;
|
||||
sync <= 8'd0;
|
||||
end else begin
|
||||
case (sm)
|
||||
SM_GET: begin
|
||||
sm <= in_valid ? SM_PUT : sm;
|
||||
da <= in[14:8];
|
||||
mdb <= in[7:0];
|
||||
end
|
||||
SM_PUT: begin
|
||||
sm <= out_ready ? SM_GET : sm;
|
||||
sync <= out_ready ? sync+1 : sync;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign out = {8'd0, da, 1'b0, mdb, sync};
|
||||
assign in_ready = sm == SM_GET;
|
||||
assign out_valid = sm == SM_PUT;
|
||||
endmodule
|
||||
+61
@@ -0,0 +1,61 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set I3C_Controller_Host_Interface [ipgui::add_page $IPINST -name "I3C Controller Host Interface" -display_name {AXI I3C Controller Host Interface}]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${I3C_Controller_Host_Interface}]
|
||||
set ID [ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ID] Core instance ID} ${ID}
|
||||
set ASYNC_CLK [ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_CLK}
|
||||
set OFFLOAD [ipgui::add_param $IPINST -name "OFFLOAD" -parent ${General_Configuration}]
|
||||
set_property tooltip {[OFFLOAD] Allows to offload output data to a external receiver, like a DMA} ${OFFLOAD}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to validate ASYNC_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OFFLOAD { PARAM_VALUE.OFFLOAD } {
|
||||
# Procedure called to update OFFLOAD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OFFLOAD { PARAM_VALUE.OFFLOAD } {
|
||||
# Procedure called to validate OFFLOAD
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OFFLOAD { MODELPARAM_VALUE.OFFLOAD PARAM_VALUE.OFFLOAD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OFFLOAD}] ${MODELPARAM_VALUE.OFFLOAD}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user