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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="d3e1001c6f6a4273955da0d13d53fb7b"/>
<Option Name="Id" Val="48dd613bd4ca48b89ed2c32714fcc0ba"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -311,21 +310,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -338,7 +337,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
+1 -1
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@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/jesd204/ad_ip_jesd204_tpl_adc/component.xml
+35 -33
View File
@@ -296,7 +296,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>caecda58</spirit:value>
<spirit:value>670acfc5</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -312,7 +312,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>649450b5</spirit:value>
<spirit:value>f78cc535</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1055,30 +1055,6 @@
<spirit:enumeration>12</spirit:enumeration>
<spirit:enumeration>16</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_00ecfe9a</spirit:name>
<spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
<spirit:enumeration spirit:text="rf">1</spirit:enumeration>
<spirit:enumeration spirit:text="fl">2</spirit:enumeration>
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<spirit:enumeration spirit:text="rb">12</spirit:enumeration>
<spirit:enumeration spirit:text="rs">13</spirit:enumeration>
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<spirit:enumeration spirit:text="ba">16</spirit:enumeration>
<spirit:enumeration spirit:text="fa">17</spirit:enumeration>
<spirit:enumeration spirit:text="fs">18</spirit:enumeration>
<spirit:enumeration spirit:text="fi">19</spirit:enumeration>
<spirit:enumeration spirit:text="vs">20</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_19f99f31</spirit:name>
<spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -1104,7 +1080,32 @@
<spirit:enumeration spirit:text="versal">4</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_fc01a186</spirit:name>
<spirit:name>choice_pairs_a6e6e044</spirit:name>
<spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
<spirit:enumeration spirit:text="rf">1</spirit:enumeration>
<spirit:enumeration spirit:text="fl">2</spirit:enumeration>
<spirit:enumeration spirit:text="ff">3</spirit:enumeration>
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<spirit:enumeration spirit:text="fg">10</spirit:enumeration>
<spirit:enumeration spirit:text="sb">11</spirit:enumeration>
<spirit:enumeration spirit:text="rb">12</spirit:enumeration>
<spirit:enumeration spirit:text="rs">13</spirit:enumeration>
<spirit:enumeration spirit:text="cl">14</spirit:enumeration>
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<spirit:name>choice_pairs_a897e79d</spirit:name>
<spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
<spirit:enumeration spirit:text="artix">1</spirit:enumeration>
<spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1112,6 +1113,7 @@
<spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
<spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
<spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
<spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
@@ -1208,7 +1210,7 @@
<spirit:file>
<spirit:name>ad_ip_jesd204_tpl_adc.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_cd763ccf</spirit:userFileType>
<spirit:userFileType>CHECKSUM_2ae5caad</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -1322,7 +1324,7 @@
<spirit:parameter>
<spirit:name>FPGA_FAMILY</spirit:name>
<spirit:displayName>Fpga Family</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SPEED_GRADE</spirit:name>
@@ -1332,7 +1334,7 @@
<spirit:parameter>
<spirit:name>DEV_PACKAGE</spirit:name>
<spirit:displayName>Dev Package</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_LANES</spirit:name>
@@ -1437,11 +1439,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_adc</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:40:08Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T02:55:52Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c47545eb"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8d6bb3cd"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="7bb43336"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="19ccb69d"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="f184678c"/>