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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/spi_engine/axi_spi_engine/Makefile
+3 -1
View File
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
@@ -22,6 +22,8 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_cdc
XILINX_INTERFACE_DEPS += spi_engine/interfaces
INTEL_DEPS += ../../common/ad_mem.v
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v
+11 -3
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -133,7 +133,7 @@ module axi_spi_engine #(
input [7:0] offload_sync_data
);
localparam PCORE_VERSION = 'h010071;
localparam PCORE_VERSION = 'h010200;
localparam S_AXI = 0;
localparam UP_FIFO = 1;
@@ -334,12 +334,20 @@ module axi_spi_engine #(
end
endgenerate
reg [7:0] offload_sdo_mem_address_width = OFFLOAD0_SDO_MEM_ADDRESS_WIDTH;
reg [7:0] offload_cmd_mem_address_width = OFFLOAD0_CMD_MEM_ADDRESS_WIDTH;
reg [7:0] sdi_fifo_address_width = SDI_FIFO_ADDRESS_WIDTH;
reg [7:0] sdo_fifo_address_width = SDO_FIFO_ADDRESS_WIDTH;
reg [7:0] sync_fifo_address_width = SYNC_FIFO_ADDRESS_WIDTH;
reg [7:0] cmd_fifo_address_width = CMD_FIFO_ADDRESS_WIDTH;
always @(posedge clk) begin
case (up_raddr_s)
8'h00: up_rdata_ff <= PCORE_VERSION;
8'h01: up_rdata_ff <= ID;
8'h02: up_rdata_ff <= up_scratch;
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
8'h04: up_rdata_ff <= {16'b0, offload_sdo_mem_address_width, offload_cmd_mem_address_width};
8'h05: up_rdata_ff <= {sdi_fifo_address_width, sdo_fifo_address_width, sync_fifo_address_width, cmd_fifo_address_width};
8'h10: up_rdata_ff <= up_sw_reset;
8'h20: up_rdata_ff <= up_irq_mask;
8'h21: up_rdata_ff <= up_irq_pending;
adi_library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="7614137f133e45a3b5014a3375bb1862"/>
<Option Name="Id" Val="a6c121ede1ae47db9f9ddbaf67411ed8"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -175,21 +174,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -202,7 +201,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl
-6
View File
@@ -109,12 +109,6 @@ proc p_elaboration {} {
}
ad_interface signal pulse_gen_period output 32
ad_interface signal pulse_gen_width output 32
ad_interface signal pulse_gen_load output 1
lappend disabled_intfs if_pulse_gen_period if_pulse_gen_width if_pulse_gen_load
foreach interface $disabled_intfs {
set_interface_property $interface ENABLED false
}
adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
+23 -24
View File
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -34,18 +34,18 @@ adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd_data" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync_data" "SYNC_DATA"} \
{"cmd_ready" "cmd_ready"} \
{"cmd_valid" "cmd_valid"} \
{"cmd_data" "cmd_data"} \
{"sdo_data_ready" "sdo_ready"} \
{"sdo_data_valid" "sdo_valid"} \
{"sdo_data" "sdo_data"} \
{"sdi_data_ready" "sdi_ready"} \
{"sdi_data_valid" "sdi_valid"} \
{"sdi_data" "sdi_data"} \
{"sync_ready" "sync_ready"} \
{"sync_valid" "sync_valid"} \
{"sync_data" "sync_data"} \
}
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master"
@@ -53,18 +53,17 @@ adi_add_bus "spi_engine_offload_ctrl0" "master" \
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
{ \
{ "offload0_cmd_wr_en" "CMD_WR_EN"} \
{ "offload0_cmd_wr_data" "CMD_WR_DATA"} \
{ "offload0_sdo_wr_en" "SDO_WR_EN"} \
{ "offload0_sdo_wr_data" "SDO_WR_DATA"} \
{ "offload0_enable" "ENABLE"} \
{ "offload0_enabled" "ENABLED"} \
{ "offload0_mem_reset" "MEM_RESET"} \
{ "offload_sync_ready" "SYNC_READY"} \
{ "offload_sync_valid" "SYNC_VALID"} \
{ "offload_sync_data" "SYNC_DATA"} \
{ "offload0_cmd_wr_en" "cmd_wr_en"} \
{ "offload0_cmd_wr_data" "cmd_wr_data"} \
{ "offload0_sdo_wr_en" "sdo_wr_en"} \
{ "offload0_sdo_wr_data" "sdo_wr_data"} \
{ "offload0_enable" "enable"} \
{ "offload0_enabled" "enabled"} \
{ "offload0_mem_reset" "mem_reset"} \
{ "offload_sync_ready" "sync_ready"} \
{ "offload_sync_valid" "sync_valid"} \
{ "offload_sync_data" "sync_data"} \
}
adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn"
foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} {
adi_library/spi_engine/axi_spi_engine/component.xml
+28 -28
View File
@@ -230,7 +230,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_READY</spirit:name>
<spirit:name>cmd_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_ready</spirit:name>
@@ -238,7 +238,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_VALID</spirit:name>
<spirit:name>cmd_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_valid</spirit:name>
@@ -246,7 +246,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_DATA</spirit:name>
<spirit:name>cmd_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_data</spirit:name>
@@ -254,7 +254,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_READY</spirit:name>
<spirit:name>sdo_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_ready</spirit:name>
@@ -262,7 +262,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_VALID</spirit:name>
<spirit:name>sdo_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_valid</spirit:name>
@@ -270,7 +270,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_DATA</spirit:name>
<spirit:name>sdo_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data</spirit:name>
@@ -278,7 +278,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_READY</spirit:name>
<spirit:name>sdi_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_ready</spirit:name>
@@ -286,7 +286,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_VALID</spirit:name>
<spirit:name>sdi_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_valid</spirit:name>
@@ -294,7 +294,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_DATA</spirit:name>
<spirit:name>sdi_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data</spirit:name>
@@ -302,7 +302,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_ready</spirit:name>
@@ -310,7 +310,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_valid</spirit:name>
@@ -318,7 +318,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_data</spirit:name>
@@ -384,7 +384,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_WR_EN</spirit:name>
<spirit:name>cmd_wr_en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_cmd_wr_en</spirit:name>
@@ -392,7 +392,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_WR_DATA</spirit:name>
<spirit:name>cmd_wr_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_cmd_wr_data</spirit:name>
@@ -400,7 +400,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_WR_EN</spirit:name>
<spirit:name>sdo_wr_en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_sdo_wr_en</spirit:name>
@@ -408,7 +408,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_WR_DATA</spirit:name>
<spirit:name>sdo_wr_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_sdo_wr_data</spirit:name>
@@ -416,7 +416,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ENABLE</spirit:name>
<spirit:name>enable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_enable</spirit:name>
@@ -424,7 +424,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ENABLED</spirit:name>
<spirit:name>enabled</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_enabled</spirit:name>
@@ -432,7 +432,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>MEM_RESET</spirit:name>
<spirit:name>mem_reset</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_mem_reset</spirit:name>
@@ -440,7 +440,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload_sync_ready</spirit:name>
@@ -448,7 +448,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload_sync_valid</spirit:name>
@@ -456,7 +456,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload_sync_data</spirit:name>
@@ -553,7 +553,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>1fd5eec0</spirit:value>
<spirit:value>01e9a617</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -575,7 +575,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>089a1d05</spirit:value>
<spirit:value>2c2a08bc</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1868,7 +1868,7 @@
<spirit:file>
<spirit:name>axi_spi_engine.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_6b9f989c</spirit:userFileType>
<spirit:userFileType>CHECKSUM_a04cf31b</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -2074,11 +2074,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:52:34Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:10:12Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="071f18c1"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="35a91dd8"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="ca848ee8"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e191cf5b"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="570013dc"/>
adi_library/spi_engine/interfaces/Makefile
+41
View File
@@ -0,0 +1,41 @@
####################################################################################
####################################################################################
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := interfaces_ip.tcl
M_DEPS += ../../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip_xilinx.tcl
M_VIVADO := vivado -mode batch -source
XML_FLIST := spi_engine.xml
XML_FLIST += spi_engine_rtl.xml
XML_FLIST += spi_engine_ctrl.xml
XML_FLIST += spi_engine_ctrl_rtl.xml
XML_FLIST += spi_engine_offload_ctrl.xml
XML_FLIST += spi_engine_offload_ctrl_rtl.xml
M_FLIST := *.log
M_FLIST += *.jou
M_FLIST += *.sv
M_FLIST += $(XML_FLIST)
.PHONY: all xilinx clean clean-all
all: xilinx
xilinx: $(XML_FLIST)
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
%.xml: $(M_DEPS)
$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
####################################################################################
####################################################################################
adi_library/spi_engine/interfaces/interfaces_ip.tcl
+47
View File
@@ -0,0 +1,47 @@
###############################################################################
## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
# SPI interface
adi_if_define "spi_engine"
adi_if_ports output 1 sclk
adi_if_ports output 1 sdo
adi_if_ports output 1 sdo_t
adi_if_ports input -1 sdi
adi_if_ports output -1 cs
adi_if_ports output 1 three_wire
# Control interface
adi_if_define "spi_engine_ctrl"
adi_if_ports input 1 cmd_ready
adi_if_ports output 1 cmd_valid
adi_if_ports output 16 cmd_data
adi_if_ports input 1 sdo_ready
adi_if_ports output 1 sdo_valid
adi_if_ports output -1 sdo_data
adi_if_ports output 1 sdi_ready
adi_if_ports input 1 sdi_valid
adi_if_ports input -1 sdi_data
adi_if_ports output 1 sync_ready
adi_if_ports input 1 sync_valid
adi_if_ports input 8 sync_data
# Offload control interface
adi_if_define "spi_engine_offload_ctrl"
adi_if_ports output 1 cmd_wr_en
adi_if_ports output 16 cmd_wr_data
adi_if_ports output 1 sdo_wr_en
adi_if_ports output -1 sdo_wr_data
adi_if_ports output 1 mem_reset
adi_if_ports output 1 enable
adi_if_ports input 1 enabled
adi_if_ports output 1 sync_ready
adi_if_ports input 1 sync_valid
adi_if_ports input 8 sync_data
adi_library/spi_engine/interfaces/spi_engine.xml
+11
View File
@@ -0,0 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>
adi_library/spi_engine/interfaces/spi_engine_ctrl.xml
+9 -11
View File
@@ -1,13 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>
adi_library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml
+172 -187
View File
@@ -1,189 +1,174 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_ctrl_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com"
spirit:library="interface"
spirit:name="spi_engine_ctrl"
spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>CMD_READY</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CMD_VALID</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CMD_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_READY</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_VALID</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_READY</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_VALID</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SYNC_READY</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SYNC_VALID</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SYNC_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_ctrl_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>cmd_ready</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>cmd_valid</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>cmd_data</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdo_ready</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdo_valid</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdo_data</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdi_ready</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdi_valid</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdi_data</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sync_ready</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sync_valid</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sync_data</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/spi_engine/interfaces/spi_engine_ctrl_v1_0.sv
+100
View File
@@ -0,0 +1,100 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`ifndef spi_engine_ctrl_v1_0
`define spi_engine_ctrl_v1_0
package parameter_structs;
typedef struct packed {
bit portEnabled;
integer portWidth;
}portConfig;
typedef struct packed {
// <typeName> <LogicalName> = {<enablement>, <width>}
portConfig sdo_data;
portConfig sdi_data;
}spi_engine_ctrl_v1_0_port_configuration;
parameter spi_engine_ctrl_v1_0_port_configuration spi_engine_ctrl_v1_0_default_port_configuration = '{sdo_data:'{1, -1}, sdi_data:'{1, -1}};
endpackage
interface spi_engine_ctrl_v1_0 #(parameter_structs::spi_engine_ctrl_v1_0_port_configuration port_configuration)();
logic cmd_ready; //
logic cmd_valid; //
logic [15:0] cmd_data; //
logic sdo_ready; //
logic sdo_valid; //
logic [port_configuration.sdo_data.portWidth-1:0] sdo_data; //
logic sdi_ready; //
logic sdi_valid; //
logic [port_configuration.sdi_data.portWidth-1:0] sdi_data; //
logic sync_ready; //
logic sync_valid; //
logic [7:0] sync_data; //
modport MASTER (
input cmd_ready, sdo_ready, sdi_valid, sdi_data, sync_valid, sync_data,
output cmd_valid, cmd_data, sdo_valid, sdo_data, sdi_ready, sync_ready
);
modport SLAVE (
input cmd_valid, cmd_data, sdo_valid, sdo_data, sdi_ready, sync_ready,
output cmd_ready, sdo_ready, sdi_valid, sdi_data, sync_valid, sync_data
);
modport MONITOR (
input cmd_ready, cmd_valid, cmd_data, sdo_ready, sdo_valid, sdo_data, sdi_ready, sdi_valid, sdi_data, sync_ready, sync_valid, sync_data
);
endinterface // spi_engine_ctrl_v1_0
`endif
adi_library/spi_engine/interfaces/spi_engine_offload_ctrl.xml
+9 -11
View File
@@ -1,13 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_offload_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_offload_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>
adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
+146 -156
View File
@@ -1,158 +1,148 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_offload_ctrl_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com"
spirit:library="interface"
spirit:name="spi_engine_offload_ctrl"
spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>CMD_WR_EN</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CMD_WR_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_WR_EN</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_WR_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>optional</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>ENABLE</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>MEM_RESET</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>ENABLED</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SYNC_READY</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SYNC_VALID</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SYNC_DATA</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_offload_ctrl_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>cmd_wr_en</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>cmd_wr_data</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>16</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdo_wr_en</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdo_wr_data</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>mem_reset</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>enable</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>enabled</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sync_ready</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sync_valid</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sync_data</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_v1_0.sv
+97
View File
@@ -0,0 +1,97 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`ifndef spi_engine_offload_ctrl_v1_0
`define spi_engine_offload_ctrl_v1_0
package parameter_structs;
typedef struct packed {
bit portEnabled;
integer portWidth;
}portConfig;
typedef struct packed {
// <typeName> <LogicalName> = {<enablement>, <width>}
portConfig sdo_wr_data;
}spi_engine_offload_ctrl_v1_0_port_configuration;
parameter spi_engine_offload_ctrl_v1_0_port_configuration spi_engine_offload_ctrl_v1_0_default_port_configuration = '{sdo_wr_data:'{1, -1}};
endpackage
interface spi_engine_offload_ctrl_v1_0 #(parameter_structs::spi_engine_offload_ctrl_v1_0_port_configuration port_configuration)();
logic cmd_wr_en; //
logic [15:0] cmd_wr_data; //
logic sdo_wr_en; //
logic [port_configuration.sdo_wr_data.portWidth-1:0] sdo_wr_data; //
logic mem_reset; //
logic enable; //
logic enabled; //
logic sync_ready; //
logic sync_valid; //
logic [7:0] sync_data; //
modport MASTER (
input enabled, sync_valid, sync_data,
output cmd_wr_en, cmd_wr_data, sdo_wr_en, sdo_wr_data, mem_reset, enable, sync_ready
);
modport SLAVE (
input cmd_wr_en, cmd_wr_data, sdo_wr_en, sdo_wr_data, mem_reset, enable, sync_ready,
output enabled, sync_valid, sync_data
);
modport MONITOR (
input cmd_wr_en, cmd_wr_data, sdo_wr_en, sdo_wr_data, mem_reset, enable, enabled, sync_ready, sync_valid, sync_data
);
endinterface // spi_engine_offload_ctrl_v1_0
`endif
adi_library/spi_engine/interfaces/spi_engine_rtl.xml
+90
View File
@@ -0,0 +1,90 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_engine_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>sclk</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdo</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdo_t</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sdi</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>cs</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>three_wire</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/spi_engine/interfaces/spi_engine_v1_0.sv
+94
View File
@@ -0,0 +1,94 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`ifndef spi_engine_v1_0
`define spi_engine_v1_0
package parameter_structs;
typedef struct packed {
bit portEnabled;
integer portWidth;
}portConfig;
typedef struct packed {
// <typeName> <LogicalName> = {<enablement>, <width>}
portConfig sdi;
portConfig cs;
}spi_engine_v1_0_port_configuration;
parameter spi_engine_v1_0_port_configuration spi_engine_v1_0_default_port_configuration = '{sdi:'{1, -1}, cs:'{1, -1}};
endpackage
interface spi_engine_v1_0 #(parameter_structs::spi_engine_v1_0_port_configuration port_configuration)();
logic sclk; //
logic sdo; //
logic sdo_t; //
logic [port_configuration.sdi.portWidth-1:0] sdi; //
logic [port_configuration.cs.portWidth-1:0] cs; //
logic three_wire; //
modport MASTER (
input sdi,
output sclk, sdo, sdo_t, cs, three_wire
);
modport SLAVE (
input sclk, sdo, sdo_t, cs, three_wire,
output sdi
);
modport MONITOR (
input sclk, sdo, sdo_t, sdi, cs, three_wire
);
endinterface // spi_engine_v1_0
`endif
adi_library/spi_engine/interfaces/spi_master.xml
-14
View File
@@ -1,14 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_master</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:description>SPI Engine physical interface</spirit:description>
</spirit:busDefinition>
adi_library/spi_engine/interfaces/spi_master_rtl.xml
-112
View File
@@ -1,112 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>spi_master_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com"
spirit:library="interface"
spirit:name="spi_master"
spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>SCLK</spirit:logicalName>
<spirit:description>SPI clock</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI</spirit:logicalName>
<spirit:description>Serial data in</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>optional</spirit:presence>
<spirit:direction>out</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO</spirit:logicalName>
<spirit:description>Serial data out</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDO_T</spirit:logicalName>
<spirit:description>Serial data out three state controle line</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>THREE_WIRE</spirit:logicalName>
<spirit:description>Three wire mode</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CS</spirit:logicalName>
<spirit:description>Chip select</spirit:description>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/spi_engine/scripts/spi_engine.tcl
+11 -3
View File
@@ -1,9 +1,9 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0}} {
proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}} {
puts "echo_sclk: $echo_sclk"
create_bd_cell -type hier $name
@@ -19,7 +19,7 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
create_bd_pin -dir I -type rst resetn
create_bd_pin -dir I trigger
create_bd_pin -dir O irq
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 m_spi
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
set execution "${name}_execution"
@@ -40,11 +40,19 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi
ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk
ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
ad_ip_parameter $axi_regmap CONFIG.SDI_FIFO_ADDRESS_WIDTH $sdi_fifo_addr_width
ad_ip_parameter $axi_regmap CONFIG.SDO_FIFO_ADDRESS_WIDTH $sdo_fifo_addr_width
ad_ip_parameter $axi_regmap CONFIG.SYNC_FIFO_ADDRESS_WIDTH $sync_fifo_addr_width
ad_ip_parameter $axi_regmap CONFIG.CMD_FIFO_ADDRESS_WIDTH $cmd_fifo_addr_width
ad_ip_instance spi_engine_offload $offload
ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width
ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK $async_spi_clk
ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi
ad_ip_parameter $offload CONFIG.CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
ad_ip_parameter $offload CONFIG.SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
ad_ip_instance spi_engine_interconnect $interconnect
ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
adi_library/spi_engine/spi_axis_reorder/Makefile
+1 -1
View File
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
adi_library/spi_engine/spi_axis_reorder/component.xml
+6 -6
View File
@@ -134,7 +134,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>6f89b3dc</spirit:value>
<spirit:value>d53c278f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -150,7 +150,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>6f89b3dc</spirit:value>
<spirit:value>d53c278f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -300,7 +300,7 @@
<spirit:file>
<spirit:name>spi_axis_reorder.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_6f89b3dc</spirit:userFileType>
<spirit:userFileType>CHECKSUM_d53c278f</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -370,11 +370,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:52:42Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:10:20Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a930cd95"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="afbeddb7"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="db78853a"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="197f2558"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="f0fce92c"/>
adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="e752d664dfd2410e84c9f4ba2321dd08"/>
<Option Name="Id" Val="3fc861695bd64c55a3491830fcd815ba"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -181,7 +180,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/spi_engine/spi_engine_execution/Makefile
+5 -3
View File
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
@@ -11,10 +11,12 @@ GENERIC_DEPS += spi_engine_execution.v
XILINX_DEPS += spi_engine_execution_constr.ttcl
XILINX_DEPS += spi_engine_execution_ip.tcl
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_master.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_rtl.xml
XILINX_INTERFACE_DEPS += spi_engine/interfaces
INTEL_DEPS += spi_engine_execution_hw.tcl
adi_library/spi_engine/spi_engine_execution/component.xml
+27 -33
View File
@@ -13,7 +13,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_READY</spirit:name>
<spirit:name>cmd_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_ready</spirit:name>
@@ -21,7 +21,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_VALID</spirit:name>
<spirit:name>cmd_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_valid</spirit:name>
@@ -29,7 +29,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_DATA</spirit:name>
<spirit:name>cmd_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd</spirit:name>
@@ -37,7 +37,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_READY</spirit:name>
<spirit:name>sdo_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_ready</spirit:name>
@@ -45,7 +45,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_VALID</spirit:name>
<spirit:name>sdo_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_valid</spirit:name>
@@ -53,7 +53,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_DATA</spirit:name>
<spirit:name>sdo_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data</spirit:name>
@@ -61,7 +61,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_READY</spirit:name>
<spirit:name>sdi_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_ready</spirit:name>
@@ -69,7 +69,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_VALID</spirit:name>
<spirit:name>sdi_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_valid</spirit:name>
@@ -77,7 +77,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_DATA</spirit:name>
<spirit:name>sdi_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data</spirit:name>
@@ -85,7 +85,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_ready</spirit:name>
@@ -93,7 +93,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_valid</spirit:name>
@@ -101,7 +101,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync</spirit:name>
@@ -161,13 +161,13 @@
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>spi</spirit:name>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master_rtl" spirit:version="1.0"/>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SCLK</spirit:name>
<spirit:name>sclk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sclk</spirit:name>
@@ -175,7 +175,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI</spirit:name>
<spirit:name>sdi</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi</spirit:name>
@@ -183,7 +183,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO</spirit:name>
<spirit:name>sdo</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo</spirit:name>
@@ -191,7 +191,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_T</spirit:name>
<spirit:name>sdo_t</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_t</spirit:name>
@@ -199,7 +199,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>THREE_WIRE</spirit:name>
<spirit:name>three_wire</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>three_wire</spirit:name>
@@ -207,7 +207,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CS</spirit:name>
<spirit:name>cs</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cs</spirit:name>
@@ -280,7 +280,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>4f3438ce</spirit:value>
<spirit:value>8ce35280</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -296,7 +296,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>4f3438ce</spirit:value>
<spirit:value>8ce35280</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -442,9 +442,6 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
@@ -613,9 +610,6 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
@@ -716,7 +710,7 @@
<spirit:file>
<spirit:name>spi_engine_execution.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_4f3438ce</spirit:userFileType>
<spirit:userFileType>CHECKSUM_8ce35280</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -797,12 +791,12 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:52:49Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:10:29Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b4974010"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="c2e40dde"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7c5528bd"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="17dd883f"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0dd4e337"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="0194bdcd"/>
</xilinx:packagingInfo>
adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v
+45 -24
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -76,10 +76,11 @@ module spi_engine_execution #(
output reg three_wire
);
localparam CMD_TRANSFER = 2'b00;
localparam CMD_CHIPSELECT = 2'b01;
localparam CMD_WRITE = 2'b10;
localparam CMD_MISC = 2'b11;
localparam CMD_TRANSFER = 3'b000;
localparam CMD_CHIPSELECT = 3'b001;
localparam CMD_WRITE = 3'b010;
localparam CMD_MISC = 3'b011;
localparam CMD_CS_INV = 3'b100;
localparam MISC_SYNC = 1'b0;
localparam MISC_SLEEP = 1'b1;
@@ -134,6 +135,8 @@ module spi_engine_execution #(
reg cpol = DEFAULT_SPI_CFG[1];
reg [7:0] clk_div = DEFAULT_CLK_DIV;
reg [NUM_OF_CS-1:0] cs_inv_mask_reg = 'h0;
reg sdo_enabled = 1'b0;
reg sdi_enabled = 1'b0;
@@ -141,12 +144,12 @@ module spi_engine_execution #(
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
wire [1:0] inst = cmd[13:12];
wire [1:0] inst_d1 = cmd_d1[13:12];
wire [2:0] inst = cmd[14:12];
wire [2:0] inst_d1 = cmd_d1[14:12];
wire exec_cmd = cmd_ready && cmd_valid;
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
wire exec_cs_inv_cmd = exec_cmd && inst == CMD_CS_INV;
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
@@ -159,6 +162,7 @@ module spi_engine_execution #(
wire cs_sleep_counter_compare;
wire cs_sleep_early_exit;
reg cs_sleep_repeat;
reg cs_active;
wire io_ready1;
wire io_ready2;
@@ -305,11 +309,21 @@ module spi_engine_execution #(
end
end
always @(posedge clk ) begin
if (resetn == 1'b0) begin
cs_inv_mask_reg <= 'h0;
end else begin
if (exec_cs_inv_cmd == 1'b1) begin
cs_inv_mask_reg <= cmd[NUM_OF_CS-1:0];
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
cs <= 'hff;
end else if (cs_gen) begin
cs <= cmd_d1[NUM_OF_CS-1:0];
cs <= cmd_d1[NUM_OF_CS-1:0]^cs_inv_mask_reg[NUM_OF_CS-1:0];
end
end
@@ -420,7 +434,14 @@ module spi_engine_execution #(
// used to latch the MISO lines, improving the overall timing margin of the
// interface.
wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
always @(posedge clk) begin
if (!resetn) begin // set cs_active during reset for a cycle to clear shift reg
cs_active <= 1;
end else begin
cs_active <= ~(&cmd_d1[NUM_OF_CS-1:0]) & cs_gen;
end
end
genvar i;
// NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point
@@ -438,8 +459,8 @@ module spi_engine_execution #(
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
reg [DATA_WIDTH-1:0] data_sdi_shift;
always @(negedge echo_sclk or posedge cs_active_s) begin
if (cs_active_s) begin
always @(negedge echo_sclk or posedge cs_active) begin
if (cs_active) begin
data_sdi_shift <= 0;
end else begin
data_sdi_shift <= {data_sdi_shift, sdi[i]};
@@ -454,8 +475,8 @@ module spi_engine_execution #(
end
always @(posedge echo_sclk or posedge cs_active_s) begin
if (cs_active_s == 1'b1) begin
always @(posedge echo_sclk or posedge cs_active) begin
if (cs_active) begin
sdi_counter <= 8'b0;
sdi_counter_d <= 8'b0;
end else begin
@@ -469,8 +490,8 @@ module spi_engine_execution #(
// MISO shift register runs on positive echo_sclk
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
reg [DATA_WIDTH-1:0] data_sdi_shift;
always @(posedge echo_sclk or posedge cs_active_s) begin
if (cs_active_s) begin
always @(posedge echo_sclk or posedge cs_active) begin
if (cs_active) begin
data_sdi_shift <= 0;
end else begin
data_sdi_shift <= {data_sdi_shift, sdi[i]};
@@ -483,8 +504,8 @@ module spi_engine_execution #(
end
end
always @(posedge echo_sclk or posedge cs_active_s) begin
if (cs_active_s == 1'b1) begin
always @(posedge echo_sclk or posedge cs_active) begin
if (cs_active) begin
sdi_counter <= 8'b0;
sdi_counter_d <= 8'b0;
end else begin
@@ -503,7 +524,7 @@ module spi_engine_execution #(
reg [3:0] last_sdi_bit_m = 4'b0;
always @(posedge clk) begin
if (cs_active_s) begin
if (cs_active) begin
last_sdi_bit_m <= 4'b0;
end else begin
last_sdi_bit_m <= {last_sdi_bit_m, last_sdi_bit};
@@ -511,7 +532,7 @@ module spi_engine_execution #(
end
always @(posedge clk) begin
if (cs_active_s) begin
if (cs_active) begin
sdi_data_valid <= 1'b0;
end else if (sdi_enabled == 1'b1 &&
last_sdi_bit_m[3] == 1'b0 &&
@@ -523,7 +544,7 @@ module spi_engine_execution #(
end
always @(posedge clk) begin
if (cs_active_s) begin
if (cs_active) begin
num_of_transfers <= 8'b0;
end else begin
if (cmd_d1[15:12] == 4'b0) begin
@@ -533,7 +554,7 @@ module spi_engine_execution #(
end
always @(posedge clk) begin
if (cs_active_s) begin
if (cs_active) begin
sdi_transfer_counter <= 0;
end else if (last_sdi_bit_m[2] == 1'b0 &&
last_sdi_bit_m[1] == 1'b1) begin
@@ -554,7 +575,7 @@ module spi_engine_execution #(
reg [DATA_WIDTH-1:0] data_sdi_shift;
always @(posedge clk) begin
if (cs_active_s) begin
if (cs_active) begin
data_sdi_shift <= 0;
end else begin
if (trigger_rx_s == 1'b1) begin
adi_library/spi_engine/spi_engine_execution/spi_engine_execution.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_execution/spi_engine_execution.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_engine_execution/spi_engine_execution.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="1f06667fc09742279c2aaecc7fa6d70e"/>
<Option Name="Id" Val="00911a71ecb04d8a81905b8675308ae8"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -155,21 +154,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -182,7 +181,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
+21 -21
View File
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -26,31 +26,31 @@ adi_add_bus "ctrl" "slave" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync" "SYNC_DATA"} \
{"cmd_ready" "cmd_ready"} \
{"cmd_valid" "cmd_valid"} \
{"cmd" "cmd_data"} \
{"sdo_data_ready" "sdo_ready"} \
{"sdo_data_valid" "sdo_valid"} \
{"sdo_data" "sdo_data"} \
{"sdi_data_ready" "sdi_ready"} \
{"sdi_data_valid" "sdi_valid"} \
{"sdi_data" "sdi_data"} \
{"sync_ready" "sync_ready"} \
{"sync_valid" "sync_valid"} \
{"sync" "sync_data"} \
}
adi_add_bus_clock "clk" "ctrl" "resetn"
adi_add_bus "spi" "master" \
"analog.com:interface:spi_master_rtl:1.0" \
"analog.com:interface:spi_master:1.0" \
"analog.com:interface:spi_engine_rtl:1.0" \
"analog.com:interface:spi_engine:1.0" \
{
{"sclk" "SCLK"} \
{"sdi" "SDI"} \
{"sdo" "SDO"} \
{"sdo_t" "SDO_T"} \
{"three_wire" "THREE_WIRE"} \
{"cs" "CS"} \
{"sclk" "sclk"} \
{"sdi" "sdi"} \
{"sdo" "sdo"} \
{"sdo_t" "sdo_t"} \
{"three_wire" "three_wire"} \
{"cs" "cs"} \
}
adi_add_bus_clock "clk" "spi" "resetn"
adi_library/spi_engine/spi_engine_interconnect/Makefile
+3 -1
View File
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
@@ -13,6 +13,8 @@ XILINX_DEPS += spi_engine_interconnect_ip.tcl
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_INTERFACE_DEPS += spi_engine/interfaces
INTEL_DEPS += spi_engine_interconnect_hw.tcl
include ../../scripts/library.mk
adi_library/spi_engine/spi_engine_interconnect/component.xml
+43 -52
View File
@@ -13,7 +13,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_READY</spirit:name>
<spirit:name>cmd_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_cmd_ready</spirit:name>
@@ -21,7 +21,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_VALID</spirit:name>
<spirit:name>cmd_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_cmd_valid</spirit:name>
@@ -29,7 +29,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_DATA</spirit:name>
<spirit:name>cmd_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_cmd_data</spirit:name>
@@ -37,7 +37,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_READY</spirit:name>
<spirit:name>sdo_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_sdo_ready</spirit:name>
@@ -45,7 +45,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_VALID</spirit:name>
<spirit:name>sdo_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_sdo_valid</spirit:name>
@@ -53,7 +53,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_DATA</spirit:name>
<spirit:name>sdo_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_sdo_data</spirit:name>
@@ -61,7 +61,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_READY</spirit:name>
<spirit:name>sdi_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_sdi_ready</spirit:name>
@@ -69,7 +69,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_VALID</spirit:name>
<spirit:name>sdi_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_sdi_valid</spirit:name>
@@ -77,7 +77,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_DATA</spirit:name>
<spirit:name>sdi_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_sdi_data</spirit:name>
@@ -85,7 +85,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_sync_ready</spirit:name>
@@ -93,7 +93,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_sync_valid</spirit:name>
@@ -101,7 +101,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_sync</spirit:name>
@@ -167,7 +167,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_READY</spirit:name>
<spirit:name>cmd_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_cmd_ready</spirit:name>
@@ -175,7 +175,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_VALID</spirit:name>
<spirit:name>cmd_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_cmd_valid</spirit:name>
@@ -183,7 +183,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_DATA</spirit:name>
<spirit:name>cmd_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_cmd_data</spirit:name>
@@ -191,7 +191,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_READY</spirit:name>
<spirit:name>sdo_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_sdo_ready</spirit:name>
@@ -199,7 +199,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_VALID</spirit:name>
<spirit:name>sdo_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_sdo_valid</spirit:name>
@@ -207,7 +207,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_DATA</spirit:name>
<spirit:name>sdo_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_sdo_data</spirit:name>
@@ -215,7 +215,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_READY</spirit:name>
<spirit:name>sdi_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_sdi_ready</spirit:name>
@@ -223,7 +223,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_VALID</spirit:name>
<spirit:name>sdi_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_sdi_valid</spirit:name>
@@ -231,7 +231,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_DATA</spirit:name>
<spirit:name>sdi_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_sdi_data</spirit:name>
@@ -239,7 +239,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_sync_ready</spirit:name>
@@ -247,7 +247,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_sync_valid</spirit:name>
@@ -255,7 +255,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s0_sync</spirit:name>
@@ -321,7 +321,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_READY</spirit:name>
<spirit:name>cmd_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_cmd_ready</spirit:name>
@@ -329,7 +329,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_VALID</spirit:name>
<spirit:name>cmd_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_cmd_valid</spirit:name>
@@ -337,7 +337,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_DATA</spirit:name>
<spirit:name>cmd_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_cmd_data</spirit:name>
@@ -345,7 +345,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_READY</spirit:name>
<spirit:name>sdo_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_sdo_ready</spirit:name>
@@ -353,7 +353,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_VALID</spirit:name>
<spirit:name>sdo_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_sdo_valid</spirit:name>
@@ -361,7 +361,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_DATA</spirit:name>
<spirit:name>sdo_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_sdo_data</spirit:name>
@@ -369,7 +369,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_READY</spirit:name>
<spirit:name>sdi_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_sdi_ready</spirit:name>
@@ -377,7 +377,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_VALID</spirit:name>
<spirit:name>sdi_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_sdi_valid</spirit:name>
@@ -385,7 +385,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_DATA</spirit:name>
<spirit:name>sdi_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_sdi_data</spirit:name>
@@ -393,7 +393,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_sync_ready</spirit:name>
@@ -401,7 +401,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_sync_valid</spirit:name>
@@ -409,7 +409,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s1_sync</spirit:name>
@@ -482,7 +482,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>d4ae3839</spirit:value>
<spirit:value>e614a53f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -498,7 +498,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>d4ae3839</spirit:value>
<spirit:value>e614a53f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -687,9 +687,6 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
@@ -884,9 +881,6 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
@@ -1065,9 +1059,6 @@
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
@@ -1107,7 +1098,7 @@
<spirit:file>
<spirit:name>spi_engine_interconnect.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_d4ae3839</spirit:userFileType>
<spirit:userFileType>CHECKSUM_e614a53f</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -1182,12 +1173,12 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/interconnect</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:52:56Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:10:37Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0b7a3255"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="c4f8ac06"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="decb81c1"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="6faa013d"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9165e5ab"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="c4388edd"/>
</xilinx:packagingInfo>
adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="d07593d6329248f7b3897d72eb22855e"/>
<Option Name="Id" Val="6694bc3256f740b39a40b8b208e5d73a"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -181,7 +180,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl
+24 -24
View File
@@ -24,18 +24,18 @@ adi_add_bus "m_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{ \
{"m_cmd_ready" "CMD_READY"} \
{"m_cmd_valid" "CMD_VALID"} \
{"m_cmd_data" "CMD_DATA"} \
{"m_sdo_ready" "SDO_READY"} \
{"m_sdo_valid" "SDO_VALID"} \
{"m_sdo_data" "SDO_DATA"} \
{"m_sdi_ready" "SDI_READY"} \
{"m_sdi_valid" "SDI_VALID"} \
{"m_sdi_data" "SDI_DATA"} \
{"m_sync_ready" "SYNC_READY"} \
{"m_sync_valid" "SYNC_VALID"} \
{"m_sync" "SYNC_DATA"} \
{"m_cmd_ready" "cmd_ready"} \
{"m_cmd_valid" "cmd_valid"} \
{"m_cmd_data" "cmd_data"} \
{"m_sdo_ready" "sdo_ready"} \
{"m_sdo_valid" "sdo_valid"} \
{"m_sdo_data" "sdo_data"} \
{"m_sdi_ready" "sdi_ready"} \
{"m_sdi_valid" "sdi_valid"} \
{"m_sdi_data" "sdi_data"} \
{"m_sync_ready" "sync_ready"} \
{"m_sync_valid" "sync_valid"} \
{"m_sync" "sync_data"} \
}
adi_add_bus_clock "clk" "m_ctrl" "resetn"
@@ -44,18 +44,18 @@ foreach prefix [list "s0" "s1"] {
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
[list \
[list [format "%s_cmd_ready" $prefix] "CMD_READY"] \
[list [format "%s_cmd_valid" $prefix] "CMD_VALID"] \
[list [format "%s_cmd_data" $prefix] "CMD_DATA"] \
[list [format "%s_sdo_ready" $prefix] "SDO_READY"] \
[list [format "%s_sdo_valid" $prefix] "SDO_VALID"] \
[list [format "%s_sdo_data" $prefix] "SDO_DATA"] \
[list [format "%s_sdi_ready" $prefix] "SDI_READY"] \
[list [format "%s_sdi_valid" $prefix] "SDI_VALID"] \
[list [format "%s_sdi_data" $prefix] "SDI_DATA"] \
[list [format "%s_sync_ready" $prefix] "SYNC_READY"] \
[list [format "%s_sync_valid" $prefix] "SYNC_VALID"] \
[list [format "%s_sync" $prefix] "SYNC_DATA"] \
[list [format "%s_cmd_ready" $prefix] "cmd_ready"] \
[list [format "%s_cmd_valid" $prefix] "cmd_valid"] \
[list [format "%s_cmd_data" $prefix] "cmd_data"] \
[list [format "%s_sdo_ready" $prefix] "sdo_ready"] \
[list [format "%s_sdo_valid" $prefix] "sdo_valid"] \
[list [format "%s_sdo_data" $prefix] "sdo_data"] \
[list [format "%s_sdi_ready" $prefix] "sdi_ready"] \
[list [format "%s_sdi_valid" $prefix] "sdi_valid"] \
[list [format "%s_sdi_data" $prefix] "sdi_data"] \
[list [format "%s_sync_ready" $prefix] "sync_ready"] \
[list [format "%s_sync_valid" $prefix] "sync_valid"] \
[list [format "%s_sync" $prefix] "sync_data"] \
]
adi_add_bus_clock "clk" [format "%s_ctrl" $prefix] "resetn"
}
adi_library/spi_engine/spi_engine_offload/Makefile
+4 -1
View File
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
@@ -18,7 +18,10 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_cdc
XILINX_INTERFACE_DEPS += spi_engine/interfaces
INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../../util_cdc/sync_event.v
INTEL_DEPS += spi_engine_offload_hw.tcl
include ../../scripts/library.mk
adi_library/spi_engine/spi_engine_offload/component.xml
+28 -28
View File
@@ -13,7 +13,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_READY</spirit:name>
<spirit:name>cmd_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_ready</spirit:name>
@@ -21,7 +21,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_VALID</spirit:name>
<spirit:name>cmd_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_valid</spirit:name>
@@ -29,7 +29,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_DATA</spirit:name>
<spirit:name>cmd_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd</spirit:name>
@@ -37,7 +37,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_READY</spirit:name>
<spirit:name>sdo_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_ready</spirit:name>
@@ -45,7 +45,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_VALID</spirit:name>
<spirit:name>sdo_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_valid</spirit:name>
@@ -53,7 +53,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_DATA</spirit:name>
<spirit:name>sdo_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data</spirit:name>
@@ -61,7 +61,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_READY</spirit:name>
<spirit:name>sdi_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_ready</spirit:name>
@@ -69,7 +69,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_VALID</spirit:name>
<spirit:name>sdi_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_valid</spirit:name>
@@ -77,7 +77,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_DATA</spirit:name>
<spirit:name>sdi_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data</spirit:name>
@@ -85,7 +85,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_ready</spirit:name>
@@ -93,7 +93,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_valid</spirit:name>
@@ -101,7 +101,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_data</spirit:name>
@@ -117,7 +117,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_WR_EN</spirit:name>
<spirit:name>cmd_wr_en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_cmd_wr_en</spirit:name>
@@ -125,7 +125,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_WR_DATA</spirit:name>
<spirit:name>cmd_wr_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_cmd_wr_data</spirit:name>
@@ -133,7 +133,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_WR_EN</spirit:name>
<spirit:name>sdo_wr_en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_sdo_wr_en</spirit:name>
@@ -141,7 +141,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_WR_DATA</spirit:name>
<spirit:name>sdo_wr_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_sdo_wr_data</spirit:name>
@@ -149,7 +149,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ENABLE</spirit:name>
<spirit:name>enable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_enable</spirit:name>
@@ -157,7 +157,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ENABLED</spirit:name>
<spirit:name>enabled</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_enabled</spirit:name>
@@ -165,7 +165,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>MEM_RESET</spirit:name>
<spirit:name>mem_reset</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_mem_reset</spirit:name>
@@ -173,7 +173,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>status_sync_ready</spirit:name>
@@ -181,7 +181,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>status_sync_valid</spirit:name>
@@ -189,7 +189,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>status_sync_data</spirit:name>
@@ -320,7 +320,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>54da56d5</spirit:value>
<spirit:value>415947b9</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -339,7 +339,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>54da56d5</spirit:value>
<spirit:value>415947b9</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -842,7 +842,7 @@
<spirit:file>
<spirit:name>spi_engine_offload.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_54da56d5</spirit:userFileType>
<spirit:userFileType>CHECKSUM_415947b9</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -941,11 +941,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:53:04Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:10:45Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8689cb20"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="582124d3"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="2756ddd5"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ae1a9eae"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="e2e1ec4a"/>
adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v
+33 -20
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -96,9 +96,12 @@ module spi_engine_offload #(
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
reg trigger_last_reg;
wire [15:0] cmd_int_s;
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
wire spi_enable;
wire trigger_posedge;
assign cmd_valid = spi_active;
assign sdo_data_valid = spi_active;
@@ -126,7 +129,7 @@ module spi_engine_offload #(
wire [ 7:0] spi_sync_id_init_s;
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1) begin
if (ctrl_mem_reset) begin
ctrl_sync_id_init <= 8'b0;
ctrl_sync_id_load <= 1'b0;
end else begin
@@ -160,7 +163,7 @@ module spi_engine_offload #(
.out_bits(spi_sync_id_init_s));
always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin
if (!spi_resetn) begin
spi_sync_id_counter <= 8'b0;
end else begin
if (spi_sync_id_load_s) begin
@@ -198,9 +201,9 @@ module spi_engine_offload #(
reg spi_enabled = 1'b0;
always @(posedge ctrl_clk) begin
if (ctrl_enable == 1'b1) begin
if (ctrl_enable) begin
ctrl_do_enable <= 1'b1;
end else if (ctrl_is_enabled == 1'b1) begin
end else if (ctrl_is_enabled) begin
ctrl_do_enable <= 1'b0;
end
end
@@ -247,57 +250,67 @@ module spi_engine_offload #(
.out_bits(trigger_s));
always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin
if (!spi_resetn) begin
trigger_last_reg <= 1'b0;
end else begin
trigger_last_reg <= trigger_s;
end
end
assign trigger_posedge = trigger_s && !trigger_last_reg;
always @(posedge spi_clk) begin
if (!spi_resetn) begin
spi_active <= 1'b0;
end else begin
if (spi_active == 1'b0) begin
if (!spi_active) begin
// start offload when we have a valid trigger, offload is enabled and
// the DMA is enabled
if (trigger_s == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1)
if (trigger_posedge && spi_enable && offload_sdi_ready)
spi_active <= 1'b1;
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
end else if (cmd_ready && (spi_cmd_rd_addr_next == ctrl_cmd_wr_addr)) begin
spi_active <= 1'b0;
end
end
end
always @(posedge spi_clk) begin
if (cmd_valid == 1'b0) begin
if (!cmd_valid) begin
spi_cmd_rd_addr <= 'h00;
end else if (cmd_ready == 1'b1) begin
end else if (cmd_ready) begin
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
end
end
always @(posedge spi_clk) begin
if (spi_active == 1'b0) begin
if (!spi_active) begin
spi_sdo_rd_addr <= 'h00;
end else if (sdo_data_ready == 1'b1) begin
end else if (sdo_data_ready) begin
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
end
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
if (ctrl_mem_reset)
ctrl_cmd_wr_addr <= 'h00;
else if (ctrl_cmd_wr_en == 1'b1)
else if (ctrl_cmd_wr_en)
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_cmd_wr_en == 1'b1)
if (ctrl_cmd_wr_en)
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
if (ctrl_mem_reset)
ctrl_sdo_wr_addr <= 'h00;
else if (ctrl_sdo_wr_en == 1'b1)
else if (ctrl_sdo_wr_en)
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_sdo_wr_en == 1'b1)
if (ctrl_sdo_wr_en)
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
end
adi_library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="30b4a7c406754ea493b787146654d616"/>
<Option Name="Id" Val="36637aefd0314394950d6379054a8d3c"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -155,21 +154,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -182,7 +181,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl
+1
View File
@@ -10,6 +10,7 @@ source ../../scripts/adi_ip_intel.tcl
ad_ip_create spi_engine_offload {SPI Engine Offload} p_elaboration
ad_ip_files spi_engine_offload [list\
$ad_hdl_dir/library/util_cdc/sync_bits.v \
$ad_hdl_dir/library/util_cdc/sync_event.v \
spi_engine_offload.v]
# parameters
adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
+22 -22
View File
@@ -32,34 +32,34 @@ adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync_data" "SYNC_DATA"} \
{"cmd_ready" "cmd_ready"} \
{"cmd_valid" "cmd_valid"} \
{"cmd" "cmd_data"} \
{"sdo_data_ready" "sdo_ready"} \
{"sdo_data_valid" "sdo_valid"} \
{"sdo_data" "sdo_data"} \
{"sdi_data_ready" "sdi_ready"} \
{"sdi_data_valid" "sdi_valid"} \
{"sdi_data" "sdi_data"} \
{"sync_ready" "sync_ready"} \
{"sync_valid" "sync_valid"} \
{"sync_data" "sync_data"} \
}
adi_add_bus "spi_engine_offload_ctrl" "slave" \
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
{ \
{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
{ "ctrl_sdo_wr_en" "SDO_WR_EN"} \
{ "ctrl_sdo_wr_data" "SDO_WR_DATA"} \
{ "ctrl_enable" "ENABLE"} \
{ "ctrl_enabled" "ENABLED"} \
{ "ctrl_mem_reset" "MEM_RESET"} \
{ "status_sync_ready" "SYNC_READY"} \
{ "status_sync_valid" "SYNC_VALID"} \
{ "status_sync_data" "SYNC_DATA"} \
{ "ctrl_cmd_wr_en" "cmd_wr_en"} \
{ "ctrl_cmd_wr_data" "cmd_wr_data"} \
{ "ctrl_sdo_wr_en" "sdo_wr_en"} \
{ "ctrl_sdo_wr_data" "sdo_wr_data"} \
{ "ctrl_enable" "enable"} \
{ "ctrl_enabled" "enabled"} \
{ "ctrl_mem_reset" "mem_reset"} \
{ "status_sync_ready" "sync_ready"} \
{ "status_sync_valid" "sync_valid"} \
{ "status_sync_data" "sync_data"} \
}
adi_add_bus "offload_sdi" "master" \