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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/spi_engine/axi_spi_engine/Makefile
+3 -1
View File
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
@@ -22,6 +22,8 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_cdc
XILINX_INTERFACE_DEPS += spi_engine/interfaces
INTEL_DEPS += ../../common/ad_mem.v
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v
+11 -3
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -133,7 +133,7 @@ module axi_spi_engine #(
input [7:0] offload_sync_data
);
localparam PCORE_VERSION = 'h010071;
localparam PCORE_VERSION = 'h010200;
localparam S_AXI = 0;
localparam UP_FIFO = 1;
@@ -334,12 +334,20 @@ module axi_spi_engine #(
end
endgenerate
reg [7:0] offload_sdo_mem_address_width = OFFLOAD0_SDO_MEM_ADDRESS_WIDTH;
reg [7:0] offload_cmd_mem_address_width = OFFLOAD0_CMD_MEM_ADDRESS_WIDTH;
reg [7:0] sdi_fifo_address_width = SDI_FIFO_ADDRESS_WIDTH;
reg [7:0] sdo_fifo_address_width = SDO_FIFO_ADDRESS_WIDTH;
reg [7:0] sync_fifo_address_width = SYNC_FIFO_ADDRESS_WIDTH;
reg [7:0] cmd_fifo_address_width = CMD_FIFO_ADDRESS_WIDTH;
always @(posedge clk) begin
case (up_raddr_s)
8'h00: up_rdata_ff <= PCORE_VERSION;
8'h01: up_rdata_ff <= ID;
8'h02: up_rdata_ff <= up_scratch;
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
8'h04: up_rdata_ff <= {16'b0, offload_sdo_mem_address_width, offload_cmd_mem_address_width};
8'h05: up_rdata_ff <= {sdi_fifo_address_width, sdo_fifo_address_width, sync_fifo_address_width, cmd_fifo_address_width};
8'h10: up_rdata_ff <= up_sw_reset;
8'h20: up_rdata_ff <= up_irq_mask;
8'h21: up_rdata_ff <= up_irq_pending;
adi_library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="7614137f133e45a3b5014a3375bb1862"/>
<Option Name="Id" Val="a6c121ede1ae47db9f9ddbaf67411ed8"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -175,21 +174,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -202,7 +201,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl
-6
View File
@@ -109,12 +109,6 @@ proc p_elaboration {} {
}
ad_interface signal pulse_gen_period output 32
ad_interface signal pulse_gen_width output 32
ad_interface signal pulse_gen_load output 1
lappend disabled_intfs if_pulse_gen_period if_pulse_gen_width if_pulse_gen_load
foreach interface $disabled_intfs {
set_interface_property $interface ENABLED false
}
adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
+23 -24
View File
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -34,18 +34,18 @@ adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd_data" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync_data" "SYNC_DATA"} \
{"cmd_ready" "cmd_ready"} \
{"cmd_valid" "cmd_valid"} \
{"cmd_data" "cmd_data"} \
{"sdo_data_ready" "sdo_ready"} \
{"sdo_data_valid" "sdo_valid"} \
{"sdo_data" "sdo_data"} \
{"sdi_data_ready" "sdi_ready"} \
{"sdi_data_valid" "sdi_valid"} \
{"sdi_data" "sdi_data"} \
{"sync_ready" "sync_ready"} \
{"sync_valid" "sync_valid"} \
{"sync_data" "sync_data"} \
}
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master"
@@ -53,18 +53,17 @@ adi_add_bus "spi_engine_offload_ctrl0" "master" \
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
{ \
{ "offload0_cmd_wr_en" "CMD_WR_EN"} \
{ "offload0_cmd_wr_data" "CMD_WR_DATA"} \
{ "offload0_sdo_wr_en" "SDO_WR_EN"} \
{ "offload0_sdo_wr_data" "SDO_WR_DATA"} \
{ "offload0_enable" "ENABLE"} \
{ "offload0_enabled" "ENABLED"} \
{ "offload0_mem_reset" "MEM_RESET"} \
{ "offload_sync_ready" "SYNC_READY"} \
{ "offload_sync_valid" "SYNC_VALID"} \
{ "offload_sync_data" "SYNC_DATA"} \
{ "offload0_cmd_wr_en" "cmd_wr_en"} \
{ "offload0_cmd_wr_data" "cmd_wr_data"} \
{ "offload0_sdo_wr_en" "sdo_wr_en"} \
{ "offload0_sdo_wr_data" "sdo_wr_data"} \
{ "offload0_enable" "enable"} \
{ "offload0_enabled" "enabled"} \
{ "offload0_mem_reset" "mem_reset"} \
{ "offload_sync_ready" "sync_ready"} \
{ "offload_sync_valid" "sync_valid"} \
{ "offload_sync_data" "sync_data"} \
}
adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn"
foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} {
adi_library/spi_engine/axi_spi_engine/component.xml
+28 -28
View File
@@ -230,7 +230,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_READY</spirit:name>
<spirit:name>cmd_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_ready</spirit:name>
@@ -238,7 +238,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_VALID</spirit:name>
<spirit:name>cmd_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_valid</spirit:name>
@@ -246,7 +246,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_DATA</spirit:name>
<spirit:name>cmd_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_data</spirit:name>
@@ -254,7 +254,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_READY</spirit:name>
<spirit:name>sdo_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_ready</spirit:name>
@@ -262,7 +262,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_VALID</spirit:name>
<spirit:name>sdo_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_valid</spirit:name>
@@ -270,7 +270,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_DATA</spirit:name>
<spirit:name>sdo_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data</spirit:name>
@@ -278,7 +278,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_READY</spirit:name>
<spirit:name>sdi_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_ready</spirit:name>
@@ -286,7 +286,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_VALID</spirit:name>
<spirit:name>sdi_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_valid</spirit:name>
@@ -294,7 +294,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_DATA</spirit:name>
<spirit:name>sdi_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data</spirit:name>
@@ -302,7 +302,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_ready</spirit:name>
@@ -310,7 +310,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_valid</spirit:name>
@@ -318,7 +318,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_data</spirit:name>
@@ -384,7 +384,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_WR_EN</spirit:name>
<spirit:name>cmd_wr_en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_cmd_wr_en</spirit:name>
@@ -392,7 +392,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_WR_DATA</spirit:name>
<spirit:name>cmd_wr_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_cmd_wr_data</spirit:name>
@@ -400,7 +400,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_WR_EN</spirit:name>
<spirit:name>sdo_wr_en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_sdo_wr_en</spirit:name>
@@ -408,7 +408,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_WR_DATA</spirit:name>
<spirit:name>sdo_wr_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_sdo_wr_data</spirit:name>
@@ -416,7 +416,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ENABLE</spirit:name>
<spirit:name>enable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_enable</spirit:name>
@@ -424,7 +424,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ENABLED</spirit:name>
<spirit:name>enabled</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_enabled</spirit:name>
@@ -432,7 +432,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>MEM_RESET</spirit:name>
<spirit:name>mem_reset</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload0_mem_reset</spirit:name>
@@ -440,7 +440,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload_sync_ready</spirit:name>
@@ -448,7 +448,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload_sync_valid</spirit:name>
@@ -456,7 +456,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>offload_sync_data</spirit:name>
@@ -553,7 +553,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>1fd5eec0</spirit:value>
<spirit:value>01e9a617</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -575,7 +575,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>089a1d05</spirit:value>
<spirit:value>2c2a08bc</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1868,7 +1868,7 @@
<spirit:file>
<spirit:name>axi_spi_engine.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_6b9f989c</spirit:userFileType>
<spirit:userFileType>CHECKSUM_a04cf31b</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -2074,11 +2074,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:52:34Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:10:12Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="071f18c1"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="35a91dd8"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="ca848ee8"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e191cf5b"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="570013dc"/>