update adi_library to vivado 2024.1
compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
@@ -1,5 +1,5 @@
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||||
####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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## Copyright (c) 2018 - 2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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||||
## Auto-generated, do not modify!
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||||
####################################################################################
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||||
@@ -11,10 +11,12 @@ GENERIC_DEPS += spi_engine_execution.v
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XILINX_DEPS += spi_engine_execution_constr.ttcl
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XILINX_DEPS += spi_engine_execution_ip.tcl
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_master.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_rtl.xml
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XILINX_INTERFACE_DEPS += spi_engine/interfaces
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INTEL_DEPS += spi_engine_execution_hw.tcl
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@@ -13,7 +13,7 @@
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CMD_READY</spirit:name>
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||||
<spirit:name>cmd_ready</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>cmd_ready</spirit:name>
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@@ -21,7 +21,7 @@
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CMD_VALID</spirit:name>
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||||
<spirit:name>cmd_valid</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>cmd_valid</spirit:name>
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@@ -29,7 +29,7 @@
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CMD_DATA</spirit:name>
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<spirit:name>cmd_data</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>cmd</spirit:name>
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@@ -37,7 +37,7 @@
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SDO_READY</spirit:name>
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<spirit:name>sdo_ready</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sdo_data_ready</spirit:name>
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@@ -45,7 +45,7 @@
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SDO_VALID</spirit:name>
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<spirit:name>sdo_valid</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sdo_data_valid</spirit:name>
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@@ -53,7 +53,7 @@
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SDO_DATA</spirit:name>
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<spirit:name>sdo_data</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sdo_data</spirit:name>
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@@ -61,7 +61,7 @@
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SDI_READY</spirit:name>
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<spirit:name>sdi_ready</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sdi_data_ready</spirit:name>
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@@ -69,7 +69,7 @@
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SDI_VALID</spirit:name>
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<spirit:name>sdi_valid</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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||||
<spirit:name>sdi_data_valid</spirit:name>
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@@ -77,7 +77,7 @@
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>SDI_DATA</spirit:name>
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||||
<spirit:name>sdi_data</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>sdi_data</spirit:name>
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||||
@@ -85,7 +85,7 @@
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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<spirit:name>SYNC_READY</spirit:name>
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||||
<spirit:name>sync_ready</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sync_ready</spirit:name>
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||||
@@ -93,7 +93,7 @@
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SYNC_VALID</spirit:name>
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||||
<spirit:name>sync_valid</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sync_valid</spirit:name>
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||||
@@ -101,7 +101,7 @@
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SYNC_DATA</spirit:name>
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||||
<spirit:name>sync_data</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sync</spirit:name>
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||||
@@ -161,13 +161,13 @@
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>spi</spirit:name>
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||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master_rtl" spirit:version="1.0"/>
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||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_rtl" spirit:version="1.0"/>
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||||
<spirit:master/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>SCLK</spirit:name>
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||||
<spirit:name>sclk</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sclk</spirit:name>
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||||
@@ -175,7 +175,7 @@
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDI</spirit:name>
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||||
<spirit:name>sdi</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdi</spirit:name>
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||||
@@ -183,7 +183,7 @@
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDO</spirit:name>
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||||
<spirit:name>sdo</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdo</spirit:name>
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||||
@@ -191,7 +191,7 @@
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>SDO_T</spirit:name>
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||||
<spirit:name>sdo_t</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>sdo_t</spirit:name>
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||||
@@ -199,7 +199,7 @@
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</spirit:portMap>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>THREE_WIRE</spirit:name>
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<spirit:name>three_wire</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>three_wire</spirit:name>
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@@ -207,7 +207,7 @@
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||||
</spirit:portMap>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>CS</spirit:name>
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||||
<spirit:name>cs</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>cs</spirit:name>
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||||
@@ -280,7 +280,7 @@
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||||
<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>4f3438ce</spirit:value>
|
||||
<spirit:value>8ce35280</spirit:value>
|
||||
</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:view>
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||||
@@ -296,7 +296,7 @@
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||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>4f3438ce</spirit:value>
|
||||
<spirit:value>8ce35280</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -442,9 +442,6 @@
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
<spirit:driver>
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||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
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||||
@@ -613,9 +610,6 @@
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
@@ -716,7 +710,7 @@
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||||
<spirit:file>
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||||
<spirit:name>spi_engine_execution.v</spirit:name>
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||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_4f3438ce</spirit:userFileType>
|
||||
<spirit:userFileType>CHECKSUM_8ce35280</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
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||||
<spirit:fileSet>
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||||
@@ -797,12 +791,12 @@
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||||
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
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||||
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-14T03:52:49Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2024-06-06T03:10:29Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b4974010"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c2e40dde"/>
|
||||
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7c5528bd"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="17dd883f"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0dd4e337"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="0194bdcd"/>
|
||||
</xilinx:packagingInfo>
|
||||
|
||||
@@ -1,6 +1,6 @@
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||||
// ***************************************************************************
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||||
// ***************************************************************************
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||||
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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||||
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
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||||
//
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||||
// In this HDL repository, there are many different and unique modules, consisting
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||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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@@ -26,7 +26,7 @@
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
@@ -76,10 +76,11 @@ module spi_engine_execution #(
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output reg three_wire
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);
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||||
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||||
localparam CMD_TRANSFER = 2'b00;
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localparam CMD_CHIPSELECT = 2'b01;
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||||
localparam CMD_WRITE = 2'b10;
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||||
localparam CMD_MISC = 2'b11;
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||||
localparam CMD_TRANSFER = 3'b000;
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||||
localparam CMD_CHIPSELECT = 3'b001;
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||||
localparam CMD_WRITE = 3'b010;
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||||
localparam CMD_MISC = 3'b011;
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||||
localparam CMD_CS_INV = 3'b100;
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||||
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||||
localparam MISC_SYNC = 1'b0;
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localparam MISC_SLEEP = 1'b1;
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@@ -134,6 +135,8 @@ module spi_engine_execution #(
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reg cpol = DEFAULT_SPI_CFG[1];
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reg [7:0] clk_div = DEFAULT_CLK_DIV;
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||||
|
||||
reg [NUM_OF_CS-1:0] cs_inv_mask_reg = 'h0;
|
||||
|
||||
reg sdo_enabled = 1'b0;
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||||
reg sdi_enabled = 1'b0;
|
||||
|
||||
@@ -141,12 +144,12 @@ module spi_engine_execution #(
|
||||
|
||||
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
|
||||
|
||||
wire [1:0] inst = cmd[13:12];
|
||||
wire [1:0] inst_d1 = cmd_d1[13:12];
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||||
wire [2:0] inst = cmd[14:12];
|
||||
wire [2:0] inst_d1 = cmd_d1[14:12];
|
||||
|
||||
wire exec_cmd = cmd_ready && cmd_valid;
|
||||
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
|
||||
|
||||
wire exec_cs_inv_cmd = exec_cmd && inst == CMD_CS_INV;
|
||||
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
|
||||
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
|
||||
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
|
||||
@@ -159,6 +162,7 @@ module spi_engine_execution #(
|
||||
wire cs_sleep_counter_compare;
|
||||
wire cs_sleep_early_exit;
|
||||
reg cs_sleep_repeat;
|
||||
reg cs_active;
|
||||
|
||||
wire io_ready1;
|
||||
wire io_ready2;
|
||||
@@ -305,11 +309,21 @@ module spi_engine_execution #(
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk ) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs_inv_mask_reg <= 'h0;
|
||||
end else begin
|
||||
if (exec_cs_inv_cmd == 1'b1) begin
|
||||
cs_inv_mask_reg <= cmd[NUM_OF_CS-1:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs <= 'hff;
|
||||
end else if (cs_gen) begin
|
||||
cs <= cmd_d1[NUM_OF_CS-1:0];
|
||||
cs <= cmd_d1[NUM_OF_CS-1:0]^cs_inv_mask_reg[NUM_OF_CS-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
@@ -420,7 +434,14 @@ module spi_engine_execution #(
|
||||
// used to latch the MISO lines, improving the overall timing margin of the
|
||||
// interface.
|
||||
|
||||
wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
|
||||
always @(posedge clk) begin
|
||||
if (!resetn) begin // set cs_active during reset for a cycle to clear shift reg
|
||||
cs_active <= 1;
|
||||
end else begin
|
||||
cs_active <= ~(&cmd_d1[NUM_OF_CS-1:0]) & cs_gen;
|
||||
end
|
||||
end
|
||||
|
||||
genvar i;
|
||||
|
||||
// NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point
|
||||
@@ -438,8 +459,8 @@ module spi_engine_execution #(
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
|
||||
always @(negedge echo_sclk or posedge cs_active_s) begin
|
||||
if (cs_active_s) begin
|
||||
always @(negedge echo_sclk or posedge cs_active) begin
|
||||
if (cs_active) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
@@ -454,8 +475,8 @@ module spi_engine_execution #(
|
||||
|
||||
end
|
||||
|
||||
always @(posedge echo_sclk or posedge cs_active_s) begin
|
||||
if (cs_active_s == 1'b1) begin
|
||||
always @(posedge echo_sclk or posedge cs_active) begin
|
||||
if (cs_active) begin
|
||||
sdi_counter <= 8'b0;
|
||||
sdi_counter_d <= 8'b0;
|
||||
end else begin
|
||||
@@ -469,8 +490,8 @@ module spi_engine_execution #(
|
||||
// MISO shift register runs on positive echo_sclk
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
always @(posedge echo_sclk or posedge cs_active_s) begin
|
||||
if (cs_active_s) begin
|
||||
always @(posedge echo_sclk or posedge cs_active) begin
|
||||
if (cs_active) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
@@ -483,8 +504,8 @@ module spi_engine_execution #(
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge echo_sclk or posedge cs_active_s) begin
|
||||
if (cs_active_s == 1'b1) begin
|
||||
always @(posedge echo_sclk or posedge cs_active) begin
|
||||
if (cs_active) begin
|
||||
sdi_counter <= 8'b0;
|
||||
sdi_counter_d <= 8'b0;
|
||||
end else begin
|
||||
@@ -503,7 +524,7 @@ module spi_engine_execution #(
|
||||
|
||||
reg [3:0] last_sdi_bit_m = 4'b0;
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
if (cs_active) begin
|
||||
last_sdi_bit_m <= 4'b0;
|
||||
end else begin
|
||||
last_sdi_bit_m <= {last_sdi_bit_m, last_sdi_bit};
|
||||
@@ -511,7 +532,7 @@ module spi_engine_execution #(
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
if (cs_active) begin
|
||||
sdi_data_valid <= 1'b0;
|
||||
end else if (sdi_enabled == 1'b1 &&
|
||||
last_sdi_bit_m[3] == 1'b0 &&
|
||||
@@ -523,7 +544,7 @@ module spi_engine_execution #(
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
if (cs_active) begin
|
||||
num_of_transfers <= 8'b0;
|
||||
end else begin
|
||||
if (cmd_d1[15:12] == 4'b0) begin
|
||||
@@ -533,7 +554,7 @@ module spi_engine_execution #(
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
if (cs_active) begin
|
||||
sdi_transfer_counter <= 0;
|
||||
end else if (last_sdi_bit_m[2] == 1'b0 &&
|
||||
last_sdi_bit_m[1] == 1'b1) begin
|
||||
@@ -554,7 +575,7 @@ module spi_engine_execution #(
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
if (cs_active) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- Product Version: Vivado v2024.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_execution/spi_engine_execution.xpr">
|
||||
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_engine_execution/spi_engine_execution.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="1f06667fc09742279c2aaecc7fa6d70e"/>
|
||||
<Option Name="Id" Val="00911a71ecb04d8a81905b8675308ae8"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
@@ -29,12 +29,12 @@
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
@@ -59,7 +59,6 @@
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
@@ -155,21 +154,21 @@
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Runs Version="1" Minor="22">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
@@ -182,7 +181,7 @@
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
@@ -26,31 +26,31 @@ adi_add_bus "ctrl" "slave" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{
|
||||
{"cmd_ready" "CMD_READY"} \
|
||||
{"cmd_valid" "CMD_VALID"} \
|
||||
{"cmd" "CMD_DATA"} \
|
||||
{"sdo_data_ready" "SDO_READY"} \
|
||||
{"sdo_data_valid" "SDO_VALID"} \
|
||||
{"sdo_data" "SDO_DATA"} \
|
||||
{"sdi_data_ready" "SDI_READY"} \
|
||||
{"sdi_data_valid" "SDI_VALID"} \
|
||||
{"sdi_data" "SDI_DATA"} \
|
||||
{"sync_ready" "SYNC_READY"} \
|
||||
{"sync_valid" "SYNC_VALID"} \
|
||||
{"sync" "SYNC_DATA"} \
|
||||
{"cmd_ready" "cmd_ready"} \
|
||||
{"cmd_valid" "cmd_valid"} \
|
||||
{"cmd" "cmd_data"} \
|
||||
{"sdo_data_ready" "sdo_ready"} \
|
||||
{"sdo_data_valid" "sdo_valid"} \
|
||||
{"sdo_data" "sdo_data"} \
|
||||
{"sdi_data_ready" "sdi_ready"} \
|
||||
{"sdi_data_valid" "sdi_valid"} \
|
||||
{"sdi_data" "sdi_data"} \
|
||||
{"sync_ready" "sync_ready"} \
|
||||
{"sync_valid" "sync_valid"} \
|
||||
{"sync" "sync_data"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "ctrl" "resetn"
|
||||
|
||||
adi_add_bus "spi" "master" \
|
||||
"analog.com:interface:spi_master_rtl:1.0" \
|
||||
"analog.com:interface:spi_master:1.0" \
|
||||
"analog.com:interface:spi_engine_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine:1.0" \
|
||||
{
|
||||
{"sclk" "SCLK"} \
|
||||
{"sdi" "SDI"} \
|
||||
{"sdo" "SDO"} \
|
||||
{"sdo_t" "SDO_T"} \
|
||||
{"three_wire" "THREE_WIRE"} \
|
||||
{"cs" "CS"} \
|
||||
{"sclk" "sclk"} \
|
||||
{"sdi" "sdi"} \
|
||||
{"sdo" "sdo"} \
|
||||
{"sdo_t" "sdo_t"} \
|
||||
{"three_wire" "three_wire"} \
|
||||
{"cs" "cs"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "spi" "resetn"
|
||||
|
||||
|
||||
Reference in New Issue
Block a user