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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/spi_engine/spi_engine_offload/Makefile
+4 -1
View File
@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
@@ -18,7 +18,10 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_cdc
XILINX_INTERFACE_DEPS += spi_engine/interfaces
INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../../util_cdc/sync_event.v
INTEL_DEPS += spi_engine_offload_hw.tcl
include ../../scripts/library.mk
adi_library/spi_engine/spi_engine_offload/component.xml
+28 -28
View File
@@ -13,7 +13,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_READY</spirit:name>
<spirit:name>cmd_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_ready</spirit:name>
@@ -21,7 +21,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_VALID</spirit:name>
<spirit:name>cmd_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_valid</spirit:name>
@@ -29,7 +29,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_DATA</spirit:name>
<spirit:name>cmd_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd</spirit:name>
@@ -37,7 +37,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_READY</spirit:name>
<spirit:name>sdo_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_ready</spirit:name>
@@ -45,7 +45,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_VALID</spirit:name>
<spirit:name>sdo_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data_valid</spirit:name>
@@ -53,7 +53,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_DATA</spirit:name>
<spirit:name>sdo_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdo_data</spirit:name>
@@ -61,7 +61,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_READY</spirit:name>
<spirit:name>sdi_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_ready</spirit:name>
@@ -69,7 +69,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_VALID</spirit:name>
<spirit:name>sdi_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data_valid</spirit:name>
@@ -77,7 +77,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDI_DATA</spirit:name>
<spirit:name>sdi_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdi_data</spirit:name>
@@ -85,7 +85,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_ready</spirit:name>
@@ -93,7 +93,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_valid</spirit:name>
@@ -101,7 +101,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sync_data</spirit:name>
@@ -117,7 +117,7 @@
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_WR_EN</spirit:name>
<spirit:name>cmd_wr_en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_cmd_wr_en</spirit:name>
@@ -125,7 +125,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_WR_DATA</spirit:name>
<spirit:name>cmd_wr_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_cmd_wr_data</spirit:name>
@@ -133,7 +133,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_WR_EN</spirit:name>
<spirit:name>sdo_wr_en</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_sdo_wr_en</spirit:name>
@@ -141,7 +141,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SDO_WR_DATA</spirit:name>
<spirit:name>sdo_wr_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_sdo_wr_data</spirit:name>
@@ -149,7 +149,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ENABLE</spirit:name>
<spirit:name>enable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_enable</spirit:name>
@@ -157,7 +157,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ENABLED</spirit:name>
<spirit:name>enabled</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_enabled</spirit:name>
@@ -165,7 +165,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>MEM_RESET</spirit:name>
<spirit:name>mem_reset</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ctrl_mem_reset</spirit:name>
@@ -173,7 +173,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_READY</spirit:name>
<spirit:name>sync_ready</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>status_sync_ready</spirit:name>
@@ -181,7 +181,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_VALID</spirit:name>
<spirit:name>sync_valid</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>status_sync_valid</spirit:name>
@@ -189,7 +189,7 @@
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SYNC_DATA</spirit:name>
<spirit:name>sync_data</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>status_sync_data</spirit:name>
@@ -320,7 +320,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>54da56d5</spirit:value>
<spirit:value>415947b9</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -339,7 +339,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>54da56d5</spirit:value>
<spirit:value>415947b9</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -842,7 +842,7 @@
<spirit:file>
<spirit:name>spi_engine_offload.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_54da56d5</spirit:userFileType>
<spirit:userFileType>CHECKSUM_415947b9</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -941,11 +941,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:53:04Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:10:45Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8689cb20"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="582124d3"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="2756ddd5"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ae1a9eae"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="e2e1ec4a"/>
adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v
+33 -20
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -96,9 +96,12 @@ module spi_engine_offload #(
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
reg trigger_last_reg;
wire [15:0] cmd_int_s;
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
wire spi_enable;
wire trigger_posedge;
assign cmd_valid = spi_active;
assign sdo_data_valid = spi_active;
@@ -126,7 +129,7 @@ module spi_engine_offload #(
wire [ 7:0] spi_sync_id_init_s;
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1) begin
if (ctrl_mem_reset) begin
ctrl_sync_id_init <= 8'b0;
ctrl_sync_id_load <= 1'b0;
end else begin
@@ -160,7 +163,7 @@ module spi_engine_offload #(
.out_bits(spi_sync_id_init_s));
always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin
if (!spi_resetn) begin
spi_sync_id_counter <= 8'b0;
end else begin
if (spi_sync_id_load_s) begin
@@ -198,9 +201,9 @@ module spi_engine_offload #(
reg spi_enabled = 1'b0;
always @(posedge ctrl_clk) begin
if (ctrl_enable == 1'b1) begin
if (ctrl_enable) begin
ctrl_do_enable <= 1'b1;
end else if (ctrl_is_enabled == 1'b1) begin
end else if (ctrl_is_enabled) begin
ctrl_do_enable <= 1'b0;
end
end
@@ -247,57 +250,67 @@ module spi_engine_offload #(
.out_bits(trigger_s));
always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin
if (!spi_resetn) begin
trigger_last_reg <= 1'b0;
end else begin
trigger_last_reg <= trigger_s;
end
end
assign trigger_posedge = trigger_s && !trigger_last_reg;
always @(posedge spi_clk) begin
if (!spi_resetn) begin
spi_active <= 1'b0;
end else begin
if (spi_active == 1'b0) begin
if (!spi_active) begin
// start offload when we have a valid trigger, offload is enabled and
// the DMA is enabled
if (trigger_s == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1)
if (trigger_posedge && spi_enable && offload_sdi_ready)
spi_active <= 1'b1;
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
end else if (cmd_ready && (spi_cmd_rd_addr_next == ctrl_cmd_wr_addr)) begin
spi_active <= 1'b0;
end
end
end
always @(posedge spi_clk) begin
if (cmd_valid == 1'b0) begin
if (!cmd_valid) begin
spi_cmd_rd_addr <= 'h00;
end else if (cmd_ready == 1'b1) begin
end else if (cmd_ready) begin
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
end
end
always @(posedge spi_clk) begin
if (spi_active == 1'b0) begin
if (!spi_active) begin
spi_sdo_rd_addr <= 'h00;
end else if (sdo_data_ready == 1'b1) begin
end else if (sdo_data_ready) begin
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
end
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
if (ctrl_mem_reset)
ctrl_cmd_wr_addr <= 'h00;
else if (ctrl_cmd_wr_en == 1'b1)
else if (ctrl_cmd_wr_en)
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_cmd_wr_en == 1'b1)
if (ctrl_cmd_wr_en)
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
if (ctrl_mem_reset)
ctrl_sdo_wr_addr <= 'h00;
else if (ctrl_sdo_wr_en == 1'b1)
else if (ctrl_sdo_wr_en)
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_sdo_wr_en == 1'b1)
if (ctrl_sdo_wr_en)
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
end
adi_library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="30b4a7c406754ea493b787146654d616"/>
<Option Name="Id" Val="36637aefd0314394950d6379054a8d3c"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -155,21 +154,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -182,7 +181,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl
+1
View File
@@ -10,6 +10,7 @@ source ../../scripts/adi_ip_intel.tcl
ad_ip_create spi_engine_offload {SPI Engine Offload} p_elaboration
ad_ip_files spi_engine_offload [list\
$ad_hdl_dir/library/util_cdc/sync_bits.v \
$ad_hdl_dir/library/util_cdc/sync_event.v \
spi_engine_offload.v]
# parameters
adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
+22 -22
View File
@@ -32,34 +32,34 @@ adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \
{
{"cmd_ready" "CMD_READY"} \
{"cmd_valid" "CMD_VALID"} \
{"cmd" "CMD_DATA"} \
{"sdo_data_ready" "SDO_READY"} \
{"sdo_data_valid" "SDO_VALID"} \
{"sdo_data" "SDO_DATA"} \
{"sdi_data_ready" "SDI_READY"} \
{"sdi_data_valid" "SDI_VALID"} \
{"sdi_data" "SDI_DATA"} \
{"sync_ready" "SYNC_READY"} \
{"sync_valid" "SYNC_VALID"} \
{"sync_data" "SYNC_DATA"} \
{"cmd_ready" "cmd_ready"} \
{"cmd_valid" "cmd_valid"} \
{"cmd" "cmd_data"} \
{"sdo_data_ready" "sdo_ready"} \
{"sdo_data_valid" "sdo_valid"} \
{"sdo_data" "sdo_data"} \
{"sdi_data_ready" "sdi_ready"} \
{"sdi_data_valid" "sdi_valid"} \
{"sdi_data" "sdi_data"} \
{"sync_ready" "sync_ready"} \
{"sync_valid" "sync_valid"} \
{"sync_data" "sync_data"} \
}
adi_add_bus "spi_engine_offload_ctrl" "slave" \
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
{ \
{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
{ "ctrl_sdo_wr_en" "SDO_WR_EN"} \
{ "ctrl_sdo_wr_data" "SDO_WR_DATA"} \
{ "ctrl_enable" "ENABLE"} \
{ "ctrl_enabled" "ENABLED"} \
{ "ctrl_mem_reset" "MEM_RESET"} \
{ "status_sync_ready" "SYNC_READY"} \
{ "status_sync_valid" "SYNC_VALID"} \
{ "status_sync_data" "SYNC_DATA"} \
{ "ctrl_cmd_wr_en" "cmd_wr_en"} \
{ "ctrl_cmd_wr_data" "cmd_wr_data"} \
{ "ctrl_sdo_wr_en" "sdo_wr_en"} \
{ "ctrl_sdo_wr_data" "sdo_wr_data"} \
{ "ctrl_enable" "enable"} \
{ "ctrl_enabled" "enabled"} \
{ "ctrl_mem_reset" "mem_reset"} \
{ "status_sync_ready" "sync_ready"} \
{ "status_sync_valid" "sync_valid"} \
{ "status_sync_data" "sync_data"} \
}
adi_add_bus "offload_sdi" "master" \