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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
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josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/util_axis_fifo/component.xml
+6 -6
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@@ -219,7 +219,7 @@
<spirit:parameters>
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<spirit:value>4837ce55</spirit:value>
<spirit:value>2735fcaa</spirit:value>
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</spirit:parameters>
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@@ -238,7 +238,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>4837ce55</spirit:value>
<spirit:value>2735fcaa</spirit:value>
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@@ -667,7 +667,7 @@
<spirit:file>
<spirit:name>util_axis_fifo.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_56c88183</spirit:userFileType>
<spirit:userFileType>CHECKSUM_f51e4483</spirit:userFileType>
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</spirit:fileSet>
<spirit:fileSet>
@@ -827,11 +827,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_axis_fifo</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:45:42Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:01:48Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="59ef6667"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="34474606"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="de18f3ae"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="7abddce6"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="c7e77367"/>