josh/vivado_pub
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 2 Wiki Activity

update adi_library to vivado 2024.1

Browse Source 
compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
Download Patch File Download Diff File Expand all files Collapse all files
adi_library/util_axis_fifo/util_axis_fifo.v
+14 -9
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -148,8 +148,8 @@ module util_axis_fifo #(
axis_tlast_d <= s_axis_tlast;
end
assign m_axis_tlast = axis_tlast_d;
end
end else
assign m_axis_tlast = 'b0;
// TKEEP support
if (TKEEP_EN) begin
@@ -161,8 +161,8 @@ module util_axis_fifo #(
axis_tkeep_d <= s_axis_tkeep;
end
assign m_axis_tkeep = axis_tkeep_d;
end
end else
assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
end /* zerodeep */
else
@@ -205,7 +205,8 @@ module util_axis_fifo #(
end
end
assign m_axis_tlast = axis_tlast_d;
end
end else
assign m_axis_tlast = 'b0;
// TKEEP support
if (TKEEP_EN) begin
@@ -219,8 +220,8 @@ module util_axis_fifo #(
end
end
assign m_axis_tkeep = axis_tkeep_d;
end
end else
assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
end /* !ASYNC_CLK */
@@ -288,13 +289,17 @@ module util_axis_fifo #(
end else if (TKEEP_EN) begin
assign s_axis_data_int_s = {s_axis_tkeep, s_axis_data};
assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
assign m_axis_tlast = 'b0;
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
end else if (TLAST_EN) begin
assign s_axis_data_int_s = {s_axis_tlast, s_axis_data};
assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
end else begin
assign s_axis_data_int_s = {s_axis_data};
assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
assign m_axis_tlast = 'b0;
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
end