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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/util_do_ram/component.xml
+6 -6
View File
@@ -358,7 +358,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>f913396f</spirit:value>
<spirit:value>735a98aa</spirit:value>
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@@ -380,7 +380,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>f913396f</spirit:value>
<spirit:value>735a98aa</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -883,7 +883,7 @@
<spirit:file>
<spirit:name>util_do_ram.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_94f67d2d</spirit:userFileType>
<spirit:userFileType>CHECKSUM_06ac53d3</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -999,11 +999,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:54:37Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:12:05Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a2d32e6c"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2392c602"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="517750cb"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e2af70cb"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="6db5087f"/>
adi_library/util_do_ram/util_do_ram.v
+38 -13
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -93,6 +93,7 @@ module util_do_ram #(
wire wr_enable;
wire [DST_DATA_WIDTH-1:0] rd_data;
wire [DST_DATA_WIDTH/8-1:0] rd_keep;
wire [1:0] rd_fifo_room;
wire rd_enable;
wire rd_last_beat;
@@ -102,6 +103,7 @@ module util_do_ram #(
reg [SRC_ADDRESS_WIDTH-1:0] wr_length = 'h0;
reg [SRC_ADDRESS_WIDTH-1:0] wr_addr = 'h0;
reg [DST_DATA_WIDTH-1:0] rd_data_l2 = 'h0;
reg [DST_DATA_WIDTH/8-1:0] rd_keep_l2 = 'h0;
reg [DST_ADDRESS_WIDTH-1:0] rd_length = 'h0;
reg [DST_ADDRESS_WIDTH-1:0] rd_addr = 'h0;
reg rd_pending = 1'b0;
@@ -168,7 +170,7 @@ module util_do_ram #(
.A_DATA_WIDTH (SRC_DATA_WIDTH),
.B_ADDRESS_WIDTH (DST_ADDRESS_WIDTH),
.B_DATA_WIDTH (DST_DATA_WIDTH)
) i_mem (
) i_mem_data (
.clka (s_axis_aclk),
.wea (wr_enable),
.addra (wr_addr),
@@ -179,6 +181,22 @@ module util_do_ram #(
.addrb (rd_addr),
.doutb (rd_data));
ad_mem_asym #(
.A_ADDRESS_WIDTH (SRC_ADDRESS_WIDTH),
.A_DATA_WIDTH (SRC_DATA_WIDTH/8),
.B_ADDRESS_WIDTH (DST_ADDRESS_WIDTH),
.B_DATA_WIDTH (DST_DATA_WIDTH/8)
) i_mem_keep (
.clka (s_axis_aclk),
.wea (wr_enable),
.addra (wr_addr),
.dina (s_axis_keep),
.clkb (m_axis_aclk),
.reb (1'b1),
.addrb (rd_addr),
.doutb (rd_keep));
reg rd_active = 1'b0;
reg [1:0] rd_req_cnt = 2'b0;
always @(posedge m_axis_aclk) begin
@@ -238,9 +256,14 @@ module util_do_ram #(
always @(posedge m_axis_aclk) begin
if (rd_valid_l1)
rd_data_l2 <= rd_data;
end
end
always @(posedge m_axis_aclk) begin
always @(posedge m_axis_aclk) begin
if (rd_valid_l1)
rd_keep_l2 <= rd_keep;
end
always @(posedge m_axis_aclk) begin
if (rd_valid_l1)
rd_valid_l2 <= 1'b1;
else if (rd_fifo_s_ready)
@@ -254,31 +277,33 @@ module util_do_ram #(
// Read datapath to AXIS logic
util_axis_fifo #(
.DATA_WIDTH(DST_DATA_WIDTH+1),
.DATA_WIDTH(DST_DATA_WIDTH),
.ADDRESS_WIDTH(2),
.ASYNC_CLK(0),
.M_AXIS_REGISTERED(0)
.M_AXIS_REGISTERED(0),
.TLAST_EN(1),
.TKEEP_EN(1)
) i_rd_fifo (
.s_axis_aclk(m_axis_aclk),
.s_axis_aresetn(m_axis_aresetn & rd_request_enable),
.s_axis_valid(rd_fifo_s_valid),
.s_axis_ready(rd_fifo_s_ready),
.s_axis_full(),
.s_axis_data({rd_last_l2,rd_data_l2}),
.s_axis_data(rd_data_l2),
.s_axis_room(rd_fifo_room),
.s_axis_tkeep(),
.s_axis_tlast(),
.s_axis_tkeep(rd_keep_l2),
.s_axis_tlast(rd_last_l2),
.s_axis_almost_full(),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn & rd_request_enable),
.m_axis_valid(m_axis_valid),
.m_axis_ready(m_axis_ready),
.m_axis_data({m_axis_last,m_axis_data}),
.m_axis_data(m_axis_data),
.m_axis_level(),
.m_axis_empty(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tkeep(m_axis_keep),
.m_axis_tlast(m_axis_last),
.m_axis_almost_empty());
endmodule
adi_library/util_do_ram/util_do_ram.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_do_ram/util_do_ram.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_do_ram/util_do_ram.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="0bf723676944490a9ab3c4490ea9a05f"/>
<Option Name="Id" Val="ab4b944285424e52805930350be11e16"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -168,21 +167,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -195,7 +194,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>