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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/util_hbm/component.xml
+9 -9
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@@ -5674,7 +5674,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>e53075f6</spirit:value>
<spirit:value>adc69daf</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -5696,7 +5696,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>9b7d6e4d</spirit:value>
<spirit:value>7348ecf4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -6696,7 +6696,7 @@
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>HBM_SEGMENTS_PER_MASTER</spirit:name>
<spirit:displayName>Hbm Segments Per Master</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HBM_SEGMENTS_PER_MASTER"/>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HBM_SEGMENTS_PER_MASTER">8</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>HBM_SEGMENT_INDEX</spirit:name>
@@ -6818,7 +6818,7 @@
<spirit:file>
<spirit:name>util_hbm.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_a4a1e134</spirit:userFileType>
<spirit:userFileType>CHECKSUM_fc2eb467</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -6948,7 +6948,7 @@
<spirit:parameter>
<spirit:name>LENGTH_WIDTH</spirit:name>
<spirit:displayName>Storage size</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LENGTH_WIDTH" spirit:choiceRef="choice_pairs_cebf9777">24</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LENGTH_WIDTH" spirit:choiceRef="choice_pairs_cebf9777">28</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AXI_PROTOCOL</spirit:name>
@@ -6973,7 +6973,7 @@
<spirit:parameter>
<spirit:name>HBM_SEGMENTS_PER_MASTER</spirit:name>
<spirit:displayName>HBM sections per master</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HBM_SEGMENTS_PER_MASTER"/>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HBM_SEGMENTS_PER_MASTER">8</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -7040,11 +7040,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:55:19Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:12:49Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="600a0db5"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0cf35e7b"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="63780b38"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="10097211"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="cd4bda90"/>
adi_library/util_hbm/gui/util_hbm_v1_0.gtcl
+1 -1
View File
@@ -1,4 +1,4 @@
# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_HBM_SEGMENTS_PER_MASTER_VALUE {LENGTH_WIDTH NUM_M } {expr int(ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}.0)) }
proc gen_USERPARAMETER_HBM_SEGMENTS_PER_MASTER_VALUE {LENGTH_WIDTH NUM_M } {expr ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}) }
proc gen_USERPARAMETER_HBM_SEGMENT_INDEX_ENABLEMENT {MEM_TYPE } {expr $MEM_TYPE == 2}
proc gen_USERPARAMETER_DDR_BASE_ADDDRESS_ENABLEMENT {MEM_TYPE } {expr $MEM_TYPE == 1}
adi_library/util_hbm/scripts/adi_util_hbm.tcl
+4 -4
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -33,12 +33,12 @@ proc ad_create_hbm {ip_name {density "4GB"}} {
}
}
proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} {
proc ad_create_util_hbm {name tx_rx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} {
if {$mem_type == 2} {
# HBM
# split converter side bus into multiple AXI masters
set number_of_masters [expr int(ceil((${rx_tx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))]
set number_of_masters [expr int(ceil((${tx_rx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))]
} else {
# DDR we have always one master
set number_of_masters 1
@@ -49,7 +49,7 @@ proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_wid
SRC_DATA_WIDTH $src_width \
DST_DATA_WIDTH $dst_width \
AXI_DATA_WIDTH $axi_data_width \
TX_RX_N $rx_tx_n \
TX_RX_N $tx_rx_n \
NUM_M $number_of_masters \
MEM_TYPE $mem_type \
]
adi_library/util_hbm/util_hbm.v
+1 -1
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@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/util_hbm/util_hbm.xpr
+13 -14
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@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_hbm/util_hbm.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_hbm/util_hbm.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="25ee62de6e2c4594bccbfad815be1926"/>
<Option Name="Id" Val="403e7461fe894850b63ec63e1744b067"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -168,21 +167,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -195,7 +194,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/util_hbm/util_hbm_ip.tcl
+3 -3
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -153,7 +153,7 @@ foreach dir {"SRC" "DST"} {
set_property -dict [list \
"value_validation_type" "pairs" \
"value" "24" \
"value" "28" \
"value_validation_pairs" {\
"256MB" "28" \
"512MB" "29" \
@@ -209,7 +209,7 @@ set_property -dict [list \
# HBM_SEGMENTS_PER_MASTER = Storage size (MB) / 256 (MB) / number of masters
set_property -dict [list \
"enablement_value" "false" \
"value_tcl_expr" {expr int(ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}.0)) } \
"value_tcl_expr" { ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}) } \
] \
[ipx::get_user_parameters HBM_SEGMENTS_PER_MASTER -of_objects $cc]