initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_ad5766
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_dac_common.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += ../common/util_pulse_gen.v
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GENERIC_DEPS += axi_ad5766.v
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GENERIC_DEPS += up_ad5766_sequencer.v
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XILINX_DEPS += axi_ad5766_ip.tcl
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XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl.xml
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XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
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XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl.xml
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XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
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XILINX_LIB_DEPS += util_cdc
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include ../scripts/library.mk
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@@ -0,0 +1,437 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad5766 #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter ASYNC_SPI_CLK = 0,
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parameter CMD_MEM_ADDRESS_WIDTH = 4,
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parameter SDO_MEM_ADDRESS_WIDTH = 4
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) (
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// Slave AXI interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input [ 2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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input [ 2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// FIFO transmit
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output dma_clk,
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output reg dma_valid,
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input dma_enable,
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input [15:0] dma_data,
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input dma_xfer_req,
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input dma_underflow,
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// SPI engine control interface (to the SPI engine interconnect)
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input spi_clk, // should be connected to up_clk
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input spi_resetn,
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input cmd_ready,
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output cmd_valid,
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output [15:0] cmd_data,
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input sdo_data_ready,
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output sdo_data_valid,
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output [ 7:0] sdo_data,
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output sdi_data_ready,
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input sdi_data_valid,
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input [ 7:0] sdi_data,
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output sync_ready,
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input sync_valid,
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input [ 7:0] sync_data,
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// SPI engine offload interface (to the AXI SPI engine)
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input ctrl_clk,
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input ctrl_cmd_wr_en,
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input [15:0] ctrl_cmd_wr_data,
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input ctrl_enable,
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output ctrl_enabled,
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input ctrl_mem_reset
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);
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// internal wires
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s[0:1];
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wire up_rack_s[0:1];
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wire up_wack_s[0:1];
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wire trigger_s;
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wire [31:0] pulse_period_s;
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wire [15:0] dac_datarate_s;
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wire spi_reset;
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wire spi_enable_s;
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wire [ 3:0] sequencer[15:0];
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wire [ 3:0] cmd_bits;
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wire [ 3:0] end_of_sequence;
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wire spi_mem_reset_s;
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wire sequence_valid_s;
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wire [ 7:0] sequence_data_s;
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wire dac_rst_s;
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wire dac_rstn_s;
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wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
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// registers
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reg [31:0] up_rdata = 32'b0;
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reg up_rack = 0;
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reg up_wack = 1'b0;
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reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
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reg [ 7:0] sdo_mem[0:2];
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reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'b0;
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reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'b0;
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reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'b0;
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reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'b0;
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reg spi_active = 1'b0;
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assign up_rstn = s_axi_aresetn;
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// the dma interface runs on SPI_CLK
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assign dma_clk = spi_clk;
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// command and SDO data offload
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assign cmd_valid = spi_active;
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assign cmd_data = cmd_mem[spi_cmd_rd_addr];
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assign sdo_data_valid = spi_active;
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assign sdo_data = sdo_mem[spi_sdo_rd_addr];
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assign sync_ready = 1'b1;
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assign sdi_data_ready = 1'b0;
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generate if (ASYNC_SPI_CLK) begin
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/*
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* The synchronization circuit takes care that there are no glitches on the
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* ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
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* asserted, but only deasserted once the signal has been synchronized back from
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* the SPI domain. This makes sure that we can't end up in a state where the
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* enable signal in the SPI domain is asserted, but neither enable nor enabled
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* is asserted in the control domain.
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*/
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reg ctrl_do_enable = 1'b0;
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wire ctrl_is_enabled;
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reg spi_enabled = 1'b0;
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always @(posedge ctrl_clk) begin
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if (ctrl_enable == 1'b1) begin
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ctrl_do_enable <= 1'b1;
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end else if (ctrl_is_enabled == 1'b1) begin
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ctrl_do_enable <= 1'b0;
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end
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end
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assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
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always @(posedge spi_clk) begin
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spi_enabled <= spi_enable_s | spi_active;
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end
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sync_bits #(
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.NUM_OF_BITS(1),
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.ASYNC_CLK(1)
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) i_sync_enable (
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.in_bits(ctrl_do_enable),
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.out_clk(spi_clk),
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.out_resetn(1'b1),
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.out_bits(spi_enable_s));
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sync_bits #(
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.NUM_OF_BITS(1),
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.ASYNC_CLK(1)
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) i_sync_enabled (
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.in_bits(spi_enabled),
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.out_clk(ctrl_clk),
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.out_resetn(1'b1),
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.out_bits(ctrl_is_enabled));
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sync_bits #(
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.NUM_OF_BITS(1),
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.ASYNC_CLK(1)
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) i_sync_mem_reset (
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.in_bits(ctrl_mem_reset),
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.out_clk(spi_clk),
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.out_resetn(1'b1),
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.out_bits(spi_mem_reset_s));
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end else begin
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assign spi_enable_s = ctrl_enable;
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assign ctrl_enabled = spi_enable_s | spi_active;
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assign spi_mem_reset_s = ctrl_mem_reset;
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end endgenerate
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assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
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always @(posedge spi_clk) begin
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if (spi_resetn == 1'b0) begin
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spi_active <= 1'b0;
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end else begin
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if (spi_active == 1'b0) begin
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if ((trigger_s == 1'b1 && spi_enable_s == 1'b1)) begin
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spi_active <= 1'b1;
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end
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end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
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spi_active <= 1'b0;
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end
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end
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end
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always @(posedge spi_clk) begin
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if (cmd_valid == 1'b0) begin
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spi_cmd_rd_addr <= 'h00;
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end else if (cmd_ready == 1'b1) begin
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spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
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end
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end
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always @(posedge spi_clk) begin
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if (spi_active == 1'b0) begin
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spi_sdo_rd_addr <= 'h00;
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end else if (sdo_data_ready == 1'b1) begin
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spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
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end
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end
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always @(posedge ctrl_clk) begin
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if (ctrl_cmd_wr_en == 1'b1) begin
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cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
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end
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end
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always @(posedge ctrl_clk) begin
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if (ctrl_mem_reset == 1'b1) begin
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ctrl_cmd_wr_addr <= 0;
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end else if (ctrl_cmd_wr_en == 1'b1) begin
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ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1;
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end
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end
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// request data from the DMA at the desired rate
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always @(posedge dma_clk) begin
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if (dma_xfer_req == 1'b0) begin
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dma_valid <= 1'b0;
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end else begin
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if ((trigger_s == 1'b1) && (dma_enable == 1'b1) && (spi_enable_s == 1'b1)) begin
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dma_valid <= 1'b1;
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end
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if (dma_valid == 1'b1) begin
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dma_valid <= 1'b0;
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end
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end
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if (dma_valid == 1'b1) begin
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sdo_mem[1] <= dma_data[15:8];
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sdo_mem[2] <= dma_data[ 7:0];
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end
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if (sequence_valid_s == 1'b1) begin
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sdo_mem[0] <= sequence_data_s;
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end
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end
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// rate controller
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assign dac_rstn_s = ~dac_rst_s;
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util_pulse_gen #(
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.PULSE_WIDTH(1)
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) i_trigger_gen (
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.clk (spi_clk),
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.rstn (dac_rstn_s),
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.pulse_width (1'b1),
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.pulse_period (pulse_period_s),
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.load_config (1'b1),
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.pulse (trigger_s));
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// offset of the sequencer registers are 8'h40
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always @(negedge up_rstn or posedge spi_clk) begin
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if (up_rstn == 1'b0) begin
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up_rdata <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end else begin
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up_rdata <= up_rdata_s[0] | up_rdata_s[1];
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up_rack <= up_rack_s[0] | up_rack_s[1];
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up_wack <= up_wack_s[0] | up_wack_s[1];
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end
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end
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// DAC common registermap
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assign pulse_period_s = {16'h0, dac_datarate_s};
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up_ad5766_sequencer #(
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.SEQ_ID(4)
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) i_sequencer (
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.sequence_clk (spi_clk),
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.sequence_rst (spi_mem_reset_s),
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.sequence_req (dma_valid),
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.sequence_valid (sequence_valid_s),
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.sequence_data (sequence_data_s),
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.up_rstn (up_rstn),
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.up_clk (spi_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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up_dac_common #(
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.COMMON_ID (0),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
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.FPGA_FAMILY (FPGA_FAMILY),
|
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.SPEED_GRADE (SPEED_GRADE),
|
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.DEV_PACKAGE (DEV_PACKAGE),
|
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.CONFIG (0),
|
||||
.CLK_EDGE_SEL (0),
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.DRP_DISABLE (6'h00),
|
||||
.USERPORTS_DISABLE (0),
|
||||
.GPIO_DISABLE (0)
|
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) i_dac_common (
|
||||
.mmcm_rst (),
|
||||
.dac_clk (spi_clk),
|
||||
.dac_rst (dac_rst_s),
|
||||
.dac_sync (),
|
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.dac_frame (),
|
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.dac_clksel (),
|
||||
.dac_custom_wr(),
|
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.dac_custom_rd(32'b0),
|
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.dac_custom_control(),
|
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.dac_status_if_busy(1'b0),
|
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.dac_par_type (),
|
||||
.dac_par_enb (),
|
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.dac_r1_mode (),
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.dac_datafmt (dac_datafmt),
|
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.dac_datarate (dac_datarate_s),
|
||||
.dac_status (1'b0),
|
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.dac_status_unf (dma_underflow),
|
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.dac_clk_ratio (32'b0),
|
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.up_dac_ce (),
|
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.up_pps_rcounter (32'b0),
|
||||
.up_pps_status (1'b0),
|
||||
.up_pps_irq_mask (),
|
||||
.up_drp_sel (),
|
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.up_drp_wr (),
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.up_drp_addr (),
|
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.up_drp_wdata (),
|
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.up_drp_rdata (16'b0),
|
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.up_drp_ready (1'b0),
|
||||
.up_drp_locked (1'b0),
|
||||
.up_usr_chanmax (),
|
||||
.dac_usr_chanmax (8'b0),
|
||||
.up_dac_gpio_in (32'b0),
|
||||
.up_dac_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (spi_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
// AXI wrapper
|
||||
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH (16)
|
||||
) i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (spi_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,462 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
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<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad5766/axi_ad5766.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="099ae3f8fc184560a374a4d0cb4961a3"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
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<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
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<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
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||||
<Option Name="WTXSimLaunchSim" Val="0"/>
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||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
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||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
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<Option Name="WTQuestaExportSim" Val="0"/>
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||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/ad_rst.v">
|
||||
<FileInfo>
|
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<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/up_ad5766_sequencer.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_clock_mon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_dac_common.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_cntrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_status.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/util_pulse_gen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad5766.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
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<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad5766"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
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<Config>
|
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
|
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SelectedSimModel" Val="rtl"/>
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<Option Name="PamDesignTestbench" Val=""/>
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||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
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<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
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||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
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</FileSet>
|
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
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</FileSet>
|
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</FileSets>
|
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<Simulators>
|
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<Simulator Name="XSim">
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<Option Name="Description" Val="Vivado Simulator"/>
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||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
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||||
</Simulator>
|
||||
<Simulator Name="VCS">
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||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
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</Simulator>
|
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<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
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</Simulators>
|
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<Runs Version="1" Minor="21">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
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||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
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||||
<Desc>Vivado Synthesis Defaults</Desc>
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||||
</StratHandle>
|
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<Step Id="synth_design"/>
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||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
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<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
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<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
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<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
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<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
|
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<Step Id="place_design"/>
|
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<Step Id="post_place_power_opt_design"/>
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||||
<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
|
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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</Runs>
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<MsgRule>
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="Vivado 12-1790"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="1"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
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<MsgAttr Name="StringsToMatch" Val="features"/>
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<MsgAttr Name="StringsToMatch" Val="should"/>
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<MsgAttr Name="StringsToMatch" Val="NOT"/>
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<MsgAttr Name="StringsToMatch" Val="be"/>
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||||
<MsgAttr Name="StringsToMatch" Val="used"/>
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<MsgAttr Name="StringsToMatch" Val="in"/>
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||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
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<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="INFO"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="RuleId" Val="10"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
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<MsgRule>
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="Place 30-73"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="11"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
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||||
<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="12"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
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</MsgRule>
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<MsgRule>
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="BD 41-1343"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="BD 41-1306"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
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||||
<MsgAttr Name="Limit" Val="-1"/>
|
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<MsgAttr Name="NewSeverity" Val="ERROR"/>
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<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,69 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ip
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create axi_ad5766
|
||||
adi_ip_files axi_ad5766 [list \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/util_pulse_gen.v" \
|
||||
"up_ad5766_sequencer.v" \
|
||||
"axi_ad5766.v" ]
|
||||
|
||||
adi_ip_properties axi_ad5766
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad5766 "bd/bd.tcl"
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
]
|
||||
|
||||
adi_add_bus "spi_engine_ctrl" "master" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{
|
||||
{"cmd_ready" "CMD_READY"} \
|
||||
{"cmd_valid" "CMD_VALID"} \
|
||||
{"cmd_data" "CMD_DATA"} \
|
||||
{"sdo_data_ready" "SDO_READY"} \
|
||||
{"sdo_data_valid" "SDO_VALID"} \
|
||||
{"sdo_data" "SDO_DATA"} \
|
||||
{"sdi_data_ready" "SDI_READY"} \
|
||||
{"sdi_data_valid" "SDI_VALID"} \
|
||||
{"sdi_data" "SDI_DATA"} \
|
||||
{"sync_ready" "SYNC_READY"} \
|
||||
{"sync_valid" "SYNC_VALID"} \
|
||||
{"sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus "spi_engine_offload_ctrl" "slave" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
|
||||
{ \
|
||||
{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
|
||||
{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
|
||||
{ "ctrl_enable" "ENABLE"} \
|
||||
{ "ctrl_enabled" "ENABLED"} \
|
||||
{ "ctrl_mem_reset" "MEM_RESET"} \
|
||||
}
|
||||
|
||||
adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
|
||||
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn"
|
||||
adi_add_bus_clock "dma_clk" "dma_fifo_tx"
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,260 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module up_ad5766_sequencer #(
|
||||
|
||||
parameter SEQ_ID = 0
|
||||
) (
|
||||
input sequence_clk,
|
||||
input sequence_rst,
|
||||
input sequence_req,
|
||||
output reg sequence_valid,
|
||||
output reg [ 7:0] sequence_data,
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack
|
||||
);
|
||||
|
||||
// registers
|
||||
|
||||
reg [ 7:0] up_sequencer[15:0];
|
||||
reg [ 3:0] up_endof_seq = 4'b0;
|
||||
reg up_xfer_req = 1'b0;
|
||||
reg [ 3:0] sequence_counter = 0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_wreq_s;
|
||||
wire up_rreq_s;
|
||||
wire [ 7:0] sequencer[15:0];
|
||||
wire [ 3:0] end_of_sequence;
|
||||
|
||||
integer i;
|
||||
|
||||
// sequence counter
|
||||
|
||||
always @(posedge sequence_clk) begin
|
||||
if (sequence_rst) begin
|
||||
sequence_counter <= 4'b0;
|
||||
end else if (sequence_req) begin
|
||||
sequence_counter <= (sequence_counter == end_of_sequence) ? 0 : sequence_counter + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// sequence output mux
|
||||
|
||||
always @(posedge sequence_clk) begin
|
||||
if (sequence_rst) begin
|
||||
sequence_data <= 16'b0;
|
||||
end
|
||||
else if (sequence_req) begin
|
||||
sequence_data <= sequencer[sequence_counter];
|
||||
end
|
||||
sequence_valid <= sequence_req;
|
||||
end
|
||||
|
||||
// decode block select
|
||||
|
||||
assign up_wreq_s = (up_waddr[13:8] == SEQ_ID) ? up_wreq : 1'b0;
|
||||
assign up_rreq_s = (up_raddr[13:8] == SEQ_ID) ? up_rreq : 1'b0;
|
||||
|
||||
// processor write interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
for (i=0; i<16; i=i+1) begin
|
||||
up_sequencer[i] <= 8'b0;
|
||||
end
|
||||
up_endof_seq <= 4'b0;
|
||||
up_wack <= 1'b0;
|
||||
end else begin
|
||||
up_wack <= up_wreq_s;
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h40)) begin
|
||||
up_sequencer[0] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h41)) begin
|
||||
up_sequencer[1] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h42)) begin
|
||||
up_sequencer[2] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h43)) begin
|
||||
up_sequencer[3] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h44)) begin
|
||||
up_sequencer[4] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h45)) begin
|
||||
up_sequencer[5] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h46)) begin
|
||||
up_sequencer[6] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h47)) begin
|
||||
up_sequencer[7] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h48)) begin
|
||||
up_sequencer[8] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h49)) begin
|
||||
up_sequencer[9] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4a)) begin
|
||||
up_sequencer[10] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4b)) begin
|
||||
up_sequencer[11] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4c)) begin
|
||||
up_sequencer[12] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4d)) begin
|
||||
up_sequencer[13] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4e)) begin
|
||||
up_sequencer[14] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4f)) begin
|
||||
up_sequencer[15] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_rack <= up_rreq_s;
|
||||
if (up_rreq_s == 1'b1) begin
|
||||
case (up_raddr[7:0])
|
||||
8'h40 : up_rdata <= {24'b0, up_sequencer[0]};
|
||||
8'h41 : up_rdata <= {24'b0, up_sequencer[1]};
|
||||
8'h42 : up_rdata <= {24'b0, up_sequencer[2]};
|
||||
8'h43 : up_rdata <= {24'b0, up_sequencer[3]};
|
||||
8'h44 : up_rdata <= {24'b0, up_sequencer[4]};
|
||||
8'h45 : up_rdata <= {24'b0, up_sequencer[5]};
|
||||
8'h46 : up_rdata <= {24'b0, up_sequencer[6]};
|
||||
8'h47 : up_rdata <= {24'b0, up_sequencer[7]};
|
||||
8'h48 : up_rdata <= {24'b0, up_sequencer[8]};
|
||||
8'h49 : up_rdata <= {24'b0, up_sequencer[9]};
|
||||
8'h4a : up_rdata <= {24'b0, up_sequencer[10]};
|
||||
8'h4b : up_rdata <= {24'b0, up_sequencer[11]};
|
||||
8'h4c : up_rdata <= {24'b0, up_sequencer[12]};
|
||||
8'h4d : up_rdata <= {24'b0, up_sequencer[13]};
|
||||
8'h4e : up_rdata <= {24'b0, up_sequencer[14]};
|
||||
8'h4f : up_rdata <= {24'b0, up_sequencer[15]};
|
||||
8'h60 : up_rdata <= {27'b0, up_xfer_req, up_endof_seq};
|
||||
endcase
|
||||
end else begin
|
||||
up_rdata <= 32'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// CDC
|
||||
|
||||
up_xfer_cntrl #(
|
||||
.DATA_WIDTH(132)
|
||||
) i_xfer_cntrl (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_data_cntrl ({up_endof_seq,
|
||||
up_sequencer[0],
|
||||
up_sequencer[1],
|
||||
up_sequencer[2],
|
||||
up_sequencer[3],
|
||||
up_sequencer[4],
|
||||
up_sequencer[5],
|
||||
up_sequencer[6],
|
||||
up_sequencer[7],
|
||||
up_sequencer[8],
|
||||
up_sequencer[9],
|
||||
up_sequencer[10],
|
||||
up_sequencer[11],
|
||||
up_sequencer[12],
|
||||
up_sequencer[13],
|
||||
up_sequencer[14],
|
||||
up_sequencer[15]}),
|
||||
.up_xfer_done (up_cntrl_xfer_done),
|
||||
.d_rst (sequence_rst),
|
||||
.d_clk (sequence_clk),
|
||||
.d_data_cntrl ({end_of_sequence,
|
||||
sequencer[0],
|
||||
sequencer[1],
|
||||
sequencer[2],
|
||||
sequencer[3],
|
||||
sequencer[4],
|
||||
sequencer[5],
|
||||
sequencer[6],
|
||||
sequencer[7],
|
||||
sequencer[8],
|
||||
sequencer[9],
|
||||
sequencer[10],
|
||||
sequencer[11],
|
||||
sequencer[12],
|
||||
sequencer[13],
|
||||
sequencer[14],
|
||||
sequencer[15]}));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,118 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CMD_MEM_ADDRESS_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SDO_MEM_ADDRESS_WIDTH" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to validate ASYNC_SPI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate CMD_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDO_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user