initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_ad7768
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/up_adc_channel.v
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GENERIC_DEPS += ../common/up_adc_common.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_ad7768.v
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GENERIC_DEPS += axi_ad7768_if.v
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XILINX_DEPS += ../common/ad_datafmt.v
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XILINX_DEPS += ../common/up_delay_cntrl.v
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XILINX_DEPS += ../xilinx/common/ad_data_clk.v
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XILINX_DEPS += ../xilinx/common/ad_data_in.v
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XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_ad7768_ip.tcl
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INTEL_DEPS += axi_ad7768_hw.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,364 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns / 1ps
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module axi_ad7768 #(
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parameter ID = 0,
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parameter NUM_CHANNELS = 8
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) (
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input adc_dovf,
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input clk_in,
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input ready_in,
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input [ 7:0] data_in,
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input adc_sshot,
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output adc_enable_0,
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output adc_enable_1,
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output adc_enable_2,
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output adc_enable_3,
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output adc_enable_4,
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output adc_enable_5,
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output adc_enable_6,
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output adc_enable_7,
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output adc_valid_0,
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output adc_valid_1,
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output adc_valid_2,
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output adc_valid_3,
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output adc_valid_4,
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output adc_valid_5,
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output adc_valid_6,
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output adc_valid_7,
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output [31:0] adc_data_0,
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output [31:0] adc_data_1,
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output [31:0] adc_data_2,
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output [31:0] adc_data_3,
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output [31:0] adc_data_4,
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output [31:0] adc_data_5,
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output [31:0] adc_data_6,
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output [31:0] adc_data_7,
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output [31:0] adc_data,
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output adc_clk,
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output adc_sync,
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output adc_reset,
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output adc_valid,
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output [ 7:0] adc_crc_ch_mismatch,
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready
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);
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// internal registers
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reg [31:0] up_rdata = 'd0;
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reg up_rack = 'd0;
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reg up_wack = 'd0;
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reg [31:0] up_rdata_r;
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reg up_rack_r;
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reg up_wack_r;
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// internal signals
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wire adc_rst_s;
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wire up_rstn;
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wire up_clk;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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wire adc_clk_s;
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wire up_wreq_s;
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wire up_rreq_s;
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wire [13:0] up_addr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s[0:8];
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wire [8:0] up_rack_s;
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wire [8:0] up_wack_s;
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wire [7:0] adc_enable;
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wire [4:0] adc_num_lanes;
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wire adc_crc_enable;
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wire [7:0] adc_status_header[0:7];
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wire [7:0] adc_crc_err;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign adc_clk = adc_clk_s;
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assign adc_reset = adc_rst_s;
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assign adc_enable_0 = adc_enable[0];
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assign adc_enable_1 = adc_enable[1];
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assign adc_enable_2 = adc_enable[2];
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assign adc_enable_3 = adc_enable[3];
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assign adc_enable_4 = adc_enable[4];
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assign adc_enable_5 = adc_enable[5];
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assign adc_enable_6 = adc_enable[6];
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assign adc_enable_7 = adc_enable[7];
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assign adc_valid_0 = adc_valid;
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assign adc_valid_1 = adc_valid;
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assign adc_valid_2 = adc_valid;
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assign adc_valid_3 = adc_valid;
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assign adc_valid_4 = adc_valid;
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assign adc_valid_5 = adc_valid;
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assign adc_valid_6 = adc_valid;
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assign adc_valid_7 = adc_valid;
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assign adc_crc_ch_mismatch = adc_crc_err;
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integer j;
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always @(*) begin
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up_rdata_r = 'h00;
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up_rack_r = 'h00;
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up_wack_r = 'h00;
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for (j = 0; j <= 8; j=j+1) begin
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up_rack_r = up_rack_r | up_rack_s[j];
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up_wack_r = up_wack_r | up_wack_s[j];
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up_rdata_r = up_rdata_r | up_rdata_s[j];
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rdata <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end else begin
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up_rdata <= up_rdata_r;
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up_rack <= up_rack_r;
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up_wack <= up_wack_r;
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end
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end
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// adc channels
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generate
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genvar i;
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for (i = 0; i < NUM_CHANNELS; i=i+1) begin : ad7768_channels
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up_adc_channel #(
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.CHANNEL_ID(i)
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) i_up_adc_channel (
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.adc_clk (adc_clk_s),
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.adc_rst (adc_rst_s),
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.adc_enable (adc_enable[i]),
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.adc_iqcor_enb (),
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.adc_dcfilt_enb (),
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.adc_dfmt_se (),
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.adc_dfmt_type (),
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.adc_dfmt_enable (),
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.adc_dcfilt_offset (),
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.adc_dcfilt_coeff (),
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.adc_iqcor_coeff_1 (),
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.adc_iqcor_coeff_2 (),
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.adc_pnseq_sel (),
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.adc_data_sel (),
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.adc_pn_err (1'b0),
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.adc_pn_oos (1'b0),
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.adc_or (1'b0),
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.adc_read_data ('d0),
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.adc_status_header(adc_status_header[i]),
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.adc_crc_err(adc_crc_err[i]),
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.up_adc_pn_err (),
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.up_adc_pn_oos (),
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.up_adc_or (),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_decimation_m (),
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.up_usr_decimation_n (),
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.adc_usr_datatype_be (1'b0),
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.adc_usr_datatype_signed (1'b1),
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.adc_usr_datatype_shift (8'd0),
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.adc_usr_datatype_total_bits (8'd32),
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.adc_usr_datatype_bits (8'd32),
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.adc_usr_decimation_m (16'd1),
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[i]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[i]),
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.up_rack (up_rack_s[i]));
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end
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endgenerate
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// adc interface
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axi_ad7768_if #(
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.NUM_CHANNELS(NUM_CHANNELS)
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) i_ad7768_if (
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.clk_in (clk_in),
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.ready_in (ready_in),
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.data_in (data_in),
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.adc_clk (adc_clk_s),
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.adc_valid (adc_valid),
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.adc_data (adc_data),
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.adc_sshot(adc_sshot),
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.adc_format(adc_num_lanes),
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.adc_crc_enable(adc_crc_enable),
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.adc_sync(adc_sync),
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.adc_data_0 (adc_data_0),
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.adc_data_1 (adc_data_1),
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.adc_data_2 (adc_data_2),
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.adc_data_3 (adc_data_3),
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.adc_data_4 (adc_data_4),
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.adc_data_5 (adc_data_5),
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.adc_data_6 (adc_data_6),
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.adc_data_7 (adc_data_7),
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.adc_crc_ch_mismatch(adc_crc_err),
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.adc_status_0(adc_status_header[0]),
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.adc_status_1(adc_status_header[1]),
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.adc_status_2(adc_status_header[2]),
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.adc_status_3(adc_status_header[3]),
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.adc_status_4(adc_status_header[4]),
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.adc_status_5(adc_status_header[5]),
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.adc_status_6(adc_status_header[6]),
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.adc_status_7(adc_status_header[7]));
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// adc up common
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up_adc_common #(
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.ID(ID)
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) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk_s),
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.adc_rst (adc_rst_s),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status ('h00),
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.adc_sync_status (1'b1),
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.adc_status_ovf (adc_dovf),
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.adc_clk_ratio (32'd1),
|
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.adc_start_code (),
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.adc_sref_sync (),
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.adc_sync (),
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.adc_ext_sync_arm(),
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.adc_ext_sync_disarm(),
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.adc_ext_sync_manual_req(),
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.adc_custom_control(),
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.adc_sdr_ddr_n(),
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.adc_symb_op(),
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.adc_symb_8_16b(),
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.adc_num_lanes(adc_num_lanes),
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.adc_crc_enable(adc_crc_enable),
|
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.up_pps_rcounter (32'b0),
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.up_pps_status (1'b0),
|
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.up_pps_irq_mask (),
|
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.up_adc_ce (),
|
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.up_status_pn_err (1'b0),
|
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.up_status_pn_oos (1'b0),
|
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.up_status_or (1'b0),
|
||||
.up_adc_r1_mode(),
|
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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.up_drp_wdata (),
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.up_drp_rdata (32'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.adc_config_wr (),
|
||||
.adc_config_ctrl (),
|
||||
.adc_config_rd ('d0),
|
||||
.adc_ctrl_status ('d0),
|
||||
.up_usr_chanmax_out (),
|
||||
.up_usr_chanmax_in (NUM_CHANNELS),
|
||||
.up_adc_gpio_in (32'b0),
|
||||
.up_adc_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[NUM_CHANNELS]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[NUM_CHANNELS]),
|
||||
.up_rack (up_rack_s[NUM_CHANNELS]));
|
||||
|
||||
// up bus interface
|
||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,526 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad7768/axi_ad7768.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="884f6cf47a34466d8843a15b819687b9"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
<FileInfo>
|
||||
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|
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||||
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||||
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|
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|
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|
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<File Path="$PPRDIR/../common/up_clock_mon.v">
|
||||
<FileInfo>
|
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<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
|
||||
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|
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</File>
|
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|
||||
<FileInfo>
|
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|
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||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
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|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_status.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
|
||||
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|
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|
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<File Path="$PPRDIR/axi_ad7768.v">
|
||||
<FileInfo>
|
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
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|
||||
</File>
|
||||
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|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
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</File>
|
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<File Path="$PPRDIR/../xilinx/common/ad_data_in.v">
|
||||
<FileInfo>
|
||||
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|
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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|
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</File>
|
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<File Path="$PPRDIR/../xilinx/common/ad_dcfilter.v">
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<FileInfo>
|
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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|
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<File Path="$PPRDIR/../common/ad_datafmt.v">
|
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<FileInfo>
|
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<File Path="$PPRDIR/../common/up_delay_cntrl.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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</File>
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<File Path="$PPRDIR/component.xml">
|
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<FileInfo SFType="IPXACT"/>
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</File>
|
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<File Path="$PPRDIR/bd/bd.tcl">
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<FileInfo>
|
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
|
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</File>
|
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<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad7768"/>
|
||||
</Config>
|
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</FileSet>
|
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
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<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_cntrl_constr.xdc">
|
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<FileInfo>
|
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<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
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|
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</File>
|
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<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
|
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<FileInfo>
|
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<Attr Name="UsedIn" Val="implementation"/>
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|
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</File>
|
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|
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<FileInfo>
|
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<Attr Name="UsedIn" Val="implementation"/>
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|
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|
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<File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
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|
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
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</Config>
|
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</FileSet>
|
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
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<Option Name="TopAutoSet" Val="TRUE"/>
|
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</Config>
|
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</FileSet>
|
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</FileSets>
|
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<Simulators>
|
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<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
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</Run>
|
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</Runs>
|
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
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<MsgAttr Name="Severity" Val="ANY"/>
|
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="1"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
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<MsgAttr Name="StringsToMatch" Val="features"/>
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<MsgAttr Name="StringsToMatch" Val="should"/>
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<MsgAttr Name="StringsToMatch" Val="NOT"/>
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<MsgAttr Name="StringsToMatch" Val="be"/>
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<MsgAttr Name="StringsToMatch" Val="used"/>
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<MsgAttr Name="StringsToMatch" Val="in"/>
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<MsgAttr Name="StringsToMatch" Val="production"/>
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<MsgAttr Name="StringsToMatch" Val="systems."/>
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|
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|
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<MsgAttr Name="NewSeverity" Val="INFO"/>
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<MsgAttr Name="Id" Val="Designutils 20-3303"/>
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<MsgAttr Name="RuleId" Val="10"/>
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<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
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<MsgRule>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="RuleId" Val="11"/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
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</MsgRule>
|
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<MsgRule>
|
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="Author" Val=""/>
|
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<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
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</MsgRule>
|
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<MsgRule>
|
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="BD 41-1343"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,82 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys
|
||||
source ../../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
set_module_property NAME axi_ad7768
|
||||
set_module_property DESCRIPTION "AXI AD7768 IP core"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_ad7768
|
||||
set_module_property ELABORATION_CALLBACK create_ports
|
||||
# source files
|
||||
|
||||
ad_ip_files axi_ad7768 [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"axi_ad7768_if.v" \
|
||||
"axi_ad7768.v"]
|
||||
|
||||
# IP parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME "ID"
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
|
||||
set group "General Configuration"
|
||||
|
||||
ad_ip_parameter NUM_CHANNELS INTEGER 8 true [list \
|
||||
DISPLAY_NAME "Number of channels" \
|
||||
DISPLAY_UNITS "channels" \
|
||||
ALLOWED_RANGES {4 8} \
|
||||
GROUP $group \
|
||||
]
|
||||
|
||||
# AXI4 Memory Mapped Interface
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 15
|
||||
|
||||
# ad7768_if and axi_gpreg ports
|
||||
|
||||
ad_interface signal adc_dovf input 1 ovf
|
||||
ad_interface signal clk_in input 1
|
||||
ad_interface signal ready_in input 1
|
||||
ad_interface signal data_in input 8
|
||||
|
||||
ad_interface reset adc_reset output 1
|
||||
ad_interface clock adc_clk output 1
|
||||
ad_interface signal adc_sync output 1 sync
|
||||
ad_interface signal adc_valid output 1 valid
|
||||
ad_interface signal adc_data output 32 data
|
||||
|
||||
set_interface_property if_adc_reset associatedClock if_adc_clk
|
||||
|
||||
proc create_ports {} {
|
||||
set num_channels [get_parameter_value "NUM_CHANNELS"]
|
||||
set samples_per_channel 1
|
||||
set sample_data_width 32
|
||||
set channel_data_width [expr $sample_data_width * $samples_per_channel]
|
||||
|
||||
for {set n 0} {$n < $num_channels} {incr n} {
|
||||
add_interface adc_ch_$n conduit end
|
||||
add_interface_port adc_ch_$n adc_enable_$n enable Output 1
|
||||
add_interface_port adc_ch_$n adc_data_$n data Output $sample_data_width
|
||||
add_interface_port adc_ch_$n adc_valid_$n valid Output 1
|
||||
set_interface_property adc_ch_$n associatedClock if_adc_clk
|
||||
set_interface_property adc_ch_$n associatedReset none
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,490 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad7768_if #(
|
||||
parameter NUM_CHANNELS = 8
|
||||
) (
|
||||
|
||||
// device-interface
|
||||
|
||||
input clk_in,
|
||||
input ready_in,
|
||||
input [ 7:0] data_in,
|
||||
|
||||
// data path interface
|
||||
|
||||
output adc_clk,
|
||||
output adc_valid,
|
||||
output [31:0] adc_data,
|
||||
output adc_sync,
|
||||
output [31:0] adc_data_0,
|
||||
output [31:0] adc_data_1,
|
||||
output [31:0] adc_data_2,
|
||||
output [31:0] adc_data_3,
|
||||
output [31:0] adc_data_4,
|
||||
output [31:0] adc_data_5,
|
||||
output [31:0] adc_data_6,
|
||||
output [31:0] adc_data_7,
|
||||
output [ 7:0] adc_status_0,
|
||||
output [ 7:0] adc_status_1,
|
||||
output [ 7:0] adc_status_2,
|
||||
output [ 7:0] adc_status_3,
|
||||
output [ 7:0] adc_status_4,
|
||||
output [ 7:0] adc_status_5,
|
||||
output [ 7:0] adc_status_6,
|
||||
output [ 7:0] adc_status_7,
|
||||
output [ 7:0] adc_crc_ch_mismatch,
|
||||
|
||||
// control interface
|
||||
|
||||
input adc_sshot,
|
||||
input [ 4:0] adc_format,
|
||||
input adc_crc_enable
|
||||
);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 95:0] adc_crc_data_s [0:7];
|
||||
reg [ 7:0] adc_crc_read_data [0:7];
|
||||
reg [ 7:0] adc_crc_reg [0:7];
|
||||
reg [ 31:0] adc_data_s_d [0:7];
|
||||
reg [ 31:0] adc_data_s [0:7];
|
||||
reg [ 31:0] adc_data_int = 'd0;
|
||||
reg [ 3:0] adc_crc_cnt = 'd0;
|
||||
reg [ 8:0] adc_cnt_p = 'd0;
|
||||
reg [255:0] adc_data_p = 'd0;
|
||||
reg [255:0] adc_ch_data_d0 = 'd0;
|
||||
reg [255:0] adc_ch_data_d1 = 'd0;
|
||||
reg [255:0] adc_ch_data_d2 = 'd0;
|
||||
reg [255:0] adc_ch_data_d3 = 'd0;
|
||||
reg [255:0] adc_ch_data_d4 = 'd0;
|
||||
reg [255:0] adc_ch_data_d5 = 'd0;
|
||||
reg [255:0] adc_ch_data_d6 = 'd0;
|
||||
reg [255:0] adc_ch_data_d7 = 'd0;
|
||||
reg [ 7:0] adc_status_0_s = 'd0;
|
||||
reg [ 7:0] adc_status_1_s = 'd0;
|
||||
reg [ 7:0] adc_status_2_s = 'd0;
|
||||
reg [ 7:0] adc_status_3_s = 'd0;
|
||||
reg [ 7:0] adc_status_4_s = 'd0;
|
||||
reg [ 7:0] adc_status_5_s = 'd0;
|
||||
reg [ 7:0] adc_status_6_s = 'd0;
|
||||
reg [ 7:0] adc_status_7_s = 'd0;
|
||||
reg [ 7:0] adc_crc_ch_mismatch_s = 'd0;
|
||||
reg adc_valid_s = 'b0;
|
||||
reg adc_valid_s_d = 'b0;
|
||||
reg adc_crc_valid_p = 'b0;
|
||||
reg sync_ss = 'd0;
|
||||
reg adc_valid_p = 'd0;
|
||||
reg adc_ready = 'd0;
|
||||
reg adc_cnt_enable_s_d = 'b0;
|
||||
// internal signals
|
||||
|
||||
wire [ 7:0] adc_crc_in_s [0:7];
|
||||
wire [ 7:0] adc_crc_s [0:7];
|
||||
wire [ 3:0] adc_crc_cnt_value;
|
||||
wire [ 8:0] adc_cnt_value;
|
||||
wire [ 7:0] adc_crc_mismatch_s;
|
||||
wire adc_crc_cnt_enable_s;
|
||||
wire adc_cnt_enable_s;
|
||||
wire adc_ready_in_s;
|
||||
wire crc_in_sync_n;
|
||||
|
||||
// function (crc8)
|
||||
|
||||
function [ 7:0] crc8;
|
||||
input [95:0] din;
|
||||
input [ 7:0] cin;
|
||||
reg [ 7:0] cout;
|
||||
begin
|
||||
|
||||
cout[0] = cin[0] ^ cin[2] ^ cin[4] ^ cin[5] ^ cin[6] ^ din[0] ^ din[6] ^ din[7] ^ din[8] ^ din[12] ^ din[14] ^ din[16] ^
|
||||
din[18] ^ din[19] ^ din[21] ^ din[23] ^ din[28] ^ din[30] ^ din[31] ^ din[34] ^ din[35] ^ din[39] ^ din[40] ^ din[43] ^
|
||||
din[45] ^ din[48] ^ din[49] ^ din[50] ^ din[52] ^ din[53] ^ din[54] ^ din[56] ^ din[60] ^ din[63] ^ din[64] ^ din[66] ^
|
||||
din[67] ^ din[68] ^ din[69] ^ din[74] ^ din[75] ^ din[77] ^ din[80] ^ din[84] ^ din[85] ^ din[86] ^ din[87] ^ din[88] ^
|
||||
din[90] ^ din[92] ^ din[93] ^ din[94];
|
||||
cout[1] = cin[1] ^ cin[2] ^ cin[3] ^ cin[4] ^ cin[7] ^ din[0] ^ din[1] ^ din[6] ^ din[9] ^ din[12] ^ din[13] ^ din[14] ^
|
||||
din[15] ^ din[16] ^ din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23] ^ din[24] ^ din[28] ^ din[29] ^ din[30] ^
|
||||
din[32] ^ din[34] ^ din[36] ^ din[39] ^ din[41] ^ din[43] ^ din[44] ^ din[45] ^ din[46] ^ din[48] ^ din[51] ^ din[52] ^
|
||||
din[55] ^ din[56] ^ din[57] ^ din[60] ^ din[61] ^ din[63] ^ din[65] ^ din[66] ^ din[70] ^ din[74] ^ din[76] ^ din[77] ^
|
||||
din[78] ^ din[80] ^ din[81] ^ din[84] ^ din[89] ^ din[90] ^ din[91] ^ din[92] ^ din[95];
|
||||
cout[2] = cin[0] ^ cin[3] ^ cin[6] ^ din[0] ^ din[1] ^ din[2] ^ din[6] ^ din[8] ^ din[10] ^ din[12] ^ din[13] ^ din[15] ^
|
||||
din[17] ^ din[22] ^ din[24] ^ din[25] ^ din[28] ^ din[29] ^ din[33] ^ din[34] ^ din[37] ^ din[39] ^ din[42] ^ din[43] ^
|
||||
din[44] ^ din[46] ^ din[47] ^ din[48] ^ din[50] ^ din[54] ^ din[57] ^ din[58] ^ din[60] ^ din[61] ^ din[62] ^ din[63] ^
|
||||
din[68] ^ din[69] ^ din[71] ^ din[74] ^ din[78] ^ din[79] ^ din[80] ^ din[81] ^ din[82] ^ din[84] ^ din[86] ^ din[87] ^
|
||||
din[88] ^ din[91] ^ din[94];
|
||||
cout[3] = cin[0] ^ cin[1] ^ cin[4] ^ cin[7] ^ din[1] ^ din[2] ^ din[3] ^ din[7] ^ din[9] ^ din[11] ^ din[13] ^ din[14] ^
|
||||
din[16] ^ din[18] ^ din[23] ^ din[25] ^ din[26] ^ din[29] ^ din[30] ^ din[34] ^ din[35] ^ din[38] ^ din[40] ^ din[43] ^
|
||||
din[44] ^ din[45] ^ din[47] ^ din[48] ^ din[49] ^ din[51] ^ din[55] ^ din[58] ^ din[59] ^ din[61] ^ din[62] ^ din[63] ^
|
||||
din[64] ^ din[69] ^ din[70] ^ din[72] ^ din[75] ^ din[79] ^ din[80] ^ din[81] ^ din[82] ^ din[83] ^ din[85] ^ din[87] ^
|
||||
din[88] ^ din[89] ^ din[92] ^ din[95];
|
||||
cout[4] = cin[0] ^ cin[1] ^ cin[2] ^ cin[5] ^ din[2] ^ din[3] ^ din[4] ^ din[8] ^ din[10] ^ din[12] ^ din[14] ^ din[15] ^
|
||||
din[17] ^ din[19] ^ din[24] ^ din[26] ^ din[27] ^ din[30] ^ din[31] ^ din[35] ^ din[36] ^ din[39] ^ din[41] ^ din[44] ^
|
||||
din[45] ^ din[46] ^ din[48] ^ din[49] ^ din[50] ^ din[52] ^ din[56] ^ din[59] ^ din[60] ^ din[62] ^ din[63] ^ din[64] ^
|
||||
din[65] ^ din[70] ^ din[71] ^ din[73] ^ din[76] ^ din[80] ^ din[81] ^ din[82] ^ din[83] ^ din[84] ^ din[86] ^ din[88] ^
|
||||
din[89] ^ din[90] ^ din[93];
|
||||
cout[5] = cin[1] ^ cin[2] ^ cin[3] ^ cin[6] ^ din[3] ^ din[4] ^ din[5] ^ din[9] ^ din[11] ^ din[13] ^ din[15] ^ din[16] ^
|
||||
din[18] ^ din[20] ^ din[25] ^ din[27] ^ din[28] ^ din[31] ^ din[32] ^ din[36] ^ din[37] ^ din[40] ^ din[42] ^ din[45] ^
|
||||
din[46] ^ din[47] ^ din[49] ^ din[50] ^ din[51] ^ din[53] ^ din[57] ^ din[60] ^ din[61] ^ din[63] ^ din[64] ^ din[65] ^
|
||||
din[66] ^ din[71] ^ din[72] ^ din[74] ^ din[77] ^ din[81] ^ din[82] ^ din[83] ^ din[84] ^ din[85] ^ din[87] ^ din[89] ^
|
||||
din[90] ^ din[91] ^ din[94];
|
||||
cout[6] = cin[0] ^ cin[2] ^ cin[3] ^ cin[4] ^ cin[7] ^ din[4] ^ din[5] ^ din[6] ^ din[10] ^ din[12] ^ din[14] ^ din[16] ^
|
||||
din[17] ^ din[19] ^ din[21] ^ din[26] ^ din[28] ^ din[29] ^ din[32] ^ din[33] ^ din[37] ^ din[38] ^ din[41] ^ din[43] ^
|
||||
din[46] ^ din[47] ^ din[48] ^ din[50] ^ din[51] ^ din[52] ^ din[54] ^ din[58] ^ din[61] ^ din[62] ^ din[64] ^ din[65] ^
|
||||
din[66] ^ din[67] ^ din[72] ^ din[73] ^ din[75] ^ din[78] ^ din[82] ^ din[83] ^ din[84] ^ din[85] ^ din[86] ^ din[88] ^
|
||||
din[90] ^ din[91] ^ din[92] ^ din[95];
|
||||
cout[7] = cin[1] ^ cin[3] ^ cin[4] ^ cin[5] ^ din[5] ^ din[6] ^ din[7] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ din[18] ^
|
||||
din[20] ^ din[22] ^ din[27] ^ din[29] ^ din[30] ^ din[33] ^ din[34] ^ din[38] ^ din[39] ^ din[42] ^ din[44] ^ din[47] ^
|
||||
din[48] ^ din[49] ^ din[51] ^ din[52] ^ din[53] ^ din[55] ^ din[59] ^ din[62] ^ din[63] ^ din[65] ^ din[66] ^ din[67] ^
|
||||
din[68] ^ din[73] ^ din[74] ^ din[76] ^ din[79] ^ din[83] ^ din[84] ^ din[85] ^ din[86] ^ din[87] ^ din[89] ^ din[91] ^
|
||||
din[92] ^ din[93];
|
||||
crc8 = cout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
assign adc_ready_in_s = ready_in;
|
||||
assign adc_clk = clk_in;
|
||||
assign adc_valid = adc_valid_s_d;
|
||||
assign adc_data= adc_data_int;
|
||||
assign adc_data_0 = adc_data_s_d[0];
|
||||
assign adc_data_1 = adc_data_s_d[1];
|
||||
assign adc_data_2 = adc_data_s_d[2];
|
||||
assign adc_data_3 = adc_data_s_d[3];
|
||||
assign adc_data_4 = adc_data_s_d[4];
|
||||
assign adc_data_5 = adc_data_s_d[5];
|
||||
assign adc_data_6 = adc_data_s_d[6];
|
||||
assign adc_data_7 = adc_data_s_d[7];
|
||||
assign adc_status_0 = adc_status_0_s;
|
||||
assign adc_status_1 = adc_status_1_s;
|
||||
assign adc_status_2 = adc_status_2_s;
|
||||
assign adc_status_3 = adc_status_3_s;
|
||||
assign adc_status_4 = adc_status_4_s;
|
||||
assign adc_status_5 = adc_status_5_s;
|
||||
assign adc_status_6 = adc_status_6_s;
|
||||
assign adc_status_7 = adc_status_7_s;
|
||||
assign adc_crc_ch_mismatch = adc_crc_ch_mismatch_s;
|
||||
assign crc_in_sync_n = |adc_crc_mismatch_s;
|
||||
|
||||
// CRC check
|
||||
|
||||
assign adc_crc_mismatch_s[0] = (adc_crc_read_data[0] == adc_crc_s[0]) ? 1'b0 : adc_crc_enable;
|
||||
assign adc_crc_mismatch_s[1] = (adc_crc_read_data[1] == adc_crc_s[1]) ? 1'b0 : adc_crc_enable;
|
||||
assign adc_crc_mismatch_s[2] = (adc_crc_read_data[2] == adc_crc_s[2]) ? 1'b0 : adc_crc_enable;
|
||||
assign adc_crc_mismatch_s[3] = (adc_crc_read_data[3] == adc_crc_s[3]) ? 1'b0 : adc_crc_enable;
|
||||
assign adc_crc_mismatch_s[4] = (adc_crc_read_data[4] == adc_crc_s[4] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable;
|
||||
assign adc_crc_mismatch_s[5] = (adc_crc_read_data[5] == adc_crc_s[5] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable;
|
||||
assign adc_crc_mismatch_s[6] = (adc_crc_read_data[6] == adc_crc_s[6] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable;
|
||||
assign adc_crc_mismatch_s[7] = (adc_crc_read_data[7] == adc_crc_s[7] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable;
|
||||
|
||||
assign adc_crc_s[0] = crc8(adc_crc_data_s[0], adc_crc_in_s[0]);
|
||||
assign adc_crc_s[1] = crc8(adc_crc_data_s[1], adc_crc_in_s[1]);
|
||||
assign adc_crc_s[2] = crc8(adc_crc_data_s[2], adc_crc_in_s[2]);
|
||||
assign adc_crc_s[3] = crc8(adc_crc_data_s[3], adc_crc_in_s[3]);
|
||||
assign adc_crc_s[4] = crc8(adc_crc_data_s[4], adc_crc_in_s[4]);
|
||||
assign adc_crc_s[5] = crc8(adc_crc_data_s[5], adc_crc_in_s[5]);
|
||||
assign adc_crc_s[6] = crc8(adc_crc_data_s[6], adc_crc_in_s[6]);
|
||||
assign adc_crc_s[7] = crc8(adc_crc_data_s[7], adc_crc_in_s[7]);
|
||||
|
||||
assign adc_crc_in_s[0] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[0];
|
||||
assign adc_crc_in_s[1] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[1];
|
||||
assign adc_crc_in_s[2] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[2];
|
||||
assign adc_crc_in_s[3] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[3];
|
||||
assign adc_crc_in_s[4] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[4];
|
||||
assign adc_crc_in_s[5] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[5];
|
||||
assign adc_crc_in_s[6] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[6];
|
||||
assign adc_crc_in_s[7] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[7];
|
||||
|
||||
assign adc_sync = adc_valid_s & ~adc_valid_s_d & sync_ss;
|
||||
|
||||
// serial output data
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_valid_s) begin
|
||||
sync_ss <= 1'h1;
|
||||
end else if (adc_sync) begin
|
||||
sync_ss <= 1'h0;
|
||||
end
|
||||
|
||||
adc_data_int <= adc_ch_data_d0[((32*0)+31):(32*0)] | adc_ch_data_d1[((32*1)+31):(32*1)] | adc_ch_data_d2[((32*2)+31):(32*2)] |
|
||||
adc_ch_data_d3[((32*3)+31):(32*3)] | adc_ch_data_d4[((32*4)+31):(32*4)] | adc_ch_data_d5[((32*5)+31):(32*5)] |
|
||||
adc_ch_data_d6[((32*6)+31):(32*6)] | adc_ch_data_d7[((32*7)+31):(32*7)];
|
||||
|
||||
adc_ch_data_d0 <= {adc_ch_data_d0[((32*6)+31):(32*0)],adc_data_s[0]};
|
||||
adc_ch_data_d1 <= {adc_ch_data_d1[((32*6)+31):(32*0)],adc_data_s[1]};
|
||||
adc_ch_data_d2 <= {adc_ch_data_d2[((32*6)+31):(32*0)],adc_data_s[2]};
|
||||
adc_ch_data_d3 <= {adc_ch_data_d3[((32*6)+31):(32*0)],adc_data_s[3]};
|
||||
adc_ch_data_d4 <= {adc_ch_data_d4[((32*6)+31):(32*0)],adc_data_s[4]};
|
||||
adc_ch_data_d5 <= {adc_ch_data_d5[((32*6)+31):(32*0)],adc_data_s[5]};
|
||||
adc_ch_data_d6 <= {adc_ch_data_d6[((32*6)+31):(32*0)],adc_data_s[6]};
|
||||
adc_ch_data_d7 <= {adc_ch_data_d7[((32*6)+31):(32*0)],adc_data_s[7]};
|
||||
|
||||
end
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
|
||||
adc_status_0_s <= (adc_valid_s == 1'b1) ? adc_data_s[0][31:24]: adc_status_0_s;
|
||||
adc_status_1_s <= (adc_valid_s == 1'b1) ? adc_data_s[1][31:24]: adc_status_1_s;
|
||||
adc_status_2_s <= (adc_valid_s == 1'b1) ? adc_data_s[2][31:24]: adc_status_2_s;
|
||||
adc_status_3_s <= (adc_valid_s == 1'b1) ? adc_data_s[3][31:24]: adc_status_3_s;
|
||||
adc_status_4_s <= (adc_valid_s == 1'b1) ? adc_data_s[4][31:24]: adc_status_4_s;
|
||||
adc_status_5_s <= (adc_valid_s == 1'b1) ? adc_data_s[5][31:24]: adc_status_5_s;
|
||||
adc_status_6_s <= (adc_valid_s == 1'b1) ? adc_data_s[6][31:24]: adc_status_6_s;
|
||||
adc_status_7_s <= (adc_valid_s == 1'b1) ? adc_data_s[7][31:24]: adc_status_7_s;
|
||||
adc_crc_ch_mismatch_s[0] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[0] : adc_crc_ch_mismatch_s[0];
|
||||
adc_crc_ch_mismatch_s[1] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[1] : adc_crc_ch_mismatch_s[1];
|
||||
adc_crc_ch_mismatch_s[2] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[2] : adc_crc_ch_mismatch_s[2];
|
||||
adc_crc_ch_mismatch_s[3] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[3] : adc_crc_ch_mismatch_s[3];
|
||||
adc_crc_ch_mismatch_s[4] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[4] : adc_crc_ch_mismatch_s[4];
|
||||
adc_crc_ch_mismatch_s[5] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[5] : adc_crc_ch_mismatch_s[5];
|
||||
adc_crc_ch_mismatch_s[6] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[6] : adc_crc_ch_mismatch_s[6];
|
||||
adc_crc_ch_mismatch_s[7] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[7] : adc_crc_ch_mismatch_s[7];
|
||||
|
||||
end
|
||||
|
||||
// 4 samples counter for crc
|
||||
|
||||
assign adc_crc_cnt_value = 4'h4;
|
||||
|
||||
assign adc_crc_cnt_enable_s = (adc_crc_cnt < adc_crc_cnt_value) ? 1'b1 : 1'b0;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if ((crc_in_sync_n == 1'b0) || (adc_crc_enable == 1'b0) || (adc_crc_cnt_enable_s ==1'b0)) begin
|
||||
adc_crc_cnt <= 4'd0;
|
||||
end else if ((adc_valid_p == 1'b1) && (adc_crc_enable == 1'b1)) begin
|
||||
adc_crc_cnt <= adc_crc_cnt + 1'b1;
|
||||
end
|
||||
|
||||
if (adc_crc_cnt == adc_crc_cnt_value) begin
|
||||
adc_crc_valid_p <= 1'b1;
|
||||
end else begin
|
||||
adc_crc_valid_p <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// capturing crc data
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if(adc_valid_s == 1'b1) begin
|
||||
adc_crc_data_s[0] <= {adc_crc_data_s[0][71:0],adc_data_s[0][23:0]};
|
||||
adc_crc_data_s[1] <= {adc_crc_data_s[1][71:0],adc_data_s[1][23:0]};
|
||||
adc_crc_data_s[2] <= {adc_crc_data_s[2][71:0],adc_data_s[2][23:0]};
|
||||
adc_crc_data_s[3] <= {adc_crc_data_s[3][71:0],adc_data_s[3][23:0]};
|
||||
adc_crc_data_s[4] <= {adc_crc_data_s[4][71:0],adc_data_s[4][23:0]};
|
||||
adc_crc_data_s[5] <= {adc_crc_data_s[5][71:0],adc_data_s[5][23:0]};
|
||||
adc_crc_data_s[6] <= {adc_crc_data_s[6][71:0],adc_data_s[6][23:0]};
|
||||
adc_crc_data_s[7] <= {adc_crc_data_s[7][71:0],adc_data_s[7][23:0]};
|
||||
adc_crc_read_data[0] <=adc_data_s[0][31:24];
|
||||
adc_crc_read_data[1] <=adc_data_s[1][31:24];
|
||||
adc_crc_read_data[2] <=adc_data_s[2][31:24];
|
||||
adc_crc_read_data[3] <=adc_data_s[3][31:24];
|
||||
adc_crc_read_data[4] <=adc_data_s[4][31:24];
|
||||
adc_crc_read_data[5] <=adc_data_s[5][31:24];
|
||||
adc_crc_read_data[6] <=adc_data_s[6][31:24];
|
||||
adc_crc_read_data[7] <=adc_data_s[7][31:24];
|
||||
adc_crc_reg[0] <= adc_crc_s[0];
|
||||
adc_crc_reg[1] <= adc_crc_s[1];
|
||||
adc_crc_reg[2] <= adc_crc_s[2];
|
||||
adc_crc_reg[3] <= adc_crc_s[3];
|
||||
adc_crc_reg[4] <= adc_crc_s[4];
|
||||
adc_crc_reg[5] <= adc_crc_s[5];
|
||||
adc_crc_reg[6] <= adc_crc_s[6];
|
||||
adc_crc_reg[7] <= adc_crc_s[7];
|
||||
end else begin
|
||||
adc_crc_data_s[0] <= adc_crc_data_s[0];
|
||||
adc_crc_data_s[1] <= adc_crc_data_s[1];
|
||||
adc_crc_data_s[2] <= adc_crc_data_s[2];
|
||||
adc_crc_data_s[3] <= adc_crc_data_s[3];
|
||||
adc_crc_data_s[4] <= adc_crc_data_s[4];
|
||||
adc_crc_data_s[5] <= adc_crc_data_s[5];
|
||||
adc_crc_data_s[6] <= adc_crc_data_s[6];
|
||||
adc_crc_data_s[7] <= adc_crc_data_s[7];
|
||||
adc_crc_read_data[0] <= 8'b0;
|
||||
adc_crc_read_data[1] <= 8'b0;
|
||||
adc_crc_read_data[2] <= 8'b0;
|
||||
adc_crc_read_data[3] <= 8'b0;
|
||||
adc_crc_read_data[4] <= 8'b0;
|
||||
adc_crc_read_data[5] <= 8'b0;
|
||||
adc_crc_read_data[6] <= 8'b0;
|
||||
adc_crc_read_data[7] <= 8'b0;
|
||||
adc_crc_reg[0] <= 'b0;
|
||||
adc_crc_reg[1] <= 'b0;
|
||||
adc_crc_reg[2] <= 'b0;
|
||||
adc_crc_reg[3] <= 'b0;
|
||||
adc_crc_reg[4] <= 'b0;
|
||||
adc_crc_reg[5] <= 'b0;
|
||||
adc_crc_reg[6] <= 'b0;
|
||||
adc_crc_reg[7] <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// data capturing counter
|
||||
|
||||
assign adc_cnt_value = (adc_format == 'h1 && NUM_CHANNELS == 8) ? 'hff :
|
||||
(((adc_format == 'h2 && NUM_CHANNELS == 8) || (adc_format == 'h1 && NUM_CHANNELS == 4)) ? 'h7f : 'h1f);
|
||||
|
||||
assign adc_cnt_enable_s = (adc_cnt_p < adc_cnt_value) ? 1'b1 : 1'b0;
|
||||
|
||||
always @(negedge adc_clk) begin
|
||||
adc_cnt_enable_s_d <= adc_cnt_enable_s;
|
||||
if (adc_ready == 1'b0) begin
|
||||
adc_cnt_p <= 'h000;
|
||||
end else if (adc_cnt_enable_s == 1'b1) begin
|
||||
adc_cnt_p <= adc_cnt_p + 1'b1;
|
||||
end
|
||||
if (adc_cnt_p == adc_cnt_value && adc_cnt_enable_s_d == 1'b1) begin
|
||||
adc_valid_p <= 1'b1;
|
||||
end else begin
|
||||
adc_valid_p <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
//delay data 1 clk for data, data_valid and crc mismatch for alignment
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_valid_s == 1'b1) begin
|
||||
adc_data_s_d[0] <= adc_data_s[0];
|
||||
adc_data_s_d[1] <= adc_data_s[1];
|
||||
adc_data_s_d[2] <= adc_data_s[2];
|
||||
adc_data_s_d[3] <= adc_data_s[3];
|
||||
adc_data_s_d[4] <= adc_data_s[4];
|
||||
adc_data_s_d[5] <= adc_data_s[5];
|
||||
adc_data_s_d[6] <= adc_data_s[6];
|
||||
adc_data_s_d[7] <= adc_data_s[7];
|
||||
adc_valid_s_d <= adc_valid_s;
|
||||
end else begin
|
||||
adc_data_s_d[0] <= 32'b0;
|
||||
adc_data_s_d[1] <= 32'b0;
|
||||
adc_data_s_d[2] <= 32'b0;
|
||||
adc_data_s_d[3] <= 32'b0;
|
||||
adc_data_s_d[4] <= 32'b0;
|
||||
adc_data_s_d[5] <= 32'b0;
|
||||
adc_data_s_d[6] <= 32'b0;
|
||||
adc_data_s_d[7] <= 32'b0;
|
||||
adc_valid_s_d <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_valid_p == 1'b1) begin
|
||||
if(adc_format == 'h1 && NUM_CHANNELS == 8) begin // 1 active line
|
||||
adc_data_s[0] <= adc_data_p[((32*7)+31):(32*7)];
|
||||
adc_data_s[1] <= adc_data_p[((32*6)+31):(32*6)];
|
||||
adc_data_s[2] <= adc_data_p[((32*5)+31):(32*5)];
|
||||
adc_data_s[3] <= adc_data_p[((32*4)+31):(32*4)];
|
||||
adc_data_s[4] <= adc_data_p[((32*3)+31):(32*3)];
|
||||
adc_data_s[5] <= adc_data_p[((32*2)+31):(32*2)];
|
||||
adc_data_s[6] <= adc_data_p[((32*1)+31):(32*1)];
|
||||
adc_data_s[7] <= adc_data_p[((32*0)+31):(32*0)];
|
||||
end else if((adc_format == 'h2 && NUM_CHANNELS == 8) || (adc_format == 'h1 && NUM_CHANNELS == 4)) begin // 2 active lines or 1 for ad7768-4
|
||||
adc_data_s[0] <= adc_data_p[((32*3)+31):(32*3)];
|
||||
adc_data_s[1] <= adc_data_p[((32*2)+31):(32*2)];
|
||||
adc_data_s[2] <= adc_data_p[((32*1)+31):(32*1)];
|
||||
adc_data_s[3] <= adc_data_p[((32*0)+31):(32*0)];
|
||||
adc_data_s[4] <= adc_data_p[((32*7)+31):(32*7)];
|
||||
adc_data_s[5] <= adc_data_p[((32*6)+31):(32*6)];
|
||||
adc_data_s[6] <= adc_data_p[((32*5)+31):(32*5)];
|
||||
adc_data_s[7] <= adc_data_p[((32*4)+31):(32*4)];
|
||||
end else begin // 8 active lines
|
||||
adc_data_s[0] <= adc_data_p[((32*0)+31):(32*0)];
|
||||
adc_data_s[1] <= adc_data_p[((32*1)+31):(32*1)];
|
||||
adc_data_s[2] <= adc_data_p[((32*2)+31):(32*2)];
|
||||
adc_data_s[3] <= adc_data_p[((32*3)+31):(32*3)];
|
||||
adc_data_s[4] <= adc_data_p[((32*4)+31):(32*4)];
|
||||
adc_data_s[5] <= adc_data_p[((32*5)+31):(32*5)];
|
||||
adc_data_s[6] <= adc_data_p[((32*6)+31):(32*6)];
|
||||
adc_data_s[7] <= adc_data_p[((32*7)+31):(32*7)];
|
||||
end
|
||||
adc_valid_s <= adc_valid_p;
|
||||
end else begin
|
||||
adc_data_s[0] <= 32'b0;
|
||||
adc_data_s[1] <= 32'b0;
|
||||
adc_data_s[2] <= 32'b0;
|
||||
adc_data_s[3] <= 32'b0;
|
||||
adc_data_s[4] <= 32'b0;
|
||||
adc_data_s[5] <= 32'b0;
|
||||
adc_data_s[6] <= 32'b0;
|
||||
adc_data_s[7] <= 32'b0;
|
||||
adc_valid_s <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// data (individual lanes)
|
||||
|
||||
always @(negedge adc_clk) begin
|
||||
if(adc_format == 'h1 && NUM_CHANNELS == 8) begin // 1 active line for ad7768
|
||||
if (adc_cnt_p == 'h0) begin
|
||||
adc_data_p[((256*0)+255):(256*0)] <= {255'd0, data_in[0]};
|
||||
end else begin
|
||||
adc_data_p[((256*0)+255):(255*0)] <= {adc_data_p[((256*0)+254):(256*0)], data_in[0]};
|
||||
end
|
||||
end else if((adc_format == 'h2 && NUM_CHANNELS == 8) || (adc_format == 'h1 && NUM_CHANNELS == 4)) begin // 2 active lines or 1 active lane for ad7768-4
|
||||
if (adc_cnt_p == 'h0) begin
|
||||
adc_data_p[((128*0)+127):(128*0)] <= {127'd0, data_in[0]};
|
||||
adc_data_p[((128*1)+127):(128*1)] <= {127'd0, data_in[1]};
|
||||
end else begin
|
||||
adc_data_p[((128*0)+127):(128*0)] <= {adc_data_p[((128*0)+126):(128*0)], data_in[0]};
|
||||
adc_data_p[((128*1)+127):(128*1)] <= {adc_data_p[((128*1)+126):(128*1)], data_in[1]};
|
||||
end
|
||||
end else begin // 8 active lines or 4 active lane for ad7768-4
|
||||
if (adc_cnt_p == 'h0) begin
|
||||
adc_data_p[((32*0)+31):(32*0)] <= {31'd0, data_in[0]};
|
||||
adc_data_p[((32*1)+31):(32*1)] <= {31'd0, data_in[1]};
|
||||
adc_data_p[((32*2)+31):(32*2)] <= {31'd0, data_in[2]};
|
||||
adc_data_p[((32*3)+31):(32*3)] <= {31'd0, data_in[3]};
|
||||
adc_data_p[((32*4)+31):(32*4)] <= {31'd0, data_in[4]};
|
||||
adc_data_p[((32*5)+31):(32*5)] <= {31'd0, data_in[5]};
|
||||
adc_data_p[((32*6)+31):(32*6)] <= {31'd0, data_in[6]};
|
||||
adc_data_p[((32*7)+31):(32*7)] <= {31'd0, data_in[7]};
|
||||
end else begin
|
||||
adc_data_p[((32*0)+31):(32*0)] <= {adc_data_p[((32*0)+30):(32*0)], data_in[0]};
|
||||
adc_data_p[((32*1)+31):(32*1)] <= {adc_data_p[((32*1)+30):(32*1)], data_in[1]};
|
||||
adc_data_p[((32*2)+31):(32*2)] <= {adc_data_p[((32*2)+30):(32*2)], data_in[2]};
|
||||
adc_data_p[((32*3)+31):(32*3)] <= {adc_data_p[((32*3)+30):(32*3)], data_in[3]};
|
||||
adc_data_p[((32*4)+31):(32*4)] <= {adc_data_p[((32*4)+30):(32*4)], data_in[4]};
|
||||
adc_data_p[((32*5)+31):(32*5)] <= {adc_data_p[((32*5)+30):(32*5)], data_in[5]};
|
||||
adc_data_p[((32*6)+31):(32*6)] <= {adc_data_p[((32*6)+30):(32*6)], data_in[6]};
|
||||
adc_data_p[((32*7)+31):(32*7)] <= {adc_data_p[((32*7)+30):(32*7)], data_in[7]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ready (single shot or continous)
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_ready <= adc_sshot ~^ adc_ready_in_s;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,66 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ip
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad7768
|
||||
|
||||
adi_ip_files axi_ad7768 [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
|
||||
"$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"axi_ad7768_if.v" \
|
||||
"axi_ad7768.v" ]
|
||||
|
||||
adi_ip_properties axi_ad7768
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad7768 "bd/bd.tcl"
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/docs/ad7768} $cc
|
||||
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects $cc]
|
||||
set_property driver_value 0 [ipx::get_ports *adc* -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
value_validation_type list \
|
||||
value_validation_list {4 8} \
|
||||
] [ipx::get_user_parameters NUM_CHANNELS -of_objects $cc]
|
||||
|
||||
set_property enablement_dependency { $NUM_CHANNELS == 8 } \
|
||||
[ipx::get_ports *_4 -of_objects $cc] \
|
||||
[ipx::get_ports *_5 -of_objects $cc] \
|
||||
[ipx::get_ports *_6 -of_objects $cc] \
|
||||
[ipx::get_ports *_7 -of_objects $cc]
|
||||
|
||||
|
||||
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 $cc
|
||||
ipx::infer_bus_interface clk_in xilinx.com:signal:clock_rtl:1.0 $cc
|
||||
set reset_intf [ipx::infer_bus_interface adc_reset xilinx.com:signal:reset_rtl:1.0 $cc ]
|
||||
set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
|
||||
set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files $cc
|
||||
|
||||
ipx::save_core $cc
|
||||
@@ -0,0 +1,41 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_CHANNELS" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
|
||||
# Procedure called to update NUM_CHANNELS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
|
||||
# Procedure called to validate NUM_CHANNELS
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_CHANNELS { MODELPARAM_VALUE.NUM_CHANNELS PARAM_VALUE.NUM_CHANNELS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_CHANNELS}] ${MODELPARAM_VALUE.NUM_CHANNELS}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user