josh/vivado_pub
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 2 Wiki Activity

initial commit, add dds_par module

Browse Source
This commit is contained in:
josh
2024-01-15 09:36:08 +08:00
commit 315a673005
1374 changed files with 465956 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
adi_library/axi_ad777x/Makefile
+35
View File
@@ -0,0 +1,35 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_ad777x
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad777x.v
GENERIC_DEPS += axi_ad777x_if.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad777x_ip.tcl
INTEL_DEPS += ../intel/common/ad_dcfilter.v
INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
INTEL_DEPS += axi_ad777x_hw.tcl
include ../scripts/library.mk
adi_library/axi_ad777x/axi_ad777x.v
+360
View File
@@ -0,0 +1,360 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns / 1ps
module axi_ad777x #(
parameter ID = 0
) (
input adc_dovf,
input clk_in,
input ready_in,
output sync_adc_mosi,
input sync_adc_miso,
input [ 3:0] data_in,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
output adc_enable_3,
output adc_enable_4,
output adc_enable_5,
output adc_enable_6,
output adc_enable_7,
output adc_valid_0,
output adc_valid_1,
output adc_valid_2,
output adc_valid_3,
output adc_valid_4,
output adc_valid_5,
output adc_valid_6,
output adc_valid_7,
output [31:0] adc_data_0,
output [31:0] adc_data_1,
output [31:0] adc_data_2,
output [31:0] adc_data_3,
output [31:0] adc_data_4,
output [31:0] adc_data_5,
output [31:0] adc_data_6,
output [31:0] adc_data_7,
output adc_clk,
output adc_reset,
output adc_valid,
output [ 7:0] adc_crc_ch_mismatch,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
// internal signals
wire adc_rst_s;
wire up_rstn;
wire up_clk;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire adc_clk_s;
wire up_wreq_s;
wire up_rreq_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:8];
wire [8:0] up_rack_s;
wire [8:0] up_wack_s;
wire [7:0] adc_enable;
wire [4:0] adc_num_lanes;
wire adc_crc_enable;
wire [7:0] adc_status_header[0:7];
wire [7:0] adc_crc_err;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk = adc_clk_s;
assign adc_reset = adc_rst_s;
assign adc_enable_0 = adc_enable[0];
assign adc_enable_1 = adc_enable[1];
assign adc_enable_2 = adc_enable[2];
assign adc_enable_3 = adc_enable[3];
assign adc_enable_4 = adc_enable[4];
assign adc_enable_5 = adc_enable[5];
assign adc_enable_6 = adc_enable[6];
assign adc_enable_7 = adc_enable[7];
assign adc_valid_0 = adc_valid;
assign adc_valid_1 = adc_valid;
assign adc_valid_2 = adc_valid;
assign adc_valid_3 = adc_valid;
assign adc_valid_4 = adc_valid;
assign adc_valid_5 = adc_valid;
assign adc_valid_6 = adc_valid;
assign adc_valid_7 = adc_valid;
assign adc_crc_ch_mismatch = adc_crc_err;
integer j;
always @(*) begin
up_rdata_r = 'h00;
up_rack_r = 'h00;
up_wack_r = 'h00;
for (j = 0; j <= 8; j=j+1) begin
up_rack_r = up_rack_r | up_rack_s[j];
up_wack_r = up_wack_r | up_wack_s[j];
up_rdata_r = up_rdata_r | up_rdata_s[j];
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_r;
up_rack <= up_rack_r;
up_wack <= up_wack_r;
end
end
// adc channels
generate
genvar i;
for (i = 0; i < 8; i=i+1) begin : ad777x_channels
up_adc_channel #(
.CHANNEL_ID(i)
) i_up_adc_channel (
.adc_clk (adc_clk_s),
.adc_rst (adc_rst_s),
.adc_enable (adc_enable[i]),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (1'b0),
.adc_pn_oos (1'b0),
.adc_or (1'b0),
.adc_read_data ('d0),
.adc_status_header(adc_status_header[i]),
.adc_crc_err(adc_crc_err[i]),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd32),
.adc_usr_datatype_bits (8'd32),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[i]),
.up_rack (up_rack_s[i]));
end
endgenerate
// adc interface
axi_ad777x_if i_ad777x_if (
.clk_in (clk_in),
.ready_in (ready_in),
.data_in (data_in),
.adc_clk (adc_clk_s),
.adc_valid (adc_valid),
.sync_adc_mosi(sync_adc_mosi),
.sync_adc_miso(sync_adc_miso),
.adc_crc_ch_mismatch(adc_crc_err),
.adc_num_lanes(adc_num_lanes),
.adc_crc_enable(adc_crc_enable),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_2 (adc_data_2),
.adc_data_3 (adc_data_3),
.adc_data_4 (adc_data_4),
.adc_data_5 (adc_data_5),
.adc_data_6 (adc_data_6),
.adc_data_7 (adc_data_7),
.adc_status_0(adc_status_header[0]),
.adc_status_1(adc_status_header[1]),
.adc_status_2(adc_status_header[2]),
.adc_status_3(adc_status_header[3]),
.adc_status_4(adc_status_header[4]),
.adc_status_5(adc_status_header[5]),
.adc_status_6(adc_status_header[6]),
.adc_status_7(adc_status_header[7]));
// adc up common
up_adc_common #(
.ID(ID)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk_s),
.adc_rst (adc_rst_s),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status ('h00),
.adc_sync_status (1'b1),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (),
.adc_ext_sync_arm(),
.adc_ext_sync_disarm(),
.adc_ext_sync_manual_req(),
.adc_custom_control(),
.adc_sdr_ddr_n(),
.adc_symb_op(),
.adc_symb_8_16b(),
.adc_num_lanes(adc_num_lanes),
.adc_crc_enable(adc_crc_enable),
.up_pps_rcounter (32'b0),
.up_pps_status (1'b0),
.up_pps_irq_mask (),
.up_adc_ce (),
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.up_adc_r1_mode(),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8),
.up_adc_gpio_in (32'b0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[8]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[8]),
.up_rack (up_rack_s[8]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
adi_library/axi_ad777x/axi_ad777x.xpr
+510
View File
@@ -0,0 +1,510 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad777x/axi_ad777x.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="8bfd791aa93e490599f044d131bc75bd"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../common/ad_rst.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad777x_if.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_adc_channel.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_adc_common.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_axi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_clock_mon.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_xfer_cntrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_xfer_status.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_ad777x.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../xilinx/common/ad_dcfilter.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/ad_datafmt.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_delay_cntrl.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<File Path="$PPRDIR/bd/bd.tcl">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_ad777x"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../xilinx/common/up_xfer_cntrl_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../xilinx/common/up_xfer_status_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/axi_ad777x/axi_ad777x_hw.tcl
+116
View File
@@ -0,0 +1,116 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
package require qsys
source ../../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_ad777x
set_module_property DESCRIPTION "AXI AD777x IP"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad777x
# source files
ad_ip_files axi_ad777x [list\
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
$ad_hdl_dir/library/intel/common/ad_dcfilter.v \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/ad_datafmt.v \
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
$ad_hdl_dir/library/common/up_xfer_status.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/common/up_delay_cntrl.v \
$ad_hdl_dir/library/common/up_adc_channel.v \
$ad_hdl_dir/library/common/up_adc_common.v \
axi_ad777x_if.v \
axi_ad777x.v ]
# IP parameters
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME "ID"
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16
# adc clock interface
add_interface adc_if conduit end
set_interface_property adc_if associatedClock clk_in
add_interface_port adc_if ready_in adc_ready Input 1
add_interface_port adc_if data_in adc_data_in Input 4
add_interface_port adc_if sync_adc_miso sync_adc_miso Input 1
add_interface_port adc_if sync_adc_mosi sync_adc_mosi Output 1
ad_interface signal clk_in input 1
ad_interface clock adc_clk output 1
ad_interface reset adc_reset output 1
set_interface_property if_adc_reset associatedClock if_adc_clk
ad_interface signal adc_crc_ch_mismatch output 8
ad_interface signal adc_dovf input 1 ovf
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_enable_0 enable Output 1
add_interface_port adc_ch_0 adc_data_0 data Output 32
add_interface_port adc_ch_0 adc_valid_0 valid Output 1
set_interface_property adc_ch_0 associatedClock if_adc_clk
set_interface_property adc_ch_0 associatedReset none
add_interface adc_ch_1 conduit end
add_interface_port adc_ch_1 adc_enable_1 enable Output 1
add_interface_port adc_ch_1 adc_data_1 data Output 32
add_interface_port adc_ch_1 adc_valid_1 valid Output 1
set_interface_property adc_ch_1 associatedClock if_adc_clk
set_interface_property adc_ch_1 associatedReset none
add_interface adc_ch_2 conduit end
add_interface_port adc_ch_2 adc_enable_2 enable Output 1
add_interface_port adc_ch_2 adc_data_2 data Output 32
add_interface_port adc_ch_2 adc_valid_2 valid Output 1
set_interface_property adc_ch_2 associatedClock if_adc_clk
set_interface_property adc_ch_2 associatedReset none
add_interface adc_ch_3 conduit end
add_interface_port adc_ch_3 adc_enable_3 enable Output 1
add_interface_port adc_ch_3 adc_data_3 data Output 32
add_interface_port adc_ch_3 adc_valid_3 valid Output 1
set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset none
add_interface adc_ch_4 conduit end
add_interface_port adc_ch_4 adc_enable_4 enable Output 1
add_interface_port adc_ch_4 adc_data_4 data Output 32
add_interface_port adc_ch_4 adc_valid_4 valid Output 1
set_interface_property adc_ch_4 associatedClock if_adc_clk
set_interface_property adc_ch_4 associatedReset none
add_interface adc_ch_5 conduit end
add_interface_port adc_ch_5 adc_enable_5 enable Output 1
add_interface_port adc_ch_5 adc_data_5 data Output 32
add_interface_port adc_ch_5 adc_valid_5 valid Output 1
set_interface_property adc_ch_5 associatedClock if_adc_clk
set_interface_property adc_ch_5 associatedReset none
add_interface adc_ch_6 conduit end
add_interface_port adc_ch_6 adc_enable_6 enable Output 1
add_interface_port adc_ch_6 adc_data_6 data Output 32
add_interface_port adc_ch_6 adc_valid_6 valid Output 1
set_interface_property adc_ch_6 associatedClock if_adc_clk
set_interface_property adc_ch_6 associatedReset none
add_interface adc_ch_7 conduit end
add_interface_port adc_ch_7 adc_enable_7 enable Output 1
add_interface_port adc_ch_7 adc_data_7 data Output 32
add_interface_port adc_ch_7 adc_valid_7 valid Output 1
set_interface_property adc_ch_7 associatedClock if_adc_clk
set_interface_property adc_ch_7 associatedReset none
adi_library/axi_ad777x/axi_ad777x_if.v
+378
View File
@@ -0,0 +1,378 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad777x_if (
// device-interface
input clk_in,
input ready_in,
output sync_adc_mosi,
input sync_adc_miso,
input [ 3:0] data_in,
input [ 4:0] adc_num_lanes,
input adc_crc_enable,
// data path interface
output adc_clk,
output adc_valid,
output [ 7:0] adc_crc_ch_mismatch,
output [31:0] adc_data_0,
output [31:0] adc_data_1,
output [31:0] adc_data_2,
output [31:0] adc_data_3,
output [31:0] adc_data_4,
output [31:0] adc_data_5,
output [31:0] adc_data_6,
output [31:0] adc_data_7,
output [ 7:0] adc_status_0,
output [ 7:0] adc_status_1,
output [ 7:0] adc_status_2,
output [ 7:0] adc_status_3,
output [ 7:0] adc_status_4,
output [ 7:0] adc_status_5,
output [ 7:0] adc_status_6,
output [ 7:0] adc_status_7
);
// internal registers
reg [ 8:0] adc_cnt_p = 'd0;
reg adc_valid_p = 'd0;
reg [255:0] adc_data_p = 'd0;
reg [31:0] adc_data_0_s = 'd0;
reg [31:0] adc_data_1_s = 'd0;
reg [31:0] adc_data_2_s = 'd0;
reg [31:0] adc_data_3_s = 'd0;
reg [31:0] adc_data_4_s = 'd0;
reg [31:0] adc_data_5_s = 'd0;
reg [31:0] adc_data_6_s = 'd0;
reg [31:0] adc_data_7_s = 'd0;
reg [31:0] adc_data_0_s_d = 'd0;
reg [31:0] adc_data_1_s_d = 'd0;
reg [31:0] adc_data_2_s_d = 'd0;
reg [31:0] adc_data_3_s_d = 'd0;
reg [31:0] adc_data_4_s_d = 'd0;
reg [31:0] adc_data_5_s_d = 'd0;
reg [31:0] adc_data_6_s_d = 'd0;
reg [31:0] adc_data_7_s_d = 'd0;
reg adc_valid_s = 'b0;
reg adc_valid_s_d = 'b0;
reg [ 7:0] adc_crc_read_data_0_1 = 'd0;
reg [ 7:0] adc_crc_read_data_2_3 = 'd0;
reg [ 7:0] adc_crc_read_data_4_5 = 'd0;
reg [ 7:0] adc_crc_read_data_6_7 = 'd0;
reg [55:0] adc_crc_data_0_1 = 'd0;
reg [55:0] adc_crc_data_2_3 = 'd0;
reg [55:0] adc_crc_data_4_5 = 'd0;
reg [55:0] adc_crc_data_6_7 = 'd0;
reg [ 7:0] adc_crc_reg_0_1 = 'd0;
reg [ 7:0] adc_crc_reg_2_3 = 'd0;
reg [ 7:0] adc_crc_reg_4_5 = 'd0;
reg [ 7:0] adc_crc_reg_6_7 = 'd0;
reg [ 7:0] adc_status_0_s = 'd0;
reg [ 7:0] adc_status_1_s = 'd0;
reg [ 7:0] adc_status_2_s = 'd0;
reg [ 7:0] adc_status_3_s = 'd0;
reg [ 7:0] adc_status_4_s = 'd0;
reg [ 7:0] adc_status_5_s = 'd0;
reg [ 7:0] adc_status_6_s = 'd0;
reg [ 7:0] adc_status_7_s = 'd0;
reg [ 7:0] adc_crc_ch_mismatch_s = 'd0;
// internal signals
wire adc_cnt_enable_s;
wire adc_ready_in_s;
wire [ 8:0] adc_cnt_value;
wire [ 7:0] adc_crc_in_s_0_1;
wire [ 7:0] adc_crc_in_s_2_3;
wire [ 7:0] adc_crc_in_s_4_5;
wire [ 7:0] adc_crc_in_s_6_7;
wire [ 7:0] adc_crc_s_0_1;
wire [ 7:0] adc_crc_s_2_3;
wire [ 7:0] adc_crc_s_4_5;
wire [ 7:0] adc_crc_s_6_7;
wire adc_crc_mismatch_s_0_1;
wire adc_crc_mismatch_s_2_3;
wire adc_crc_mismatch_s_4_5;
wire adc_crc_mismatch_s_6_7;
assign adc_valid = adc_valid_s_d;
assign adc_ready_in_s = ready_in;
assign adc_data_0 = adc_data_0_s_d;
assign adc_data_1 = adc_data_1_s_d;
assign adc_data_2 = adc_data_2_s_d;
assign adc_data_3 = adc_data_3_s_d;
assign adc_data_4 = adc_data_4_s_d;
assign adc_data_5 = adc_data_5_s_d;
assign adc_data_6 = adc_data_6_s_d;
assign adc_data_7 = adc_data_7_s_d;
assign sync_adc_mosi = sync_adc_miso;
assign adc_clk = clk_in;
assign adc_status_0 = adc_status_0_s;
assign adc_status_1 = adc_status_1_s;
assign adc_status_2 = adc_status_2_s;
assign adc_status_3 = adc_status_3_s;
assign adc_status_4 = adc_status_4_s;
assign adc_status_5 = adc_status_5_s;
assign adc_status_6 = adc_status_6_s;
assign adc_status_7 = adc_status_7_s;
assign adc_crc_ch_mismatch = adc_crc_ch_mismatch_s;
// function (crc)
function [ 7:0] crc8;
input [55:0] din;
input [ 7:0] cin;
reg [ 7:0] cout;
begin
cout[0] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 5] ^ cin[ 6] ^ din[ 0] ^ din[ 6] ^ din[ 7] ^ din[ 8] ^ din[12] ^ din[14] ^ din[16] ^
din[18] ^ din[19] ^ din[21] ^ din[23] ^ din[28] ^ din[30] ^ din[31] ^ din[34] ^ din[35] ^ din[39] ^ din[40] ^ din[43] ^ din[45] ^
din[48] ^ din[49] ^ din[50] ^ din[52] ^ din[53] ^ din[54];
cout[1] = cin[ 0] ^ cin[ 3] ^ cin[ 4] ^ cin[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23] ^ din[24] ^ din[28] ^ din[29] ^ din[30] ^ din[32] ^ din[34] ^ din[36] ^
din[39] ^ din[41] ^ din[43] ^ din[44] ^ din[45] ^ din[46] ^ din[48] ^ din[51] ^ din[52] ^ din[55];
cout[2] = cin[ 0] ^ cin[ 2] ^ cin[ 6] ^ din[ 0] ^ din[ 1] ^ din[ 2] ^ din[ 6] ^ din[ 8] ^ din[10] ^ din[12] ^ din[13] ^ din[15] ^ din[17] ^
din[22] ^ din[24] ^ din[25] ^ din[28] ^ din[29] ^ din[33] ^ din[34] ^ din[37] ^ din[39] ^ din[42] ^ din[43] ^ din[44] ^ din[46] ^
din[47] ^ din[48] ^ din[50] ^ din[54];
cout[3] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 9] ^ din[11] ^ din[13] ^ din[14] ^ din[16] ^
din[18] ^ din[23] ^ din[25] ^ din[26] ^ din[29] ^ din[30] ^ din[34] ^ din[35] ^ din[38] ^ din[40] ^ din[43] ^ din[44] ^ din[45] ^
din[47] ^ din[48] ^ din[49] ^ din[51] ^ din[55];
cout[4] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 4] ^ din[ 8] ^ din[10] ^ din[12] ^ din[14] ^ din[15] ^ din[17] ^
din[19] ^ din[24] ^ din[26] ^ din[27] ^ din[30] ^ din[31] ^ din[35] ^ din[36] ^ din[39] ^ din[41] ^ din[44] ^ din[45] ^ din[46] ^
din[48] ^ din[49] ^ din[50] ^ din[52];
cout[5] = cin[ 1] ^ cin[ 2] ^ cin[ 3] ^ cin[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 5] ^ din[ 9] ^ din[11] ^ din[13] ^ din[15] ^ din[16] ^ din[18] ^
din[20] ^ din[25] ^ din[27] ^ din[28] ^ din[31] ^ din[32] ^ din[36] ^ din[37] ^ din[40] ^ din[42] ^ din[45] ^ din[46] ^ din[47] ^
din[49] ^ din[50] ^ din[51] ^ din[53];
cout[6] = cin[ 0] ^ cin[ 2] ^ cin[ 3] ^ cin[ 4] ^ cin[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 6] ^ din[10] ^ din[12] ^ din[14] ^ din[16] ^ din[17] ^
din[19] ^ din[21] ^ din[26] ^ din[28] ^ din[29] ^ din[32] ^ din[33] ^ din[37] ^ din[38] ^ din[41] ^ din[43] ^ din[46] ^ din[47] ^
din[48] ^ din[50] ^ din[51] ^ din[52] ^ din[54];
cout[7] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 4] ^ cin[ 5] ^ cin[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 7] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^
din[18] ^ din[20] ^ din[22] ^ din[27] ^ din[29] ^ din[30] ^ din[33] ^ din[34] ^ din[38] ^ din[39] ^ din[42] ^ din[44] ^ din[47] ^
din[48] ^ din[49] ^ din[51] ^ din[52] ^ din[53] ^ din[55];
crc8 = cout;
end
endfunction
//crc computing
assign adc_crc_s_0_1 = crc8(adc_crc_data_0_1, adc_crc_in_s_0_1);
assign adc_crc_s_2_3 = crc8(adc_crc_data_2_3, adc_crc_in_s_2_3);
assign adc_crc_s_4_5 = crc8(adc_crc_data_4_5, adc_crc_in_s_4_5);
assign adc_crc_s_6_7 = crc8(adc_crc_data_6_7, adc_crc_in_s_6_7);
assign adc_crc_in_s_0_1 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_0_1;
assign adc_crc_in_s_2_3 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_2_3;
assign adc_crc_in_s_4_5 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_4_5;
assign adc_crc_in_s_6_7 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_6_7;
assign adc_crc_mismatch_s_0_1 = (adc_crc_read_data_0_1 == adc_crc_s_0_1) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s_2_3 = (adc_crc_read_data_2_3 == adc_crc_s_2_3) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s_4_5 = (adc_crc_read_data_4_5 == adc_crc_s_4_5) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s_6_7 = (adc_crc_read_data_6_7 == adc_crc_s_6_7) ? 1'b0 : adc_crc_enable;
always @(posedge adc_clk) begin
adc_status_0_s <= (adc_valid_s == 1'b1 ) ? adc_data_0_s[31:24]: adc_status_0_s;
adc_status_1_s <= (adc_valid_s == 1'b1 ) ? adc_data_1_s[31:24]: adc_status_1_s;
adc_status_2_s <= (adc_valid_s == 1'b1 ) ? adc_data_2_s[31:24]: adc_status_2_s;
adc_status_3_s <= (adc_valid_s == 1'b1 ) ? adc_data_3_s[31:24]: adc_status_3_s;
adc_status_4_s <= (adc_valid_s == 1'b1 ) ? adc_data_4_s[31:24]: adc_status_4_s;
adc_status_5_s <= (adc_valid_s == 1'b1 ) ? adc_data_5_s[31:24]: adc_status_5_s;
adc_status_6_s <= (adc_valid_s == 1'b1 ) ? adc_data_6_s[31:24]: adc_status_6_s;
adc_status_7_s <= (adc_valid_s == 1'b1 ) ? adc_data_7_s[31:24]: adc_status_7_s;
adc_crc_ch_mismatch_s[1:0] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_0_1}} : adc_crc_ch_mismatch_s[1:0];
adc_crc_ch_mismatch_s[3:2] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_2_3}} : adc_crc_ch_mismatch_s[3:2];
adc_crc_ch_mismatch_s[5:4] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_4_5}} : adc_crc_ch_mismatch_s[5:4];
adc_crc_ch_mismatch_s[7:6] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_6_7}} : adc_crc_ch_mismatch_s[7:6];
end
// crc generation/validation data
always @(posedge adc_clk) begin
if (adc_valid_s == 1'b1) begin
adc_crc_reg_0_1 <= adc_crc_s_0_1;
adc_crc_reg_2_3 <= adc_crc_s_2_3;
adc_crc_reg_4_5 <= adc_crc_s_4_5;
adc_crc_reg_6_7 <= adc_crc_s_6_7;
adc_crc_read_data_0_1 <= {adc_data_0_s[27:24],adc_data_1_s[27:24]};
adc_crc_read_data_2_3 <= {adc_data_2_s[27:24],adc_data_3_s[27:24]};
adc_crc_read_data_4_5 <= {adc_data_4_s[27:24],adc_data_5_s[27:24]};
adc_crc_read_data_6_7 <= {adc_data_6_s[27:24],adc_data_7_s[27:24]};
adc_crc_data_0_1 <= {adc_data_0_s[31:28],adc_data_0_s[23:0],adc_data_1_s[31:28],adc_data_1_s[23:0]};
adc_crc_data_2_3 <= {adc_data_2_s[31:28],adc_data_2_s[23:0],adc_data_3_s[31:28],adc_data_3_s[23:0]};
adc_crc_data_4_5 <= {adc_data_4_s[31:28],adc_data_4_s[23:0],adc_data_5_s[31:28],adc_data_5_s[23:0]};
adc_crc_data_6_7 <= {adc_data_6_s[31:28],adc_data_6_s[23:0],adc_data_7_s[31:28],adc_data_7_s[23:0]};
end else begin
adc_crc_reg_0_1 <= 'd0;
adc_crc_reg_2_3 <= 'd0;
adc_crc_reg_4_5 <= 'd0;
adc_crc_reg_6_7 <= 'd0;
adc_crc_read_data_0_1 <= 'd0;
adc_crc_read_data_2_3 <= 'd0;
adc_crc_read_data_4_5 <= 'd0;
adc_crc_read_data_6_7 <= 'd0;
adc_crc_data_0_1 <= 'd0;
adc_crc_data_2_3 <= 'd0;
adc_crc_data_4_5 <= 'd0;
adc_crc_data_6_7 <= 'd0;
end
end
//delay data 1 clk for data, data_valid and crc mismatch for alignment
always @(posedge adc_clk) begin
if (adc_valid_s == 1'b1) begin
adc_data_0_s_d <= adc_data_0_s;
adc_data_1_s_d <= adc_data_1_s;
adc_data_2_s_d <= adc_data_2_s;
adc_data_3_s_d <= adc_data_3_s;
adc_data_4_s_d <= adc_data_4_s;
adc_data_5_s_d <= adc_data_5_s;
adc_data_6_s_d <= adc_data_6_s;
adc_data_7_s_d <= adc_data_7_s;
adc_valid_s_d <= adc_valid_s;
end else begin
adc_data_0_s_d <= 32'b0;
adc_data_1_s_d <= 32'b0;
adc_data_2_s_d <= 32'b0;
adc_data_3_s_d <= 32'b0;
adc_data_4_s_d <= 32'b0;
adc_data_5_s_d <= 32'b0;
adc_data_6_s_d <= 32'b0;
adc_data_7_s_d <= 32'b0;
adc_valid_s_d <= 1'b0;
end
end
always @(posedge adc_clk) begin
if (adc_valid_p == 1'b1) begin
if( adc_num_lanes == 'h1) begin
adc_data_0_s <= adc_data_p[((32*7)+31):(32*7)];
adc_data_1_s <= adc_data_p[((32*6)+31):(32*6)];
adc_data_2_s <= adc_data_p[((32*5)+31):(32*5)];
adc_data_3_s <= adc_data_p[((32*4)+31):(32*4)];
adc_data_4_s <= adc_data_p[((32*3)+31):(32*3)];
adc_data_5_s <= adc_data_p[((32*2)+31):(32*2)];
adc_data_6_s <= adc_data_p[((32*1)+31):(32*1)];
adc_data_7_s <= adc_data_p[((32*0)+31):(32*0)];
end else if( adc_num_lanes == 'h2) begin
adc_data_0_s <= adc_data_p[((32*3)+31):(32*3)];
adc_data_1_s <= adc_data_p[((32*2)+31):(32*2)];
adc_data_2_s <= adc_data_p[((32*1)+31):(32*1)];
adc_data_3_s <= adc_data_p[((32*0)+31):(32*0)];
adc_data_4_s <= adc_data_p[((32*7)+31):(32*7)];
adc_data_5_s <= adc_data_p[((32*6)+31):(32*6)];
adc_data_6_s <= adc_data_p[((32*5)+31):(32*5)];
adc_data_7_s <= adc_data_p[((32*4)+31):(32*4)];
end else begin
adc_data_0_s <= adc_data_p[((32*1)+31):(32*1)];
adc_data_1_s <= adc_data_p[((32*0)+31):(32*0)];
adc_data_2_s <= adc_data_p[((32*3)+31):(32*3)];
adc_data_3_s <= adc_data_p[((32*2)+31):(32*2)];
adc_data_4_s <= adc_data_p[((32*5)+31):(32*5)];
adc_data_5_s <= adc_data_p[((32*4)+31):(32*4)];
adc_data_6_s <= adc_data_p[((32*7)+31):(32*7)];
adc_data_7_s <= adc_data_p[((32*6)+31):(32*6)];
end
adc_valid_s <= adc_valid_p;
end else begin
adc_data_0_s <= 32'b0;
adc_data_1_s <= 32'b0;
adc_data_2_s <= 32'b0;
adc_data_3_s <= 32'b0;
adc_data_4_s <= 32'b0;
adc_data_5_s <= 32'b0;
adc_data_6_s <= 32'b0;
adc_data_7_s <= 32'b0;
adc_valid_s <= 1'b0;
end
end
assign adc_cnt_value = (adc_num_lanes == 'h1) ? 'hff :
((adc_num_lanes == 'h2)? 'h7f : 'h3f);
assign adc_cnt_enable_s = (adc_cnt_p < adc_cnt_value) ? 1'b1 : 1'b0;
always @(negedge adc_clk) begin
if (adc_ready_in_s == 1'b1) begin
adc_cnt_p <= 'h000;
end else if (adc_cnt_enable_s == 1'b1) begin
adc_cnt_p <= adc_cnt_p + 1'b1;
end
if (adc_cnt_p == adc_cnt_value) begin
adc_valid_p <= 1'b1;
end else begin
adc_valid_p <= 1'b0;
end
end
// data (individual lanes)
always @(negedge adc_clk) begin
if( adc_num_lanes == 'h1) begin
if (adc_cnt_p == 'h000 ) begin
adc_data_p[((256*0)+255):(256*0)] <= {255'd0, data_in[0]};
end else begin
adc_data_p[((256*0)+255):(255*0)] <= {adc_data_p[((256*0)+254):(256*0)], data_in[0]};
end
end else if( adc_num_lanes == 'h2) begin
if (adc_cnt_p == 'h000 ) begin
adc_data_p[((128*0)+127):(128*0)] <= {127'd0, data_in[0]};
adc_data_p[((128*1)+127):(128*1)] <= {127'd0, data_in[1]};
end else begin
adc_data_p[((128*0)+127):(128*0)] <= {adc_data_p[((128*0)+126):(128*0)], data_in[0]};
adc_data_p[((128*1)+127):(128*1)] <= {adc_data_p[((128*1)+126):(128*1)], data_in[1]};
end
end else begin
if (adc_cnt_p == 'h000 ) begin
adc_data_p[((64*0)+63):(64*0)] <= {63'd0, data_in[0]};
adc_data_p[((64*1)+63):(64*1)] <= {63'd0, data_in[1]};
adc_data_p[((64*2)+63):(64*2)] <= {63'd0, data_in[2]};
adc_data_p[((64*3)+63):(64*3)] <= {63'd0, data_in[3]};
end else begin
adc_data_p[((64*0)+63):(64*0)] <= {adc_data_p[((64*0)+62):(64*0)], data_in[0]};
adc_data_p[((64*1)+63):(64*1)] <= {adc_data_p[((64*1)+62):(64*1)], data_in[1]};
adc_data_p[((64*2)+63):(64*2)] <= {adc_data_p[((64*2)+62):(64*2)], data_in[2]};
adc_data_p[((64*3)+63):(64*3)] <= {adc_data_p[((64*3)+62):(64*3)], data_in[3]};
end
end
end
endmodule
adi_library/axi_ad777x/axi_ad777x_ip.tcl
+49
View File
@@ -0,0 +1,49 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_ad777x
adi_ip_files axi_ad777x [list \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"axi_ad777x_if.v" \
"axi_ad777x.v" ]
adi_ip_properties axi_ad777x
adi_init_bd_tcl
adi_ip_bd axi_ad777x "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/ad777x} [ipx::current_core]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface clk_in xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
set reset_intf [ipx::infer_bus_interface adc_reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
set_property value "ACTIVE_HIGH" $reset_polarity
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/axi_ad777x/bd/bd.tcl
+41
View File
@@ -0,0 +1,41 @@
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
adi_library/axi_ad777x/component.xml
+1364
View File
File diff suppressed because it is too large Load Diff
adi_library/axi_ad777x/temporary_case_dependencies.mk
+2
View File
@@ -0,0 +1,2 @@
CLEAN_TARGET += bd
CLEAN_TARGET += temporary_case_dependencies.mk
adi_library/axi_ad777x/xgui/axi_ad777x_v1_0.tcl
+25
View File
@@ -0,0 +1,25 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}