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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_alt_lvds_rx (
// physical interface (receive)
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
// data interface
output clk,
output [ 3:0] rx_frame,
output [ 5:0] rx_data_0,
output [ 5:0] rx_data_1,
output [ 5:0] rx_data_2,
output [ 5:0] rx_data_3,
output rx_locked
);
// internal signals
wire [27:0] rx_data_s;
// instantiations
assign rx_frame[3] = rx_data_s[24];
assign rx_frame[2] = rx_data_s[25];
assign rx_frame[1] = rx_data_s[26];
assign rx_frame[0] = rx_data_s[27];
assign rx_data_3[5] = rx_data_s[20];
assign rx_data_3[4] = rx_data_s[16];
assign rx_data_3[3] = rx_data_s[12];
assign rx_data_3[2] = rx_data_s[ 8];
assign rx_data_3[1] = rx_data_s[ 4];
assign rx_data_3[0] = rx_data_s[ 0];
assign rx_data_2[5] = rx_data_s[21];
assign rx_data_2[4] = rx_data_s[17];
assign rx_data_2[3] = rx_data_s[13];
assign rx_data_2[2] = rx_data_s[ 9];
assign rx_data_2[1] = rx_data_s[ 5];
assign rx_data_2[0] = rx_data_s[ 1];
assign rx_data_1[5] = rx_data_s[22];
assign rx_data_1[4] = rx_data_s[18];
assign rx_data_1[3] = rx_data_s[14];
assign rx_data_1[2] = rx_data_s[10];
assign rx_data_1[1] = rx_data_s[ 6];
assign rx_data_1[0] = rx_data_s[ 2];
assign rx_data_0[5] = rx_data_s[23];
assign rx_data_0[4] = rx_data_s[19];
assign rx_data_0[3] = rx_data_s[15];
assign rx_data_0[2] = rx_data_s[11];
assign rx_data_0[1] = rx_data_s[ 7];
assign rx_data_0[0] = rx_data_s[ 3];
altlvds_rx #(
.buffer_implementation ("RAM"),
.cds_mode ("UNUSED"),
.common_rx_tx_pll ("ON"),
.data_align_rollover (4),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.dpa_initial_phase_value (0),
.dpll_lock_count (0),
.dpll_lock_window (0),
.enable_clock_pin_mode ("UNUSED"),
.enable_dpa_align_to_rising_edge_only ("OFF"),
.enable_dpa_calibration ("ON"),
.enable_dpa_fifo ("UNUSED"),
.enable_dpa_initial_phase_selection ("OFF"),
.enable_dpa_mode ("OFF"),
.enable_dpa_pll_calibration ("OFF"),
.enable_soft_cdr_mode ("OFF"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.input_data_rate (500),
.intended_device_family ("Cyclone V"),
.lose_lock_on_one_change ("UNUSED"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_rx"),
.lpm_type ("altlvds_rx"),
.number_of_channels (7),
.outclock_resource ("Regional clock"),
.pll_operation_mode ("NORMAL"),
.pll_self_reset_on_loss_lock ("UNUSED"),
.port_rx_channel_data_align ("PORT_UNUSED"),
.port_rx_data_align ("PORT_UNUSED"),
.refclk_frequency ("250.000000 MHz"),
.registered_data_align_input ("UNUSED"),
.registered_output ("ON"),
.reset_fifo_at_first_lock ("UNUSED"),
.rx_align_data_reg ("RISING_EDGE"),
.sim_dpa_is_negative_ppm_drift ("OFF"),
.sim_dpa_net_ppm_variation (0),
.sim_dpa_output_clock_phase_shift (0),
.use_coreclock_input ("OFF"),
.use_dpll_rawperror ("OFF"),
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.x_on_bitslip ("ON"),
.clk_src_is_pll ("off")
) i_altlvds_rx (
.rx_inclock (rx_clk_in_p),
.rx_in ({rx_frame_in_p, rx_data_in_p}),
.rx_outclock (clk),
.rx_out (rx_data_s),
.rx_locked (rx_locked),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_areset (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset ({7{1'b0}}),
.rx_channel_data_align ({7{1'b0}}),
.rx_coreclk ({7{1'b1}}),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_divfwdclk (),
.rx_dpa_lock_reset ({7{1'b0}}),
.rx_dpa_locked (),
.rx_dpaclock (1'b0),
.rx_dpll_enable ({7{1'b1}}),
.rx_dpll_hold ({7{1'b0}}),
.rx_dpll_reset ({7{1'b0}}),
.rx_enable (1'b1),
.rx_fifo_reset ({7{1'b0}}),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_reset ({7{1'b0}}),
.rx_syncclock (1'b0));
endmodule
adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_alt_lvds_tx (
// physical interface (transmit)
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
// data interface
input tx_clk,
input clk,
input [ 3:0] tx_frame,
input [ 5:0] tx_data_0,
input [ 5:0] tx_data_1,
input [ 5:0] tx_data_2,
input [ 5:0] tx_data_3,
output tx_locked
);
// internal registers
reg [27:0] tx_data_n = 'd0;
reg [27:0] tx_data_p = 'd0;
// internal signals
wire core_clk;
wire [27:0] tx_data_s;
// instantiations
assign tx_clk_out_n = 1'd0;
assign tx_frame_out_n = 1'd0;
assign tx_data_out_n = 6'd0;
assign tx_data_s[24] = tx_frame[3];
assign tx_data_s[25] = tx_frame[2];
assign tx_data_s[26] = tx_frame[1];
assign tx_data_s[27] = tx_frame[0];
assign tx_data_s[20] = tx_data_3[5];
assign tx_data_s[16] = tx_data_3[4];
assign tx_data_s[12] = tx_data_3[3];
assign tx_data_s[ 8] = tx_data_3[2];
assign tx_data_s[ 4] = tx_data_3[1];
assign tx_data_s[ 0] = tx_data_3[0];
assign tx_data_s[21] = tx_data_2[5];
assign tx_data_s[17] = tx_data_2[4];
assign tx_data_s[13] = tx_data_2[3];
assign tx_data_s[ 9] = tx_data_2[2];
assign tx_data_s[ 5] = tx_data_2[1];
assign tx_data_s[ 1] = tx_data_2[0];
assign tx_data_s[22] = tx_data_1[5];
assign tx_data_s[18] = tx_data_1[4];
assign tx_data_s[14] = tx_data_1[3];
assign tx_data_s[10] = tx_data_1[2];
assign tx_data_s[ 6] = tx_data_1[1];
assign tx_data_s[ 2] = tx_data_1[0];
assign tx_data_s[23] = tx_data_0[5];
assign tx_data_s[19] = tx_data_0[4];
assign tx_data_s[15] = tx_data_0[3];
assign tx_data_s[11] = tx_data_0[2];
assign tx_data_s[ 7] = tx_data_0[1];
assign tx_data_s[ 3] = tx_data_0[0];
always @(negedge clk) begin
tx_data_n <= tx_data_s;
end
always @(posedge core_clk) begin
tx_data_p <= tx_data_n;
end
altlvds_tx #(
.center_align_msb ("UNUSED"),
.common_rx_tx_pll ("ON"),
.coreclock_divide_by (1),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.differential_drive (0),
.enable_clock_pin_mode ("UNUSED"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.intended_device_family ("Cyclone V"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_tx"),
.lpm_type ("altlvds_tx"),
.multi_clock ("OFF"),
.number_of_channels (7),
.outclock_alignment ("EDGE_ALIGNED"),
.outclock_divide_by (2),
.outclock_duty_cycle (50),
.outclock_multiply_by (1),
.outclock_phase_shift (0),
.outclock_resource ("Regional clock"),
.output_data_rate (500),
.pll_compensation_mode ("AUTO"),
.pll_self_reset_on_loss_lock ("OFF"),
.preemphasis_setting (0),
.refclk_frequency ("250.000000 MHz"),
.registered_input ("TX_CORECLK"),
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.vod_setting (0),
.clk_src_is_pll ("off")
) i_altlvds_tx (
.tx_inclock (tx_clk),
.tx_coreclock (core_clk),
.tx_in (tx_data_p),
.tx_outclock (tx_clk_out_p),
.tx_out ({tx_frame_out_p, tx_data_out_p}),
.tx_locked (tx_locked),
.pll_areset (1'b0),
.sync_inclock (1'b0),
.tx_data_reset (1'b0),
.tx_enable (1'b1),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
endmodule
adi_library/axi_ad9361/intel/axi_ad9361_cmos_if.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_cmos_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter CLK_DESKEW = 0,
parameter USE_SSI_CLK = 1,
// Dummy parameters, required keep the code consistency(used on Xilinx)
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter IODELAY_CTRL = 1,
parameter DELAY_REFCLK_FREQUENCY = 0
) (
// physical interface (receive)
input rx_clk_in,
input rx_frame_in,
input [11:0] rx_data_in,
// physical interface (transmit)
output tx_clk_out,
output tx_frame_out,
output [11:0] tx_data_out,
// ensm control
output enable,
output txnrx,
// clock (common to both receive and transmit)
input rst,
input clk,
output l_clk,
// receive data path interface
output adc_valid,
output [47:0] adc_data,
output adc_status,
input adc_r1_mode,
input adc_ddr_edgesel,
// transmit data path interface
input dac_valid,
input [47:0] dac_data,
input dac_clksel,
input dac_r1_mode,
// tdd interface
input tdd_enable,
input tdd_txnrx,
input tdd_mode,
// delay interface
input mmcm_rst,
input up_clk,
input up_rstn,
input up_enable,
input up_txnrx,
input [12:0] up_adc_dld,
input [64:0] up_adc_dwdata,
output [64:0] up_adc_drdata,
input [15:0] up_dac_dld,
input [79:0] up_dac_dwdata,
output [79:0] up_dac_drdata,
input delay_clk,
input delay_rst,
output delay_locked,
// drp interface
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked
);
// cmos is not supported on intel platforms yet.
assign tx_clk_out = 1'd0;
assign tx_frame_out = 1'd0;
assign tx_data_out = 12'd0;
assign enable = 1'd0;
assign txnrx = 1'd0;
assign l_clk = 1'd0;
assign adc_valid = 1'd0;
assign adc_data = 48'd0;
assign adc_status = 1'd0;
assign up_adc_drdata = 65'd0;
assign up_dac_drdata = 80'd0;
assign delay_locked = 1'd0;
assign up_drp_rdata = 32'd0;
assign up_drp_ready = 1'd0;
assign up_drp_locked = 1'd0;
endmodule
adi_library/axi_ad9361/intel/axi_ad9361_lvds_if.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_lvds_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter CLK_DESKEW = 0,
// Dummy parameters, required keep the code consistency(used on Xilinx)
parameter USE_SSI_CLK = 1,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter IODELAY_CTRL = 1,
parameter DELAY_REFCLK_FREQUENCY = 0,
parameter RX_NODPA = 0
) (
// physical interface (receive)
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
// physical interface (transmit)
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
// ensm control
output enable,
output txnrx,
// clock (common to both receive and transmit)
input rst,
input clk,
output l_clk,
// receive data path interface
output adc_valid,
output [47:0] adc_data,
output adc_status,
input adc_r1_mode,
input adc_ddr_edgesel,
// transmit data path interface
input dac_valid,
input [47:0] dac_data,
input dac_clksel,
input dac_r1_mode,
// tdd interface
input tdd_enable,
input tdd_txnrx,
input tdd_mode,
// delay interface
input mmcm_rst,
input up_clk,
input up_rstn,
input up_enable,
input up_txnrx,
input [ 6:0] up_adc_dld,
input [34:0] up_adc_dwdata,
output [34:0] up_adc_drdata,
input [ 9:0] up_dac_dld,
input [49:0] up_dac_dwdata,
output [49:0] up_dac_drdata,
input delay_clk,
input delay_rst,
output delay_locked,
// drp interface
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked
);
// internal registers
reg up_drp_locked_m1 = 1'd0;
reg up_drp_locked_int = 1'd0;
reg rx_r1_mode = 'd0;
reg [ 3:0] rx_frame_d = 'd0;
reg [ 5:0] rx_data_3 = 'd0;
reg [ 5:0] rx_data_2 = 'd0;
reg [ 5:0] rx_data_1 = 'd0;
reg adc_valid_p = 'd0;
reg [47:0] adc_data_p = 'd0;
reg adc_status_p = 'd0;
reg adc_valid_int = 'd0;
reg [47:0] adc_data_int = 'd0;
reg adc_status_int = 'd0;
reg tx_valid = 'd0;
reg [47:0] tx_data = 'd0;
reg [ 3:0] tx_frame_p = 'd0;
reg [ 5:0] tx_data_0_p = 'd0;
reg [ 5:0] tx_data_1_p = 'd0;
reg [ 5:0] tx_data_2_p = 'd0;
reg [ 5:0] tx_data_3_p = 'd0;
reg [ 3:0] tx_frame = 'd0;
reg [ 5:0] tx_data_0 = 'd0;
reg [ 5:0] tx_data_1 = 'd0;
reg [ 5:0] tx_data_2 = 'd0;
reg [ 5:0] tx_data_3 = 'd0;
reg up_enable_int = 'd0;
reg up_txnrx_int = 'd0;
reg enable_up_m1 = 'd0;
reg txnrx_up_m1 = 'd0;
reg enable_up = 'd0;
reg txnrx_up = 'd0;
reg enable_int = 'd0;
reg txnrx_int = 'd0;
reg enable_int_p = 'd0;
reg txnrx_int_p = 'd0;
// internal signals
wire locked_s;
wire [ 3:0] rx_frame_s;
wire [ 5:0] rx_data_3_s;
wire [ 5:0] rx_data_2_s;
wire [ 5:0] rx_data_1_s;
wire [ 5:0] rx_data_0_s;
// local parameters
localparam CYCLONE5 = 101;
localparam ARRIA10 = 103;
// unused interface signals
assign up_adc_drdata = 35'b0;
assign up_dac_drdata = 50'b0;
assign delay_locked = 1'b1;
// drp locked must be on up-clock
assign up_drp_locked = up_drp_locked_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_locked_m1 <= 1'd0;
up_drp_locked_int <= 1'd0;
end else begin
up_drp_locked_m1 <= locked_s;
up_drp_locked_int <= up_drp_locked_m1;
end
end
// r1mode
generate if (CLK_DESKEW) begin
reg adc_r1_mode_n = 'd0;
always @(negedge clk) begin
adc_r1_mode_n <= adc_r1_mode;
end
always @(posedge l_clk) begin
rx_r1_mode <= adc_r1_mode_n;
end
end else begin /* CLK_DESKEW == 0 */
always @(posedge l_clk) begin
rx_r1_mode <= adc_r1_mode;
end
end
endgenerate
// frame check
always @(posedge l_clk) begin
if (rx_r1_mode == 1'd1) begin
rx_frame_d <= rx_frame_s;
end else begin
rx_frame_d <= ~rx_frame_s;
end
end
// data hold
always @(posedge l_clk) begin
rx_data_3 <= rx_data_3_s;
rx_data_2 <= rx_data_2_s;
rx_data_1 <= rx_data_1_s;
end
// delineation
always @(posedge l_clk) begin
case ({rx_r1_mode, rx_frame_s})
5'b01111: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_1_s, rx_data_3_s};
adc_data_p[11: 0] <= {rx_data_0_s, rx_data_2_s};
end
5'b00000: begin
adc_valid_p <= 1'b1;
adc_data_p[47:36] <= {rx_data_1_s, rx_data_3_s};
adc_data_p[35:24] <= {rx_data_0_s, rx_data_2_s};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
5'b00111: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_0_s, rx_data_2_s};
adc_data_p[11: 0] <= {rx_data_3, rx_data_1_s};
end
5'b01000: begin
adc_valid_p <= 1'b1;
adc_data_p[47:36] <= {rx_data_0_s, rx_data_2_s};
adc_data_p[35:24] <= {rx_data_3, rx_data_1_s};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
5'b00011: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_3, rx_data_1_s};
adc_data_p[11: 0] <= {rx_data_2, rx_data_0_s};
end
5'b01100: begin
adc_valid_p <= 1'b1;
adc_data_p[47:36] <= {rx_data_3, rx_data_1_s};
adc_data_p[35:24] <= {rx_data_2, rx_data_0_s};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
5'b00001: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_2, rx_data_0_s};
adc_data_p[11: 0] <= {rx_data_1, rx_data_3};
end
5'b01110: begin
adc_valid_p <= 1'b1;
adc_data_p[47:36] <= {rx_data_2, rx_data_0_s};
adc_data_p[35:24] <= {rx_data_1, rx_data_3};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
5'b10011: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_1_s, rx_data_3_s};
adc_data_p[11: 0] <= {rx_data_0_s, rx_data_2_s};
end
5'b11001: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_0_s, rx_data_2_s};
adc_data_p[11: 0] <= {rx_data_3, rx_data_1_s};
end
5'b11100: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_3, rx_data_1_s};
adc_data_p[11: 0] <= {rx_data_2, rx_data_0_s};
end
5'b10110: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_2, rx_data_0_s};
adc_data_p[11: 0] <= {rx_data_1, rx_data_3};
end
default: begin
adc_valid_p <= 1'b0;
adc_data_p <= 48'd0;
end
endcase
end
// adc-status
always @(posedge l_clk) begin
if (rx_frame_d == rx_frame_s) begin
adc_status_p <= locked_s;
end else begin
adc_status_p <= 1'b0;
end
end
// transfer to common clock
generate if (CLK_DESKEW) begin
reg adc_valid_n = 'd0;
reg [47:0] adc_data_n = 'd0;
reg adc_status_n = 'd0;
always @(negedge l_clk) begin
adc_valid_n <= adc_valid_p;
adc_data_n <= adc_data_p;
adc_status_n <= adc_status_p;
end
always @(posedge clk) begin
adc_valid_int <= adc_valid_n;
adc_data_int <= adc_data_n;
adc_status_int <= adc_status_n;
end
end else begin /* CLK_DESKEW == 0 */
always @(posedge l_clk) begin
adc_valid_int <= adc_valid_p;
adc_data_int <= adc_data_p;
adc_status_int <= adc_status_p;
end
end
endgenerate
assign adc_valid = adc_valid_int;
assign adc_data = adc_data_int;
assign adc_status = adc_status_int;
// dac-tx interface
always @(posedge clk) begin
tx_valid <= dac_valid;
if (dac_valid == 1'b1) begin
tx_data <= dac_data;
end
end
always @(posedge clk) begin
if (dac_r1_mode == 1'b1) begin
tx_frame_p <= 4'b0011;
tx_data_0_p <= tx_data[11: 6];
tx_data_1_p <= tx_data[23:18];
tx_data_2_p <= tx_data[ 5: 0];
tx_data_3_p <= tx_data[17:12];
end else if (tx_valid == 1'b1) begin
tx_frame_p <= 4'b1111;
tx_data_0_p <= tx_data[11: 6];
tx_data_1_p <= tx_data[23:18];
tx_data_2_p <= tx_data[ 5: 0];
tx_data_3_p <= tx_data[17:12];
end else begin
tx_frame_p <= 4'b0000;
tx_data_0_p <= tx_data[35:30];
tx_data_1_p <= tx_data[47:42];
tx_data_2_p <= tx_data[29:24];
tx_data_3_p <= tx_data[41:36];
end
end
// transfer to local clock
generate if (CLK_DESKEW) begin
reg tx_frame_n = 'd0;
reg [ 5:0] tx_data_0_n = 'd0;
reg [ 5:0] tx_data_1_n = 'd0;
reg [ 5:0] tx_data_2_n = 'd0;
reg [ 5:0] tx_data_3_n = 'd0;
always @(negedge clk) begin
tx_frame_n <= tx_frame_p;
tx_data_0_n <= tx_data_0_p;
tx_data_1_n <= tx_data_1_p;
tx_data_2_n <= tx_data_2_p;
tx_data_3_n <= tx_data_3_p;
end
always @(posedge l_clk) begin
tx_frame <= tx_frame_n;
tx_data_0 <= tx_data_0_n;
tx_data_1 <= tx_data_1_n;
tx_data_2 <= tx_data_2_n;
tx_data_3 <= tx_data_3_n;
end
end else begin /* CLK_DESKEW == 0 */
always @(posedge l_clk) begin
tx_frame <= tx_frame_p;
tx_data_0 <= tx_data_0_p;
tx_data_1 <= tx_data_1_p;
tx_data_2 <= tx_data_2_p;
tx_data_3 <= tx_data_3_p;
end
end
endgenerate
// tdd/ensm control
always @(posedge up_clk) begin
up_enable_int <= up_enable;
up_txnrx_int <= up_txnrx;
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
enable_up_m1 <= 1'b0;
txnrx_up_m1 <= 1'b0;
enable_up <= 1'b0;
txnrx_up <= 1'b0;
end else begin
enable_up_m1 <= up_enable_int;
txnrx_up_m1 <= up_txnrx_int;
enable_up <= enable_up_m1;
txnrx_up <= txnrx_up_m1;
end
end
always @(posedge clk) begin
if (tdd_mode == 1'b1) begin
enable_int <= tdd_enable;
txnrx_int <= tdd_txnrx;
end else begin
enable_int <= enable_up;
txnrx_int <= txnrx_up;
end
end
generate if (CLK_DESKEW) begin
reg enable_int_n = 'd0;
reg txnrx_int_n = 'd0;
always @(negedge clk) begin
enable_int_n <= enable_int;
txnrx_int_n <= txnrx_int;
end
always @(posedge l_clk) begin
enable_int_p <= enable_int_n;
txnrx_int_p <= txnrx_int_n;
end
end else begin /* CLK_DESKEW == 0 */
always @(posedge l_clk) begin
enable_int_p <= enable_int;
txnrx_int_p <= txnrx_int;
end
end
endgenerate
generate
if (FPGA_TECHNOLOGY == CYCLONE5) begin
axi_ad9361_lvds_if_c5 i_axi_ad9361_lvds_if_c5 (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
.rx_frame_in_p (rx_frame_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_data_in_n (rx_data_in_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_clk_out_n (tx_clk_out_n),
.tx_frame_out_p (tx_frame_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_data_out_n (tx_data_out_n),
.enable (enable),
.txnrx (txnrx),
.clk (l_clk),
.rx_frame (rx_frame_s),
.rx_data_0 (rx_data_0_s),
.rx_data_1 (rx_data_1_s),
.rx_data_2 (rx_data_2_s),
.rx_data_3 (rx_data_3_s),
.tx_frame (tx_frame),
.tx_data_0 (tx_data_0),
.tx_data_1 (tx_data_1),
.tx_data_2 (tx_data_2),
.tx_data_3 (tx_data_3),
.tx_enable (enable_int_p),
.tx_txnrx (txnrx_int_p),
.locked (locked_s),
.up_clk (up_clk),
.up_rstn (up_rstn));
end
endgenerate
generate
if (FPGA_TECHNOLOGY == ARRIA10) begin
axi_ad9361_lvds_if_10 #(
.RX_NODPA (RX_NODPA)
) i_axi_ad9361_lvds_if_10 (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
.rx_frame_in_p (rx_frame_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_data_in_n (rx_data_in_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_clk_out_n (tx_clk_out_n),
.tx_frame_out_p (tx_frame_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_data_out_n (tx_data_out_n),
.enable (enable),
.txnrx (txnrx),
.clk (l_clk),
.rx_frame (rx_frame_s),
.rx_data_0 (rx_data_0_s),
.rx_data_1 (rx_data_1_s),
.rx_data_2 (rx_data_2_s),
.rx_data_3 (rx_data_3_s),
.tx_frame (tx_frame),
.tx_data_0 (tx_data_0),
.tx_data_1 (tx_data_1),
.tx_data_2 (tx_data_2),
.tx_data_3 (tx_data_3),
.tx_enable (enable_int_p),
.tx_txnrx (txnrx_int_p),
.locked (locked_s),
.up_clk (up_clk),
.up_rstn (up_rstn));
end
endgenerate
endmodule
adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
+306
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@@ -0,0 +1,306 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_lvds_if_10 #(
parameter RX_NODPA = 0
) (
// physical interface (receive)
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
// physical interface (transmit)
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
// ensm control
output enable,
output txnrx,
// clock (common to both receive and transmit)
output clk,
// receive data path interface
output [ 3:0] rx_frame,
output [ 5:0] rx_data_0,
output [ 5:0] rx_data_1,
output [ 5:0] rx_data_2,
output [ 5:0] rx_data_3,
// transmit data path interface
input [ 3:0] tx_frame,
input [ 5:0] tx_data_0,
input [ 5:0] tx_data_1,
input [ 5:0] tx_data_2,
input [ 5:0] tx_data_3,
input tx_enable,
input tx_txnrx,
// locked (status)
output locked,
// delay interface
input up_clk,
input up_rstn
);
// internal registers
reg pll_rst = 1'd1;
reg locked_int = 'd0;
// internal signals
wire [27:0] rx_data_s;
wire [ 6:0] rx_data_locked_s;
wire [ 6:0] rx_delay_locked_s;
wire [27:0] tx_data_s;
wire locked_s;
wire lvds_clk;
wire lvds_loaden;
wire [ 7:0] lvds_phase;
wire rx_clk;
// pll reset
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
pll_rst <= 1'b1;
end else begin
pll_rst <= 1'b0;
end
end
assign locked = locked_int;
always @(posedge clk) begin
locked_int <= locked_s & (& rx_data_locked_s) &
(& rx_delay_locked_s);
end
// receive
assign rx_frame[3] = rx_data_s[24];
assign rx_frame[2] = rx_data_s[25];
assign rx_frame[1] = rx_data_s[26];
assign rx_frame[0] = rx_data_s[27];
assign rx_data_3[5] = rx_data_s[20];
assign rx_data_3[4] = rx_data_s[16];
assign rx_data_3[3] = rx_data_s[12];
assign rx_data_3[2] = rx_data_s[ 8];
assign rx_data_3[1] = rx_data_s[ 4];
assign rx_data_3[0] = rx_data_s[ 0];
assign rx_data_2[5] = rx_data_s[21];
assign rx_data_2[4] = rx_data_s[17];
assign rx_data_2[3] = rx_data_s[13];
assign rx_data_2[2] = rx_data_s[ 9];
assign rx_data_2[1] = rx_data_s[ 5];
assign rx_data_2[0] = rx_data_s[ 1];
assign rx_data_1[5] = rx_data_s[22];
assign rx_data_1[4] = rx_data_s[18];
assign rx_data_1[3] = rx_data_s[14];
assign rx_data_1[2] = rx_data_s[10];
assign rx_data_1[1] = rx_data_s[ 6];
assign rx_data_1[0] = rx_data_s[ 2];
assign rx_data_0[5] = rx_data_s[23];
assign rx_data_0[4] = rx_data_s[19];
assign rx_data_0[3] = rx_data_s[15];
assign rx_data_0[2] = rx_data_s[11];
assign rx_data_0[1] = rx_data_s[ 7];
assign rx_data_0[0] = rx_data_s[ 3];
// transmit
assign tx_clk_out_n = 1'd0;
assign tx_frame_out_n = 1'd0;
assign tx_data_out_n = 6'd0;
assign tx_data_s[24] = tx_frame[3];
assign tx_data_s[25] = tx_frame[2];
assign tx_data_s[26] = tx_frame[1];
assign tx_data_s[27] = tx_frame[0];
assign tx_data_s[20] = tx_data_3[5];
assign tx_data_s[16] = tx_data_3[4];
assign tx_data_s[12] = tx_data_3[3];
assign tx_data_s[ 8] = tx_data_3[2];
assign tx_data_s[ 4] = tx_data_3[1];
assign tx_data_s[ 0] = tx_data_3[0];
assign tx_data_s[21] = tx_data_2[5];
assign tx_data_s[17] = tx_data_2[4];
assign tx_data_s[13] = tx_data_2[3];
assign tx_data_s[ 9] = tx_data_2[2];
assign tx_data_s[ 5] = tx_data_2[1];
assign tx_data_s[ 1] = tx_data_2[0];
assign tx_data_s[22] = tx_data_1[5];
assign tx_data_s[18] = tx_data_1[4];
assign tx_data_s[14] = tx_data_1[3];
assign tx_data_s[10] = tx_data_1[2];
assign tx_data_s[ 6] = tx_data_1[1];
assign tx_data_s[ 2] = tx_data_1[0];
assign tx_data_s[23] = tx_data_0[5];
assign tx_data_s[19] = tx_data_0[4];
assign tx_data_s[15] = tx_data_0[3];
assign tx_data_s[11] = tx_data_0[2];
assign tx_data_s[ 7] = tx_data_0[1];
assign tx_data_s[ 3] = tx_data_0[0];
// instantiations
genvar i;
generate
for (i = 0; i < 6; i = i + 1) begin: g_rx_data
if (RX_NODPA == 0) begin
axi_ad9361_serdes_in i_rx_data (
.data_in_export (rx_data_in_p[i]),
.clk_export (lvds_clk),
.loaden_export (lvds_loaden),
.div_clk_export (clk),
.hs_phase_export (lvds_phase),
.locked_export (rx_data_locked_s[i]),
.data_s_export (rx_data_s[((i*4)+3):(i*4)]),
.delay_locked_export (rx_delay_locked_s[i]));
end else begin
axi_ad9361_serdes_in i_rx_data (
.data_in_export (rx_data_in_p[i]),
.clk_export (lvds_clk),
.loaden_export (lvds_loaden),
.div_clk_export (clk),
.data_s_export (rx_data_s[((i*4)+3):(i*4)]));
assign rx_data_locked_s[i] = 1'b1;
assign rx_delay_locked_s[i] = 1'b1;
end
end
if (RX_NODPA == 0) begin
axi_ad9361_serdes_in i_rx_frame (
.data_in_export (rx_frame_in_p),
.clk_export (lvds_clk),
.loaden_export (lvds_loaden),
.div_clk_export (clk),
.hs_phase_export (lvds_phase),
.locked_export (rx_data_locked_s[6]),
.data_s_export (rx_data_s[27:24]),
.delay_locked_export (rx_delay_locked_s[6]));
assign rx_clk = rx_clk_in_p;
end else begin
axi_ad9361_serdes_in i_rx_frame (
.data_in_export (rx_frame_in_p),
.clk_export (lvds_clk),
.loaden_export (lvds_loaden),
.div_clk_export (clk),
.data_s_export (rx_data_s[27:24]) );
assign rx_data_locked_s[6] = 1'b1;
assign rx_delay_locked_s[6] = 1'b1;
clk_buffer clk_buf (
.inclk (rx_clk_in_p),
.outclk (rx_clk));
end
endgenerate
generate
for (i = 0; i < 6; i = i + 1) begin: g_tx_data
axi_ad9361_serdes_out i_tx_data (
.data_out_export (tx_data_out_p[i]),
.clk_export (lvds_clk),
.loaden_export (lvds_loaden),
.div_clk_export (clk),
.data_s_export (tx_data_s[((i*4)+3):(i*4)]));
end
endgenerate
axi_ad9361_serdes_out i_tx_frame (
.data_out_export (tx_frame_out_p),
.clk_export (lvds_clk),
.loaden_export (lvds_loaden),
.div_clk_export (clk),
.data_s_export (tx_data_s[27:24]));
axi_ad9361_serdes_out i_tx_clk (
.data_out_export (tx_clk_out_p),
.clk_export (lvds_clk),
.loaden_export (lvds_loaden),
.div_clk_export (clk),
.data_s_export (4'b1010));
axi_ad9361_data_out i_enable (
.ck (clk),
.din ({tx_enable, tx_enable}),
.pad_out (enable));
axi_ad9361_data_out i_txnrx (
.ck (clk),
.din ({tx_txnrx, tx_txnrx}),
.pad_out (txnrx));
axi_ad9361_serdes_clk i_clk (
.rst_reset (pll_rst),
.ref_clk_clk (rx_clk),
.locked_export (locked_s),
.hs_phase_phout (lvds_phase),
.hs_clk_lvds_clk (lvds_clk),
.loaden_loaden (lvds_loaden),
.ls_clk_clk (clk));
endmodule
adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v
+395
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@@ -0,0 +1,395 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_lvds_if_c5 (
// physical interface (receive)
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
// physical interface (transmit)
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
// ensm control
output enable,
output txnrx,
// clock (common to both receive and transmit)
output clk,
// receive data path interface
output [ 3:0] rx_frame,
output [ 5:0] rx_data_0,
output [ 5:0] rx_data_1,
output [ 5:0] rx_data_2,
output [ 5:0] rx_data_3,
// transmit data path interface
input [ 3:0] tx_frame,
input [ 5:0] tx_data_0,
input [ 5:0] tx_data_1,
input [ 5:0] tx_data_2,
input [ 5:0] tx_data_3,
input tx_enable,
input tx_txnrx,
// locked (status)
output locked,
// delay interface
input up_clk,
input up_rstn
);
// internal registers
reg pll_rst = 1'd1;
reg locked_int = 'd0;
reg tx_core_enable_int = 'd0;
reg tx_core_txnrx_int = 'd0;
reg [27:0] tx_core_data_int = 'd0;
reg tx_core_enable = 'd0;
reg tx_core_txnrx = 'd0;
reg [27:0] tx_core_data = 'd0;
reg tx_locked_int = 'd0;
reg tx_locked = 'd0;
// internal signals
wire [27:0] rx_core_data_s;
wire rx_locked_s;
wire tx_core_clk;
wire tx_locked_s;
// pll reset
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
pll_rst <= 1'b1;
end else begin
pll_rst <= 1'b0;
end
end
assign locked = locked_int;
always @(posedge clk) begin
locked_int <= rx_locked_s & tx_locked;
end
// receive
assign rx_frame[3] = rx_core_data_s[24];
assign rx_frame[2] = rx_core_data_s[25];
assign rx_frame[1] = rx_core_data_s[26];
assign rx_frame[0] = rx_core_data_s[27];
assign rx_data_3[5] = rx_core_data_s[20];
assign rx_data_3[4] = rx_core_data_s[16];
assign rx_data_3[3] = rx_core_data_s[12];
assign rx_data_3[2] = rx_core_data_s[ 8];
assign rx_data_3[1] = rx_core_data_s[ 4];
assign rx_data_3[0] = rx_core_data_s[ 0];
assign rx_data_2[5] = rx_core_data_s[21];
assign rx_data_2[4] = rx_core_data_s[17];
assign rx_data_2[3] = rx_core_data_s[13];
assign rx_data_2[2] = rx_core_data_s[ 9];
assign rx_data_2[1] = rx_core_data_s[ 5];
assign rx_data_2[0] = rx_core_data_s[ 1];
assign rx_data_1[5] = rx_core_data_s[22];
assign rx_data_1[4] = rx_core_data_s[18];
assign rx_data_1[3] = rx_core_data_s[14];
assign rx_data_1[2] = rx_core_data_s[10];
assign rx_data_1[1] = rx_core_data_s[ 6];
assign rx_data_1[0] = rx_core_data_s[ 2];
assign rx_data_0[5] = rx_core_data_s[23];
assign rx_data_0[4] = rx_core_data_s[19];
assign rx_data_0[3] = rx_core_data_s[15];
assign rx_data_0[2] = rx_core_data_s[11];
assign rx_data_0[1] = rx_core_data_s[ 7];
assign rx_data_0[0] = rx_core_data_s[ 3];
// transmit (by definition, tx_core_clk and clk are the same (shared pll))
// however, we safe guard transition - incase you keep them separate
assign tx_clk_out_n = 1'd0;
assign tx_frame_out_n = 1'd0;
assign tx_data_out_n = 6'd0;
always @(negedge clk) begin
tx_core_enable_int <= tx_enable;
tx_core_txnrx_int <= tx_txnrx;
tx_core_data_int[24] <= tx_frame[3];
tx_core_data_int[25] <= tx_frame[2];
tx_core_data_int[26] <= tx_frame[1];
tx_core_data_int[27] <= tx_frame[0];
tx_core_data_int[20] <= tx_data_3[5];
tx_core_data_int[16] <= tx_data_3[4];
tx_core_data_int[12] <= tx_data_3[3];
tx_core_data_int[ 8] <= tx_data_3[2];
tx_core_data_int[ 4] <= tx_data_3[1];
tx_core_data_int[ 0] <= tx_data_3[0];
tx_core_data_int[21] <= tx_data_2[5];
tx_core_data_int[17] <= tx_data_2[4];
tx_core_data_int[13] <= tx_data_2[3];
tx_core_data_int[ 9] <= tx_data_2[2];
tx_core_data_int[ 5] <= tx_data_2[1];
tx_core_data_int[ 1] <= tx_data_2[0];
tx_core_data_int[22] <= tx_data_1[5];
tx_core_data_int[18] <= tx_data_1[4];
tx_core_data_int[14] <= tx_data_1[3];
tx_core_data_int[10] <= tx_data_1[2];
tx_core_data_int[ 6] <= tx_data_1[1];
tx_core_data_int[ 2] <= tx_data_1[0];
tx_core_data_int[23] <= tx_data_0[5];
tx_core_data_int[19] <= tx_data_0[4];
tx_core_data_int[15] <= tx_data_0[3];
tx_core_data_int[11] <= tx_data_0[2];
tx_core_data_int[ 7] <= tx_data_0[1];
tx_core_data_int[ 3] <= tx_data_0[0];
end
always @(posedge tx_core_clk) begin
tx_core_enable <= tx_core_enable_int;
tx_core_txnrx <= tx_core_txnrx_int;
tx_core_data <= tx_core_data_int;
end
always @(negedge tx_core_clk) begin
tx_locked_int <= tx_locked_s;
end
always @(posedge clk) begin
tx_locked <= tx_locked_int;
end
// instantiations
altlvds_rx #(
.buffer_implementation ("RAM"),
.cds_mode ("UNUSED"),
.common_rx_tx_pll ("ON"),
.data_align_rollover (4),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.dpa_initial_phase_value (0),
.dpll_lock_count (0),
.dpll_lock_window (0),
.enable_clock_pin_mode ("UNUSED"),
.enable_dpa_align_to_rising_edge_only ("OFF"),
.enable_dpa_calibration ("ON"),
.enable_dpa_fifo ("UNUSED"),
.enable_dpa_initial_phase_selection ("OFF"),
.enable_dpa_mode ("OFF"),
.enable_dpa_pll_calibration ("OFF"),
.enable_soft_cdr_mode ("OFF"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.input_data_rate (500),
.intended_device_family ("Cyclone V"),
.lose_lock_on_one_change ("UNUSED"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_lvds_if_c5_rx"),
.lpm_type ("altlvds_rx"),
.number_of_channels (7),
.outclock_resource ("Global clock"),
.pll_operation_mode ("NORMAL"),
.pll_self_reset_on_loss_lock ("UNUSED"),
.port_rx_channel_data_align ("PORT_UNUSED"),
.port_rx_data_align ("PORT_UNUSED"),
.refclk_frequency ("250.000000 MHz"),
.registered_data_align_input ("UNUSED"),
.registered_output ("ON"),
.reset_fifo_at_first_lock ("UNUSED"),
.rx_align_data_reg ("RISING_EDGE"),
.sim_dpa_is_negative_ppm_drift ("OFF"),
.sim_dpa_net_ppm_variation (0),
.sim_dpa_output_clock_phase_shift (0),
.use_coreclock_input ("OFF"),
.use_dpll_rawperror ("OFF"),
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.x_on_bitslip ("ON"),
.clk_src_is_pll ("off"))
i_altlvds_rx (
.pll_areset (pll_rst),
.rx_in ({rx_frame_in_p, rx_data_in_p}),
.rx_inclock (rx_clk_in_p),
.rx_locked (rx_locked_s),
.rx_out (rx_core_data_s),
.rx_outclock (clk),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset ({7{1'b0}}),
.rx_channel_data_align ({7{1'b0}}),
.rx_coreclk ({7{1'b1}}),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_divfwdclk (),
.rx_dpa_lock_reset ({7{1'b0}}),
.rx_dpa_locked (),
.rx_dpaclock (1'b0),
.rx_dpll_enable ({7{1'b1}}),
.rx_dpll_hold ({7{1'b0}}),
.rx_dpll_reset ({7{1'b0}}),
.rx_enable (1'b1),
.rx_fifo_reset ({7{1'b0}}),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_reset ({7{1'b0}}),
.rx_syncclock (1'b0));
altlvds_tx #(
.center_align_msb ("UNUSED"),
.common_rx_tx_pll ("ON"),
.coreclock_divide_by (1),
.data_rate ("500.0 Mbps"),
.deserialization_factor (4),
.differential_drive (0),
.enable_clock_pin_mode ("UNUSED"),
.implement_in_les ("OFF"),
.inclock_boost (0),
.inclock_data_alignment ("EDGE_ALIGNED"),
.inclock_period (4000),
.inclock_phase_shift (0),
.intended_device_family ("Cyclone V"),
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_lvds_if_c5_tx"),
.lpm_type ("altlvds_tx"),
.multi_clock ("OFF"),
.number_of_channels (7),
.outclock_alignment ("EDGE_ALIGNED"),
.outclock_divide_by (2),
.outclock_duty_cycle (50),
.outclock_multiply_by (1),
.outclock_phase_shift (0),
.outclock_resource ("Global clock"),
.output_data_rate (500),
.pll_compensation_mode ("AUTO"),
.pll_self_reset_on_loss_lock ("OFF"),
.preemphasis_setting (0),
.refclk_frequency ("250.000000 MHz"),
.registered_input ("TX_CORECLK"),
.use_external_pll ("OFF"),
.use_no_phase_shift ("ON"),
.vod_setting (0),
.clk_src_is_pll ("off"))
i_altlvds_tx (
.pll_areset (pll_rst),
.tx_in (tx_core_data),
.tx_inclock (rx_clk_in_p),
.tx_coreclock (tx_core_clk),
.tx_locked (tx_locked_s),
.tx_out ({tx_frame_out_p, tx_data_out_p}),
.tx_outclock (tx_clk_out_p),
.sync_inclock (1'b0),
.tx_data_reset (1'b0),
.tx_enable (1'b1),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
altddio_out #(
.extend_oe_disable ("OFF"),
.intended_device_family ("Cyclone V"),
.invert_output ("OFF"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNREGISTERED"),
.power_up_high ("OFF"),
.width (1))
i_altddio_enable (
.datain_h (tx_core_enable),
.datain_l (tx_core_enable),
.outclock (tx_core_clk),
.dataout (enable),
.aclr (1'b0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
altddio_out #(
.extend_oe_disable ("OFF"),
.intended_device_family ("Cyclone V"),
.invert_output ("OFF"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNREGISTERED"),
.power_up_high ("OFF"),
.width (1))
i_altddio_txnrx (
.datain_h (tx_core_txnrx),
.datain_l (tx_core_txnrx),
.outclock (tx_core_clk),
.dataout (txnrx),
.aclr (1'b0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
endmodule