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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/axi_adaq8092/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_adaq8092
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_adaq8092.v
GENERIC_DEPS += axi_adaq8092_apb_decode.v
GENERIC_DEPS += axi_adaq8092_channel.v
GENERIC_DEPS += axi_adaq8092_if.v
GENERIC_DEPS += axi_adaq8092_rand_decode.v
XILINX_DEPS += ../xilinx/common/ad_data_clk.v
XILINX_DEPS += ../xilinx/common/ad_data_in.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_adaq8092_ip.tcl
include ../scripts/library.mk
adi_library/axi_adaq8092/axi_adaq8092.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adaq8092 #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter ADC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter OUTPUT_MODE = 0,
parameter [27:0] POLARITY_MASK ='hfffffff
) (
// adc interface (clk, data, over-range)
input adc_clk_in_p,
input adc_clk_in_n,
input [ 6:0] lvds_adc_data_in1_p,
input [ 6:0] lvds_adc_data_in1_n,
input [ 6:0] lvds_adc_data_in2_p,
input [ 6:0] lvds_adc_data_in2_n,
input lvds_adc_or_in_p,
input lvds_adc_or_in_n,
input [13:0] cmos_adc_data_in1,
input [13:0] cmos_adc_data_in2,
input cmos_adc_or_in_1,
input cmos_adc_or_in_2,
// delay interface
input delay_clk,
// dma interface
output adc_clk,
output adc_rst,
output adc_valid,
output adc_enable_1,
output adc_enable_2,
output [15:0] adc_data_channel1,
output [15:0] adc_data_channel2,
input adc_dovf,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot
);
// configuration settings
localparam CONFIG = (OUTPUT_MODE * 128);
// internal registers
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
// internal clocks & resets
wire up_rstn;
wire up_clk;
wire delay_rst;
// internal signals
wire adc_or_s;
wire [27:0] adc_data_s;
wire [1:0] up_status_or_s;
wire adc_status_s;
wire [29:0] up_dld_s;
wire [149:0] up_dwdata_s;
wire [149:0] up_drdata_s;
wire delay_locked_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:3];
wire [3:0] up_rack_s;
wire [3:0] up_wack_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] adc_decoded_data_s_1;
wire [13:0] adc_decoded_data_s_2;
wire [27:0] adc_part_decoded_data_s;
wire [7:0] adc_custom_control_s;
wire sdr_or_ddr_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_valid = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_or <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_or <= up_status_or_s[0] | up_status_or_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
end
end
// ADC channel 1
axi_adaq8092_channel #(
.CHANNEL_ID(0),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)
) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_decoded_data_s_1),
.adc_or (adc_or_s),
.adc_dcfilter_data_out (adc_data_channel1),
.adc_enable (adc_enable_1),
.adc_valid (),
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// ADC channel 2
axi_adaq8092_channel #(
.CHANNEL_ID(1),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)
) i_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_decoded_data_s_2),
.adc_or (adc_or_s),
.adc_dcfilter_data_out (adc_data_channel2),
.adc_enable (adc_enable_2),
.adc_valid (),
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// ADC interface
axi_adaq8092_rand_decode i_rand (
.adc_data(adc_data_s),
.adc_clk(adc_clk),
.adc_rand_enb(adc_custom_control_s[0]),
.adc_data_decoded(adc_part_decoded_data_s));
axi_adaq8092_apb_decode i_apb (
.adc_data(adc_part_decoded_data_s),
.adc_clk(adc_clk),
.adc_abp_enb(adc_custom_control_s[1]),
.adc_data_decoded({adc_decoded_data_s_2,adc_decoded_data_s_1}));
axi_adaq8092_if #(
.OUTPUT_MODE(OUTPUT_MODE),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.POLARITY_MASK(POLARITY_MASK)
) i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.lvds_adc_data_p({lvds_adc_data_in2_p,lvds_adc_data_in1_p}),
.lvds_adc_data_n({lvds_adc_data_in2_n,lvds_adc_data_in1_n}),
.lvds_adc_or_p(lvds_adc_or_in_p),
.lvds_adc_or_n(lvds_adc_or_in_n),
.cmos_adc_data({cmos_adc_data_in2,cmos_adc_data_in1}),
.cmos_adc_data_or_1(cmos_adc_or_in_1),
.cmos_adc_data_or_2(cmos_adc_or_in_2),
.sdr_or_ddr(sdr_or_ddr_s),
.adc_clk (adc_clk),
.adc_data(adc_data_s),
.adc_or(adc_or_s),
.adc_status (adc_status_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// adc delay control
up_delay_cntrl #(
.DATA_WIDTH(30),
.BASE_ADDRESS(6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// common processor control
up_adc_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (CONFIG),
.COMMON_ID (6'h00),
.DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (0),
.GPIO_DISABLE (0),
.START_CODE_DISABLE(0)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_custom_control(adc_custom_control_s),
.adc_sdr_ddr_n(sdr_or_ddr_s),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (),
.adc_ext_sync_arm(),
.adc_ext_sync_disarm(),
.adc_ext_sync_manual_req(),
.adc_crc_enable (),
.adc_num_lanes(),
.adc_symb_op(),
.adc_symb_8_16b(),
.up_pps_rcounter(32'd0),
.up_pps_status(1'd0),
.up_pps_irq_mask(),
.up_adc_ce (),
.up_status_pn_err (),
.up_status_pn_oos (),
.up_status_or (),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd0),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_adc_r1_mode(),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
adi_library/axi_adaq8092/axi_adaq8092.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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adi_library/axi_adaq8092/axi_adaq8092_apb_decode.v
+64
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@@ -0,0 +1,64 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// ADC ALTERNATE BIT POLARITY DECODE
`timescale 1ns/100ps
module axi_adaq8092_apb_decode (
input [27:0] adc_data,
input adc_clk,
input adc_abp_enb,
output [27:0] adc_data_decoded
);
// internal registers
reg [27:0] adc_data_decoded_s;
// internal variable
integer i;
assign adc_data_decoded = adc_abp_enb ? adc_data_decoded_s : adc_data ;
always @(posedge adc_clk) begin
for (i = 0; i <= 13; i = i + 1) begin
adc_data_decoded_s[2*i+1] = ~adc_data[2*i+1];
adc_data_decoded_s[2*i] = adc_data[2*i];
end
end
endmodule
adi_library/axi_adaq8092/axi_adaq8092_channel.v
+173
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@@ -0,0 +1,173 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_adaq8092_channel #(
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0
) (
// adc interface
input adc_clk,
input adc_rst,
input [13:0] adc_data,
input adc_or,
// channel interface
output [15:0] adc_dcfilter_data_out,
output adc_valid,
output adc_enable,
output up_adc_or,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack
);
// internal signals
wire [15:0] adc_dfmt_data_s;
wire adc_dcfilt_enb_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
generate
if (DATAPATH_DISABLE == 1) begin
assign adc_dfmt_data_s = {2'b0 , adc_data};
end else begin
ad_datafmt #(
.DATA_WIDTH(14)
) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data),
.valid_out (),
.data_out (adc_dfmt_data_s),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
generate
if (DATAPATH_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
.clk (adc_clk),
.valid (1'b1),
.data (adc_dfmt_data_s),
.valid_out (adc_valid),
.data_out (adc_dcfilter_data_out),
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
endgenerate
up_adc_channel #(
.COMMON_ID (6'h01),
.CHANNEL_ID(CHANNEL_ID),
.USERPORTS_DISABLE (0),
.DATAFORMAT_DISABLE (0),
.DCFILTER_DISABLE (0),
.IQCORRECTION_DISABLE (0)
) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (),
.adc_pn_oos (),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd14),
.adc_usr_datatype_bits (8'd14),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
adi_library/axi_adaq8092/axi_adaq8092_if.v
+299
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@@ -0,0 +1,299 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
`timescale 1ns/100ps
module axi_adaq8092_if #(
parameter FPGA_TECHNOLOGY = 0,
parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter DELAY_REFCLK_FREQUENCY = 200,
parameter [27:0] POLARITY_MASK ='hfffffff,
parameter OUTPUT_MODE = 0
) (
// adc interface (clk, data, over-range)
// nominal clock 80 MHz, up to 105 MHz
input adc_clk_in_p,
input adc_clk_in_n,
input [13:0] lvds_adc_data_p,
input [13:0] lvds_adc_data_n,
input lvds_adc_or_p,
input lvds_adc_or_n,
input [27:0] cmos_adc_data,
input cmos_adc_data_or_1,
input cmos_adc_data_or_2,
// up control SDR or DDR
input sdr_or_ddr,
// interface outputs
output adc_clk,
output reg [27:0] adc_data,
output reg adc_or,
output reg adc_status,
// delay control signals
input up_clk,
input [29:0] up_dld,
input [149:0] up_dwdata,
output [149:0] up_drdata,
input delay_clk,
input delay_rst,
output delay_locked
);
// internal registers
reg [27:0] adc_data_s='b0;
// internal signals
wire [13:0] lvds_adc_data_p_s;
wire [13:0] lvds_adc_data_n_s;
wire [27:0] cmos_adc_data_p_s;
wire [27:0] cmos_adc_data_n_s;
wire adc_or_s_1;
wire adc_or_s_2;
wire adc_or_s_1_p;
wire adc_or_s_1_n;
wire adc_or_s_2_p;
wire adc_or_s_2_n;
wire [27:0] adc_data_if_out;
genvar l_inst;
// LOCAL parameters
localparam LVDS = 0;
localparam CMOS = 1;
always @(posedge adc_clk) begin
adc_status <= 1'b1;
if (OUTPUT_MODE == LVDS) begin
adc_or <= adc_or_s_1 | adc_or_s_2;
adc_data <= POLARITY_MASK ^ adc_data_s;
adc_data_s <= { lvds_adc_data_n_s[13], lvds_adc_data_p_s[13],
lvds_adc_data_n_s[12], lvds_adc_data_p_s[12],
lvds_adc_data_n_s[11], lvds_adc_data_p_s[11],
lvds_adc_data_n_s[10], lvds_adc_data_p_s[10],
lvds_adc_data_n_s[9], lvds_adc_data_p_s[9],
lvds_adc_data_n_s[8], lvds_adc_data_p_s[8],
lvds_adc_data_n_s[7], lvds_adc_data_p_s[7],
lvds_adc_data_n_s[6], lvds_adc_data_p_s[6],
lvds_adc_data_n_s[5], lvds_adc_data_p_s[5],
lvds_adc_data_n_s[4], lvds_adc_data_p_s[4],
lvds_adc_data_n_s[3], lvds_adc_data_p_s[3],
lvds_adc_data_n_s[2], lvds_adc_data_p_s[2],
lvds_adc_data_n_s[1], lvds_adc_data_p_s[1],
lvds_adc_data_n_s[0], lvds_adc_data_p_s[0]};
end else if (OUTPUT_MODE == CMOS) begin
adc_data <= adc_data_s;
if (sdr_or_ddr == 0) begin //DDR_CMOS
adc_or <= adc_or_s_1_p | adc_or_s_1_n;
adc_data_s <= { cmos_adc_data_n_s[27], cmos_adc_data_p_s[27],
cmos_adc_data_n_s[25], cmos_adc_data_p_s[25],
cmos_adc_data_n_s[23], cmos_adc_data_p_s[23],
cmos_adc_data_n_s[21], cmos_adc_data_p_s[21],
cmos_adc_data_n_s[19], cmos_adc_data_p_s[19],
cmos_adc_data_n_s[17], cmos_adc_data_p_s[17],
cmos_adc_data_n_s[15], cmos_adc_data_p_s[15],
cmos_adc_data_n_s[13], cmos_adc_data_p_s[13],
cmos_adc_data_n_s[11], cmos_adc_data_p_s[11],
cmos_adc_data_n_s[9], cmos_adc_data_p_s[9],
cmos_adc_data_n_s[7], cmos_adc_data_p_s[7],
cmos_adc_data_n_s[5], cmos_adc_data_p_s[5],
cmos_adc_data_n_s[3], cmos_adc_data_p_s[3],
cmos_adc_data_n_s[1], cmos_adc_data_p_s[1]};
end else if (sdr_or_ddr == 1) begin //SDR_CMOS
adc_or <= adc_or_s_1_p | adc_or_s_2_p;
adc_data_s <= { cmos_adc_data_p_s[27], cmos_adc_data_p_s[26],
cmos_adc_data_p_s[25], cmos_adc_data_p_s[24],
cmos_adc_data_p_s[23], cmos_adc_data_p_s[22],
cmos_adc_data_p_s[21], cmos_adc_data_p_s[20],
cmos_adc_data_p_s[19], cmos_adc_data_p_s[18],
cmos_adc_data_p_s[17], cmos_adc_data_p_s[16],
cmos_adc_data_p_s[15], cmos_adc_data_p_s[14],
cmos_adc_data_p_s[13], cmos_adc_data_p_s[12],
cmos_adc_data_p_s[11], cmos_adc_data_p_s[10],
cmos_adc_data_p_s[9], cmos_adc_data_p_s[8],
cmos_adc_data_p_s[7], cmos_adc_data_p_s[6],
cmos_adc_data_p_s[5], cmos_adc_data_p_s[4],
cmos_adc_data_p_s[3], cmos_adc_data_p_s[2],
cmos_adc_data_p_s[1], cmos_adc_data_p_s[0]};
end
end
end
// data interface
generate
if (OUTPUT_MODE == LVDS) begin
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : lvds_adc_if // DDR LVDS INTERFACE
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.IDDR_CLK_EDGE("OPPOSITE_EDGE")
) i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (lvds_adc_data_p[l_inst]),
.rx_data_in_n (lvds_adc_data_n[l_inst]),
.rx_data_p (lvds_adc_data_p_s[l_inst]),
.rx_data_n (lvds_adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
end else if (OUTPUT_MODE == CMOS) begin
for (l_inst = 0; l_inst <= 27; l_inst = l_inst + 1) begin : cmos_adc_if // CMOS INTERFACE
ad_data_in #(
.SINGLE_ENDED(1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.IDDR_CLK_EDGE("OPPOSITE_EDGE")
) i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (cmos_adc_data[l_inst]),
.rx_data_in_n (),
.rx_data_p (cmos_adc_data_p_s[l_inst]),
.rx_data_n (cmos_adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
end
endgenerate
// over-range interface
if (OUTPUT_MODE == LVDS) begin
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.IDDR_CLK_EDGE("OPPOSITE_EDGE")
) i_adc_or_lvds (
.rx_clk (adc_clk),
.rx_data_in_p (lvds_adc_or_p),
.rx_data_in_n (lvds_adc_or_n),
.rx_data_p (adc_or_s_1),
.rx_data_n (adc_or_s_2),
.up_clk (up_clk),
.up_dld (up_dld[14]),
.up_dwdata (up_dwdata[74:70]),
.up_drdata (up_drdata[74:70]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
end else if (OUTPUT_MODE == CMOS) begin
ad_data_in #(
.SINGLE_ENDED(1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.IDDR_CLK_EDGE("OPPOSITE_EDGE")
) i_adc_or_cmos_1 (
.rx_clk (adc_clk),
.rx_data_in_p (cmos_adc_data_or_1),
.rx_data_in_n (),
.rx_data_p (adc_or_s_1_p),
.rx_data_n (adc_or_s_1_n),
.up_clk (up_clk),
.up_dld (up_dld[28]),
.up_dwdata (up_dwdata[144:140]),
.up_drdata (up_drdata[144:140]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
ad_data_in #(
.SINGLE_ENDED(1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.IDDR_CLK_EDGE("OPPOSITE_EDGE")
) i_adc_or_cmos_2 (
.rx_clk (adc_clk),
.rx_data_in_p (cmos_adc_data_or_2),
.rx_data_in_n (),
.rx_data_p (adc_or_s_2_p),
.rx_data_n (adc_or_s_2_n),
.up_clk (up_clk),
.up_dld (up_dld[29]),
.up_dwdata (up_dwdata[149:145]),
.up_drdata (up_drdata[149:145]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
// clock
ad_data_clk i_adc_clk (
.rst (1'b0),
.locked (),
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
adi_library/axi_adaq8092/axi_adaq8092_ip.tcl
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###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_adaq8092
adi_ip_files axi_adaq8092 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"axi_adaq8092_if.v" \
"axi_adaq8092_channel.v" \
"axi_adaq8092_apb_decode.v"\
"axi_adaq8092_rand_decode.v"\
"axi_adaq8092.v" ]
adi_ip_properties axi_adaq8092
adi_init_bd_tcl
adi_ip_bd axi_adaq8092 "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/adaq8092} [ipx::current_core]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *adc* -of_objects [ipx::current_core]]
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {LVDS 0 CMOS 1 } \
] [ipx::get_user_parameters OUTPUT_MODE -of_objects [ipx::current_core]]
set_property enablement_dependency { $OUTPUT_MODE == 0 } \
[ipx::get_ports *lvds* -of_objects [ipx::current_core]]
set_property enablement_dependency { $OUTPUT_MODE == 1 } \
[ipx::get_ports *cmos* -of_objects [ipx::current_core]]
set_property enablement_tcl_expr {$OUTPUT_MODE == 0} \
[ipx::get_user_parameters POLARITY_MASK -of_objects [ipx::current_core]]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
set reset_intf [ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
set_property value "ACTIVE_HIGH" $reset_polarity
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/axi_adaq8092/axi_adaq8092_rand_decode.v
+71
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// ADC DIGITAL OUTPUT RANDOMIZE DECODE
`timescale 1ns/100ps
module axi_adaq8092_rand_decode (
// data interface
input [27:0] adc_data,
input adc_clk,
input adc_rand_enb,
output [27:0] adc_data_decoded
);
// internal register
reg [27:0] adc_data_decoded_s;
integer i;
assign adc_data_decoded = adc_rand_enb ? adc_data_decoded_s : adc_data ;
// DATA DECODING
always @(posedge adc_clk) begin
for (i = 1; i <= 13; i = i + 1) begin
adc_data_decoded_s[i] = adc_data[i] ^ adc_data[0];
end
for (i = 15; i <= 27; i = i + 1) begin
adc_data_decoded_s[i] = adc_data[i] ^ adc_data[14];
end
adc_data_decoded_s[0] = adc_data[0];
adc_data_decoded_s[14] = adc_data[14];
end
endmodule
adi_library/axi_adaq8092/bd/bd.tcl
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# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
DEV_PACKAGE \
SPEED_GRADE \
FPGA_FAMILY \
FPGA_TECHNOLOGY"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
adi_library/axi_adaq8092/component.xml
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adi_library/axi_adaq8092/gui/axi_adaq8092_v1_0.gtcl
+2
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@@ -0,0 +1,2 @@
# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_POLARITY_MASK_ENABLEMENT {OUTPUT_MODE } {expr $OUTPUT_MODE == 0}
adi_library/axi_adaq8092/temporary_case_dependencies.mk
+2
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CLEAN_TARGET += bd
CLEAN_TARGET += temporary_case_dependencies.mk
adi_library/axi_adaq8092/xgui/axi_adaq8092_v1_0.tcl
+161
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# Loading additional proc with user specified bodies to compute parameter values.
source [file join [file dirname [file dirname [info script]]] gui/axi_adaq8092_v1_0.gtcl]
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "ADC_DATAPATH_DISABLE" -parent ${Page_0}
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0}
ipgui::add_param $IPINST -name "OUTPUT_MODE" -parent ${Page_0}
ipgui::add_param $IPINST -name "POLARITY_MASK" -parent ${Page_0}
#Adding Group
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
}
proc update_PARAM_VALUE.POLARITY_MASK { PARAM_VALUE.POLARITY_MASK PARAM_VALUE.OUTPUT_MODE } {
# Procedure called to update POLARITY_MASK when any of the dependent parameters in the arguments change
set POLARITY_MASK ${PARAM_VALUE.POLARITY_MASK}
set OUTPUT_MODE ${PARAM_VALUE.OUTPUT_MODE}
set values(OUTPUT_MODE) [get_property value $OUTPUT_MODE]
if { [gen_USERPARAMETER_POLARITY_MASK_ENABLEMENT $values(OUTPUT_MODE)] } {
set_property enabled true $POLARITY_MASK
} else {
set_property enabled false $POLARITY_MASK
}
}
proc validate_PARAM_VALUE.POLARITY_MASK { PARAM_VALUE.POLARITY_MASK } {
# Procedure called to validate POLARITY_MASK
return true
}
proc update_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } {
# Procedure called to update ADC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } {
# Procedure called to validate ADC_DATAPATH_DISABLE
return true
}
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to validate DEV_PACKAGE
return true
}
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to validate FPGA_FAMILY
return true
}
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to validate FPGA_TECHNOLOGY
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
# Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
# Procedure called to validate IO_DELAY_GROUP
return true
}
proc update_PARAM_VALUE.OUTPUT_MODE { PARAM_VALUE.OUTPUT_MODE } {
# Procedure called to update OUTPUT_MODE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.OUTPUT_MODE { PARAM_VALUE.OUTPUT_MODE } {
# Procedure called to validate OUTPUT_MODE
return true
}
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to validate SPEED_GRADE
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
}
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
}
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
}
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
}
proc update_MODELPARAM_VALUE.ADC_DATAPATH_DISABLE { MODELPARAM_VALUE.ADC_DATAPATH_DISABLE PARAM_VALUE.ADC_DATAPATH_DISABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ADC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAPATH_DISABLE}
}
proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP}
}
proc update_MODELPARAM_VALUE.OUTPUT_MODE { MODELPARAM_VALUE.OUTPUT_MODE PARAM_VALUE.OUTPUT_MODE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.OUTPUT_MODE}] ${MODELPARAM_VALUE.OUTPUT_MODE}
}
proc update_MODELPARAM_VALUE.POLARITY_MASK { MODELPARAM_VALUE.POLARITY_MASK PARAM_VALUE.POLARITY_MASK } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.POLARITY_MASK}] ${MODELPARAM_VALUE.POLARITY_MASK}
}