initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_clkgen
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clkgen.v
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GENERIC_DEPS += axi_clkgen.v
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XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v
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XILINX_DEPS += axi_clkgen_ip.tcl
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XILINX_DEPS += bd/bd.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,222 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// software programmable clock generator (still needs a reference input!)
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`timescale 1ns/100ps
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module axi_clkgen #(
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter FPGA_VOLTAGE = 0,
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parameter CLKSEL_EN = 0,
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parameter real CLKIN_PERIOD = 5.000,
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parameter real CLKIN2_PERIOD = 5.000,
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parameter integer VCO_DIV = 11,
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parameter real VCO_MUL = 49.000,
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parameter real CLK0_DIV = 6.000,
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parameter real CLK0_PHASE = 0.000,
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parameter integer CLK1_DIV = 6,
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parameter real CLK1_PHASE = 0.000
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) (
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// clocks
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input clk,
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input clk2,
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output clk_0,
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output clk_1,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot
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);
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// reset and clocks
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wire mmcm_rst;
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wire clk_sel_s;
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wire up_clk_sel_s;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire up_drp_sel_s;
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wire up_drp_wr_s;
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wire [11:0] up_drp_addr_s;
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wire [15:0] up_drp_wdata_s;
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wire [15:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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wire up_drp_locked_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s;
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wire up_rack_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// processor interface
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up_clkgen #(
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.ID(ID),
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.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
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.FPGA_FAMILY(FPGA_FAMILY),
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.SPEED_GRADE(SPEED_GRADE),
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.DEV_PACKAGE(DEV_PACKAGE),
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.FPGA_VOLTAGE(FPGA_VOLTAGE)
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) i_up_clkgen (
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.mmcm_rst (mmcm_rst),
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.clk_sel (up_clk_sel_s),
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.up_drp_sel (up_drp_sel_s),
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.up_drp_wr (up_drp_wr_s),
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.up_drp_addr (up_drp_addr_s),
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.up_drp_wdata (up_drp_wdata_s),
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.up_drp_rdata (up_drp_rdata_s),
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.up_drp_ready (up_drp_ready_s),
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.up_drp_locked (up_drp_locked_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// If CLKSEL_EN is not active, the clk0 port of the MMCM is used, this
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// should be used when the MMCM has only one active clock source
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generate if (CLKSEL_EN == 1) begin
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assign clk_sel_s = up_clk_sel_s;
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end else begin
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assign clk_sel_s = 1'b1;
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end
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endgenerate
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// mmcm instantiations
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ad_mmcm_drp #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.MMCM_CLKIN_PERIOD (CLKIN_PERIOD),
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.MMCM_CLKIN2_PERIOD (CLKIN2_PERIOD),
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.MMCM_VCO_DIV (VCO_DIV),
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.MMCM_VCO_MUL (VCO_MUL),
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.MMCM_CLK0_DIV (CLK0_DIV),
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.MMCM_CLK0_PHASE (CLK0_PHASE),
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.MMCM_CLK1_DIV (CLK1_DIV),
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.MMCM_CLK1_PHASE (CLK1_PHASE)
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) i_mmcm_drp (
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.clk (clk),
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.clk2 (clk2),
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.clk_sel(clk_sel_s),
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.mmcm_rst (mmcm_rst),
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.mmcm_clk_0 (clk_0),
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.mmcm_clk_1 (clk_1),
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.mmcm_clk_2 (),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel_s),
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.up_drp_wr (up_drp_wr_s),
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.up_drp_addr (up_drp_addr_s),
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.up_drp_wdata (up_drp_wdata_s),
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.up_drp_rdata (up_drp_rdata_s),
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.up_drp_ready (up_drp_ready_s),
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.up_drp_locked (up_drp_locked_s));
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endmodule
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@@ -0,0 +1,441 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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||||
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||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_clkgen/axi_clkgen.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="26e82b0ffa23468db83dd550853d79e4"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_mmcm_drp.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_clkgen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_clkgen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../scripts/adi_xilinx_device_info_enc.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_clkgen"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,62 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ip
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_clkgen
|
||||
adi_ip_files axi_clkgen [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_clkgen.v" \
|
||||
"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
|
||||
"bd/bd.tcl" \
|
||||
"axi_clkgen.v" ]
|
||||
|
||||
adi_ip_properties axi_clkgen
|
||||
adi_ip_bd axi_clkgen "bd/bd.tcl"
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_clkgen} [ipx::current_core]
|
||||
|
||||
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
set cc [ipx::current_core]
|
||||
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
|
||||
set param [ipx::add_user_parameter ENABLE_CLKIN2 $cc]
|
||||
set_property -dict {value_resolve_type user value_format bool value false} $param
|
||||
|
||||
set param [ipgui::add_param -name {ENABLE_CLKIN2} -component $cc -parent $page0]
|
||||
set_property -dict [list \
|
||||
display_name {Enable secondary clock input} \
|
||||
widget {checkBox} \
|
||||
] $param
|
||||
|
||||
set param [ipx::add_user_parameter ENABLE_CLKOUT1 $cc]
|
||||
set_property -dict {value_resolve_type user value_format bool value false} $param
|
||||
|
||||
set param [ipgui::add_param -name {ENABLE_CLKOUT1} -component $cc -parent $page0]
|
||||
set_property -dict [list \
|
||||
display_name {Enable secondary clock output} \
|
||||
widget {checkBox} \
|
||||
] $param
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc]
|
||||
set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc]
|
||||
set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc]
|
||||
|
||||
adi_set_ports_dependency clk2 ENABLE_CLKIN2 0
|
||||
adi_set_ports_dependency clk_1 ENABLE_CLKOUT1
|
||||
|
||||
ipx::create_xgui_files $cc
|
||||
ipx::save_core $cc
|
||||
@@ -0,0 +1,124 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_override $ip \
|
||||
"CLKIN_PERIOD \
|
||||
CLKIN2_PERIOD \
|
||||
FPGA_VOLTAGE"
|
||||
|
||||
bd::mark_propagate_only $ip \
|
||||
"FPGA_TECHNOLOGY \
|
||||
FPGA_FAMILY \
|
||||
SPEED_GRADE \
|
||||
DEV_PACKAGE \
|
||||
FPGA_VOLTAGE"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
proc axi_clkgen_get_infer_period {ip param clk_name} {
|
||||
set param_src [get_property "CONFIG.$param.VALUE_SRC" $ip]
|
||||
if {[string equal $param_src "USER"]} {
|
||||
return;
|
||||
}
|
||||
|
||||
set clk [get_bd_pins "$ip/$clk_name"]
|
||||
set clk_freq [get_property CONFIG.FREQ_HZ $clk]
|
||||
|
||||
if {$clk_freq != {}} {
|
||||
set clk_period [expr 1000000000.0 / $clk_freq]
|
||||
set_property "CONFIG.$param" [format "%.6f" $clk_period] $ip
|
||||
}
|
||||
}
|
||||
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc propagate {cellpath otherinfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
set vco_mul [get_property CONFIG.VCO_MUL $ip]
|
||||
set vco_div [get_property CONFIG.VCO_DIV $ip]
|
||||
set clk0_div [get_property CONFIG.CLK0_DIV $ip]
|
||||
set clk1_div [get_property CONFIG.CLK1_DIV $ip]
|
||||
|
||||
if {$vco_mul == {} || $vco_mul < 1} {
|
||||
set vco_mul 1
|
||||
}
|
||||
if {$vco_div == {} || $vco_div < 1} {
|
||||
set vco_div 1
|
||||
}
|
||||
if {$clk0_div == {} || $clk0_div < 1} {
|
||||
set clk0_div 1
|
||||
}
|
||||
if {$clk1_div == {} || $clk0_div < 1} {
|
||||
set clk1_div 1
|
||||
}
|
||||
|
||||
set clk [get_bd_pins "$ip/clk"]
|
||||
set clk_freq [get_property CONFIG.FREQ_HZ $clk]
|
||||
if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} {
|
||||
set clk2 [get_bd_pins "$ip/clk"]
|
||||
set clk2_freq [get_property CONFIG.FREQ_HZ $clk2]
|
||||
# Use the larger of the two
|
||||
if {$clk_freq == {} || $clk2_freq > $clk_freq} {
|
||||
set clk_freq $clk2_freq
|
||||
}
|
||||
}
|
||||
|
||||
if {$clk_freq != {}} {
|
||||
set clk0_out [get_bd_pins "$ip/clk_0"]
|
||||
set clk0_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk0_div)]
|
||||
set_property CONFIG.FREQ_HZ $clk0_out_freq $clk0_out
|
||||
|
||||
if {[get_property "CONFIG.ENABLE_CLKOUT1" $ip] == "true"} {
|
||||
set clk1_out [get_bd_pins "$ip/clk_1"]
|
||||
set clk1_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk1_div)]
|
||||
set_property CONFIG.FREQ_HZ $clk1_out_freq $clk1_out
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc post_propagate {cellpath otherinfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
axi_clkgen_get_infer_period $ip CLKIN_PERIOD clk
|
||||
if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} {
|
||||
axi_clkgen_get_infer_period $ip CLKIN2_PERIOD clk2
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,4 @@
|
||||
# This file is automatically written. Do not modify.
|
||||
proc gen_USERPARAMETER_CLKIN2_PERIOD_ENABLEMENT {ENABLE_CLKIN2 } {expr $ENABLE_CLKIN2}
|
||||
proc gen_USERPARAMETER_CLK1_DIV_ENABLEMENT {ENABLE_CLKOUT1 } {expr $ENABLE_CLKOUT1}
|
||||
proc gen_USERPARAMETER_CLK1_PHASE_ENABLEMENT {ENABLE_CLKOUT1 } {expr $ENABLE_CLKOUT1}
|
||||
@@ -0,0 +1,289 @@
|
||||
|
||||
# Loading additional proc with user specified bodies to compute parameter values.
|
||||
source [file join [file dirname [file dirname [info script]]] gui/axi_clkgen_v1_0.gtcl]
|
||||
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "CLK0_DIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLK0_PHASE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLK1_DIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLK1_PHASE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLKIN2_PERIOD" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLKIN_PERIOD" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CLKSEL_EN" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "VCO_DIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "VCO_MUL" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ENABLE_CLKIN2" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ENABLE_CLKOUT1" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_VOLTAGE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLK1_DIV { PARAM_VALUE.CLK1_DIV PARAM_VALUE.ENABLE_CLKOUT1 } {
|
||||
# Procedure called to update CLK1_DIV when any of the dependent parameters in the arguments change
|
||||
|
||||
set CLK1_DIV ${PARAM_VALUE.CLK1_DIV}
|
||||
set ENABLE_CLKOUT1 ${PARAM_VALUE.ENABLE_CLKOUT1}
|
||||
set values(ENABLE_CLKOUT1) [get_property value $ENABLE_CLKOUT1]
|
||||
if { [gen_USERPARAMETER_CLK1_DIV_ENABLEMENT $values(ENABLE_CLKOUT1)] } {
|
||||
set_property enabled true $CLK1_DIV
|
||||
} else {
|
||||
set_property enabled false $CLK1_DIV
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLK1_DIV { PARAM_VALUE.CLK1_DIV } {
|
||||
# Procedure called to validate CLK1_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLK1_PHASE { PARAM_VALUE.CLK1_PHASE PARAM_VALUE.ENABLE_CLKOUT1 } {
|
||||
# Procedure called to update CLK1_PHASE when any of the dependent parameters in the arguments change
|
||||
|
||||
set CLK1_PHASE ${PARAM_VALUE.CLK1_PHASE}
|
||||
set ENABLE_CLKOUT1 ${PARAM_VALUE.ENABLE_CLKOUT1}
|
||||
set values(ENABLE_CLKOUT1) [get_property value $ENABLE_CLKOUT1]
|
||||
if { [gen_USERPARAMETER_CLK1_PHASE_ENABLEMENT $values(ENABLE_CLKOUT1)] } {
|
||||
set_property enabled true $CLK1_PHASE
|
||||
} else {
|
||||
set_property enabled false $CLK1_PHASE
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLK1_PHASE { PARAM_VALUE.CLK1_PHASE } {
|
||||
# Procedure called to validate CLK1_PHASE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLKIN2_PERIOD { PARAM_VALUE.CLKIN2_PERIOD PARAM_VALUE.ENABLE_CLKIN2 } {
|
||||
# Procedure called to update CLKIN2_PERIOD when any of the dependent parameters in the arguments change
|
||||
|
||||
set CLKIN2_PERIOD ${PARAM_VALUE.CLKIN2_PERIOD}
|
||||
set ENABLE_CLKIN2 ${PARAM_VALUE.ENABLE_CLKIN2}
|
||||
set values(ENABLE_CLKIN2) [get_property value $ENABLE_CLKIN2]
|
||||
if { [gen_USERPARAMETER_CLKIN2_PERIOD_ENABLEMENT $values(ENABLE_CLKIN2)] } {
|
||||
set_property enabled true $CLKIN2_PERIOD
|
||||
} else {
|
||||
set_property enabled false $CLKIN2_PERIOD
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLKIN2_PERIOD { PARAM_VALUE.CLKIN2_PERIOD } {
|
||||
# Procedure called to validate CLKIN2_PERIOD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLK0_DIV { PARAM_VALUE.CLK0_DIV } {
|
||||
# Procedure called to update CLK0_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLK0_DIV { PARAM_VALUE.CLK0_DIV } {
|
||||
# Procedure called to validate CLK0_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLK0_PHASE { PARAM_VALUE.CLK0_PHASE } {
|
||||
# Procedure called to update CLK0_PHASE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLK0_PHASE { PARAM_VALUE.CLK0_PHASE } {
|
||||
# Procedure called to validate CLK0_PHASE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLKIN_PERIOD { PARAM_VALUE.CLKIN_PERIOD } {
|
||||
# Procedure called to update CLKIN_PERIOD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLKIN_PERIOD { PARAM_VALUE.CLKIN_PERIOD } {
|
||||
# Procedure called to validate CLKIN_PERIOD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CLKSEL_EN { PARAM_VALUE.CLKSEL_EN } {
|
||||
# Procedure called to update CLKSEL_EN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CLKSEL_EN { PARAM_VALUE.CLKSEL_EN } {
|
||||
# Procedure called to validate CLKSEL_EN
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ENABLE_CLKIN2 { PARAM_VALUE.ENABLE_CLKIN2 } {
|
||||
# Procedure called to update ENABLE_CLKIN2 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ENABLE_CLKIN2 { PARAM_VALUE.ENABLE_CLKIN2 } {
|
||||
# Procedure called to validate ENABLE_CLKIN2
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ENABLE_CLKOUT1 { PARAM_VALUE.ENABLE_CLKOUT1 } {
|
||||
# Procedure called to update ENABLE_CLKOUT1 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ENABLE_CLKOUT1 { PARAM_VALUE.ENABLE_CLKOUT1 } {
|
||||
# Procedure called to validate ENABLE_CLKOUT1
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } {
|
||||
# Procedure called to update FPGA_VOLTAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } {
|
||||
# Procedure called to validate FPGA_VOLTAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.VCO_DIV { PARAM_VALUE.VCO_DIV } {
|
||||
# Procedure called to update VCO_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.VCO_DIV { PARAM_VALUE.VCO_DIV } {
|
||||
# Procedure called to validate VCO_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.VCO_MUL { PARAM_VALUE.VCO_MUL } {
|
||||
# Procedure called to update VCO_MUL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.VCO_MUL { PARAM_VALUE.VCO_MUL } {
|
||||
# Procedure called to validate VCO_MUL
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_VOLTAGE { MODELPARAM_VALUE.FPGA_VOLTAGE PARAM_VALUE.FPGA_VOLTAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_VOLTAGE}] ${MODELPARAM_VALUE.FPGA_VOLTAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLKSEL_EN { MODELPARAM_VALUE.CLKSEL_EN PARAM_VALUE.CLKSEL_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLKSEL_EN}] ${MODELPARAM_VALUE.CLKSEL_EN}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLKIN_PERIOD { MODELPARAM_VALUE.CLKIN_PERIOD PARAM_VALUE.CLKIN_PERIOD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLKIN_PERIOD}] ${MODELPARAM_VALUE.CLKIN_PERIOD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLKIN2_PERIOD { MODELPARAM_VALUE.CLKIN2_PERIOD PARAM_VALUE.CLKIN2_PERIOD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLKIN2_PERIOD}] ${MODELPARAM_VALUE.CLKIN2_PERIOD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.VCO_DIV { MODELPARAM_VALUE.VCO_DIV PARAM_VALUE.VCO_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.VCO_DIV}] ${MODELPARAM_VALUE.VCO_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.VCO_MUL { MODELPARAM_VALUE.VCO_MUL PARAM_VALUE.VCO_MUL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.VCO_MUL}] ${MODELPARAM_VALUE.VCO_MUL}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLK0_DIV { MODELPARAM_VALUE.CLK0_DIV PARAM_VALUE.CLK0_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLK0_DIV}] ${MODELPARAM_VALUE.CLK0_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLK0_PHASE { MODELPARAM_VALUE.CLK0_PHASE PARAM_VALUE.CLK0_PHASE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLK0_PHASE}] ${MODELPARAM_VALUE.CLK0_PHASE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLK1_DIV { MODELPARAM_VALUE.CLK1_DIV PARAM_VALUE.CLK1_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLK1_DIV}] ${MODELPARAM_VALUE.CLK1_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CLK1_PHASE { MODELPARAM_VALUE.CLK1_PHASE PARAM_VALUE.CLK1_PHASE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CLK1_PHASE}] ${MODELPARAM_VALUE.CLK1_PHASE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user