initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_dac_interpolate
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GENERIC_DEPS += ../common/ad_iqcor.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += axi_dac_interpolate.v
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GENERIC_DEPS += axi_dac_interpolate_filter.v
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GENERIC_DEPS += axi_dac_interpolate_reg.v
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GENERIC_DEPS += cic_interp.v
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GENERIC_DEPS += fir_interp.v
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XILINX_DEPS += ../xilinx/common/ad_mul.v
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += axi_dac_interpolate_constr.xdc
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XILINX_DEPS += axi_dac_interpolate_ip.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,341 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dac_interpolate #(
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parameter CORRECTION_DISABLE = 1
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) (
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input dac_clk,
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input dac_rst,
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input [15:0] dac_data_a,
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input [15:0] dac_data_b,
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input dac_valid_a,
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input dac_valid_b,
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input dma_valid_a,
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input dma_valid_b,
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output dma_ready_a,
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output dma_ready_b,
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input dac_enable_a,
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input dac_enable_b,
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output [15:0] dac_int_data_a,
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output [15:0] dac_int_data_b,
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output dac_valid_out_a,
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output dac_valid_out_b,
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output underflow,
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input [ 1:0] trigger_i,
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input trigger_adc,
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input trigger_la,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 6:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 6:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready
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);
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reg [ 1:0] trigger_i_m1;
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reg [ 1:0] trigger_i_m2;
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reg [ 1:0] trigger_i_m3;
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reg trigger_adc_m1;
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reg trigger_adc_m2;
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reg trigger_adc_m3;
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reg trigger_la_m1;
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reg trigger_la_m2;
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reg trigger_la_m3;
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reg [ 1:0] any_edge_trigger;
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reg [ 1:0] rise_edge_trigger;
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reg [ 1:0] fall_edge_trigger;
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reg [ 1:0] high_level_trigger;
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reg [ 1:0] low_level_trigger;
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire [ 4:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_wreq;
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wire up_rack;
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wire [31:0] up_rdata;
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wire up_rreq;
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wire [ 4:0] up_raddr;
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wire [31:0] interpolation_ratio_a;
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wire [31:0] interpolation_ratio_b;
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wire [ 2:0] filter_mask_a;
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wire [ 2:0] filter_mask_b;
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wire dma_transfer_suspend;
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wire flush_dma_s;
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wire start_sync_channels;
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wire dac_correction_enable_a;
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wire dac_correction_enable_b;
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wire [15:0] dac_correction_coefficient_a;
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wire [15:0] dac_correction_coefficient_b;
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wire [19:0] trigger_config;
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wire en_start_trigger;
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wire en_stop_trigger;
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wire [ 1:0] en_trigger_pins;
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wire en_trigger_adc;
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wire en_trigger_la;
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wire [ 1:0] low_level;
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wire [ 1:0] high_level;
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wire [ 1:0] any_edge;
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wire [ 1:0] rise_edge;
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wire [ 1:0] fall_edge;
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wire trigger_active;
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wire trigger;
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wire ext_trigger;
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wire underflow_a;
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wire underflow_b;
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wire stop_sync_channels;
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wire [ 1:0] raw_transfer_en;
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wire [15:0] dac_raw_ch_a_data;
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wire [15:0] dac_raw_ch_b_data;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// trigger logic
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assign low_level = trigger_config[1:0];
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assign high_level = trigger_config[3:2];
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assign any_edge = trigger_config[5:4];
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assign rise_edge = trigger_config[7:6];
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assign fall_edge = trigger_config[9:8];
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assign en_start_trigger = trigger_config[14];
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assign en_stop_trigger = trigger_config[15];
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assign en_trigger_pins = trigger_config[17:16];
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assign en_trigger_adc = trigger_config[18];
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assign en_trigger_la = trigger_config[19];
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assign trigger_active = |trigger_config[19:16];
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assign trigger = (ext_trigger & en_trigger_pins) |
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(trigger_adc_m2 & en_trigger_adc) |
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(trigger_la_m2 & en_trigger_la);
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assign ext_trigger = |(any_edge_trigger |
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rise_edge_trigger |
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fall_edge_trigger |
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high_level_trigger |
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low_level_trigger);
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// sync
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always @(posedge dac_clk) begin
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trigger_i_m1 <= trigger_i;
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trigger_i_m2 <= trigger_i_m1;
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trigger_i_m3 <= trigger_i_m2;
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trigger_adc_m1 <= trigger_adc;
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trigger_adc_m2 <= trigger_adc_m1;
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trigger_la_m1 <= trigger_la;
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trigger_la_m2 <= trigger_la_m1;
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end
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always @(posedge dac_clk) begin
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any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & any_edge;
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rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & rise_edge;
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fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & fall_edge;
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high_level_trigger <= trigger_i_m3 & high_level;
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low_level_trigger <= ~trigger_i_m3 & low_level;
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end
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assign underflow = underflow_a | underflow_b;
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axi_dac_interpolate_filter #(
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.CORRECTION_DISABLE (CORRECTION_DISABLE)
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) i_filter_a (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data (dac_data_a),
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.dac_valid (dac_valid_a),
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.dac_valid_out (dac_valid_out_a),
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.dac_enable (dac_enable_a),
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.dac_int_data (dac_int_data_a),
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.dma_ready (dma_ready_a),
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.underflow (underflow_a),
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.filter_mask (filter_mask_a),
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.interpolation_ratio (interpolation_ratio_a),
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.dma_transfer_suspend (dma_transfer_suspend),
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.start_sync_channels (start_sync_channels),
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.sync_stop_channels (stop_sync_channels),
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.flush_dma_in (flush_dma_s),
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.raw_transfer_en (raw_transfer_en[0]),
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.dac_raw_ch_data (dac_raw_ch_a_data),
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.trigger (trigger),
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.trigger_active (trigger_active),
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.en_start_trigger (en_start_trigger),
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.en_stop_trigger (en_stop_trigger),
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.dma_valid (dma_valid_a),
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.dma_valid_adjacent (dma_valid_b),
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.dac_correction_enable(dac_correction_enable_a),
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.dac_correction_coefficient(dac_correction_coefficient_a));
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axi_dac_interpolate_filter #(
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.CORRECTION_DISABLE(CORRECTION_DISABLE)
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) i_filter_b (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data (dac_data_b),
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.dac_valid (dac_valid_b),
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.dac_valid_out (dac_valid_out_b),
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.underflow (underflow_b),
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.dac_enable (dac_enable_b),
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.dac_int_data (dac_int_data_b),
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.dma_ready (dma_ready_b),
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.filter_mask (filter_mask_b),
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.interpolation_ratio (interpolation_ratio_b),
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.dma_transfer_suspend (dma_transfer_suspend),
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.start_sync_channels (start_sync_channels),
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.sync_stop_channels (stop_sync_channels),
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.flush_dma_in (flush_dma_s),
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.raw_transfer_en (raw_transfer_en[1]),
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.dac_raw_ch_data (dac_raw_ch_b_data),
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.trigger (trigger),
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.trigger_active (trigger_active),
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.en_start_trigger (en_start_trigger),
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.en_stop_trigger (en_stop_trigger),
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.dma_valid (dma_valid_b),
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.dma_valid_adjacent (dma_valid_a),
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.dac_correction_enable(dac_correction_enable_b),
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.dac_correction_coefficient(dac_correction_coefficient_b));
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axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
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.clk (dac_clk),
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.dac_interpolation_ratio_a (interpolation_ratio_a),
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.dac_filter_mask_a (filter_mask_a),
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.dac_interpolation_ratio_b (interpolation_ratio_b),
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.dac_filter_mask_b (filter_mask_b),
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.dma_transfer_suspend (dma_transfer_suspend),
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.flush_dma_out (flush_dma_s),
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.raw_transfer_en (raw_transfer_en),
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.dac_raw_ch_a_data (dac_raw_ch_a_data),
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.dac_raw_ch_b_data (dac_raw_ch_b_data),
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.start_sync_channels (start_sync_channels),
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.dac_correction_enable_a(dac_correction_enable_a),
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.dac_correction_enable_b(dac_correction_enable_b),
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.dac_correction_coefficient_a(dac_correction_coefficient_a),
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.dac_correction_coefficient_b(dac_correction_coefficient_b),
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.trigger_config (trigger_config),
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.stop_sync_channels (stop_sync_channels),
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||||
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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up_axi #(
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||||
.AXI_ADDRESS_WIDTH(7)
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||||
) i_up_axi (
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||||
.up_rstn (up_rstn),
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||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
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||||
@@ -0,0 +1,467 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_dac_interpolate/axi_dac_interpolate.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="310465cb0190479ca3545deb6a343657"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,12 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_i_m*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_adc_m*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_la_m*}]
|
||||
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *trigger_i_m1_reg* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *trigger_adc_m1_reg* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *trigger_la_m1_reg* && IS_SEQUENTIAL}]
|
||||
@@ -0,0 +1,291 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_dac_interpolate_filter #(
|
||||
|
||||
parameter CORRECTION_DISABLE = 1
|
||||
) (
|
||||
input dac_clk,
|
||||
input dac_rst,
|
||||
|
||||
input [15:0] dac_data,
|
||||
input dac_valid,
|
||||
|
||||
input dac_enable,
|
||||
output reg [15:0] dac_int_data,
|
||||
output dma_ready,
|
||||
output dac_valid_out,
|
||||
output underflow,
|
||||
|
||||
input [ 2:0] filter_mask,
|
||||
input [31:0] interpolation_ratio,
|
||||
input [15:0] dac_correction_coefficient,
|
||||
input dac_correction_enable,
|
||||
input dma_transfer_suspend,
|
||||
input start_sync_channels,
|
||||
input sync_stop_channels,
|
||||
input flush_dma_in,
|
||||
input raw_transfer_en,
|
||||
input [15:0] dac_raw_ch_data,
|
||||
input trigger,
|
||||
input trigger_active,
|
||||
input en_start_trigger,
|
||||
input en_stop_trigger,
|
||||
input dma_valid,
|
||||
input dma_valid_adjacent
|
||||
);
|
||||
|
||||
// local parameters
|
||||
|
||||
localparam [1:0] IDLE = 0;
|
||||
localparam [1:0] WAIT = 1;
|
||||
localparam [1:0] TRANSFER = 2;
|
||||
localparam [1:0] FLUSHING = 3;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dac_int_ready;
|
||||
reg dac_filt_int_valid;
|
||||
reg [15:0] interp_rate_cic;
|
||||
reg [ 2:0] filter_mask_d1;
|
||||
reg cic_change_rate;
|
||||
reg [31:0] interpolation_counter;
|
||||
|
||||
reg dma_data_valid = 1'b0;
|
||||
reg dma_data_valid_adjacent = 1'b0;
|
||||
|
||||
reg filter_enable = 1'b0;
|
||||
reg [15:0] dma_valid_m = 16'd0;
|
||||
reg stop_transfer = 1'd0;
|
||||
|
||||
reg transfer = 1'd0;
|
||||
reg [ 1:0] transfer_sm = 2'd0;
|
||||
reg [ 1:0] transfer_sm_next = 2'd0;
|
||||
reg raw_dma_n = 1'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_valid_corrected;
|
||||
wire [15:0] dac_data_corrected;
|
||||
wire dac_fir_valid;
|
||||
wire [35:0] dac_fir_data;
|
||||
|
||||
wire dac_cic_valid;
|
||||
wire [109:0] dac_cic_data;
|
||||
|
||||
wire dma_valid_ch_sync;
|
||||
wire dma_valid_ch;
|
||||
wire flush_dma;
|
||||
|
||||
wire [15:0] iqcor_data_in;
|
||||
wire iqcor_valid_in;
|
||||
|
||||
wire transfer_start;
|
||||
wire transfer_ready;
|
||||
|
||||
// Once enabled the raw value will be selected until the DMA has valid data.
|
||||
// This is a workaround for when DAC channels are start/stopped independent
|
||||
// of each other and working in cyclic mode at a lower samplerate. It is
|
||||
// used to solve a system limitation(delay) between the application and
|
||||
// Linux kernel, which resulted in a pulse at the beginning of a new buffer
|
||||
// consisting in the last sample on the DMA bus.
|
||||
always @(posedge dac_clk) begin
|
||||
raw_dma_n <= raw_transfer_en | flush_dma ? 1'b1 : raw_dma_n & !dma_valid;
|
||||
end
|
||||
|
||||
assign reset_filt = !raw_dma_n & dma_transfer_suspend;
|
||||
|
||||
assign iqcor_data_in = raw_dma_n ? dac_raw_ch_data : dac_data;
|
||||
assign iqcor_valid_in = raw_dma_n ? 1'b1 : dac_valid;
|
||||
|
||||
ad_iqcor #(
|
||||
.Q_OR_I_N (0),
|
||||
.DISABLE(CORRECTION_DISABLE),
|
||||
.SCALE_ONLY(1)
|
||||
) i_ad_iqcor (
|
||||
.clk (dac_clk),
|
||||
.valid (iqcor_valid_in),
|
||||
.data_in (iqcor_data_in),
|
||||
.data_iq (16'h0),
|
||||
.valid_out (dac_valid_corrected),
|
||||
.data_out (dac_data_corrected),
|
||||
.iqcor_enable (dac_correction_enable),
|
||||
.iqcor_coeff_1 (dac_correction_coefficient),
|
||||
.iqcor_coeff_2 (16'h0));
|
||||
|
||||
fir_interp fir_interpolation (
|
||||
.clk (dac_clk),
|
||||
.clk_enable (dac_cic_valid),
|
||||
.reset (dac_rst | reset_filt),
|
||||
.filter_in (dac_data_corrected),
|
||||
.filter_out (dac_fir_data),
|
||||
.ce_out (dac_fir_valid));
|
||||
|
||||
cic_interp cic_interpolation (
|
||||
.clk (dac_clk),
|
||||
.clk_enable (dac_valid_corrected),
|
||||
.reset (dac_rst | cic_change_rate | reset_filt),
|
||||
.rate (interp_rate_cic),
|
||||
.load_rate (1'b0),
|
||||
.filter_in (dac_fir_data[30:0]),
|
||||
.filter_out (dac_cic_data),
|
||||
.ce_out (dac_cic_valid));
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
filter_mask_d1 <= filter_mask;
|
||||
if (filter_mask_d1 != filter_mask) begin
|
||||
cic_change_rate <= 1'b1;
|
||||
end else begin
|
||||
cic_change_rate <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// - for start synchronized, wait until the DMA has valid data on both channels
|
||||
// - for non synchronized channels the start of transmission gets the 2 data
|
||||
// paths randomly ready, only when using data buffers
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_filt_int_valid & transfer_ready) begin
|
||||
if (interpolation_counter == interpolation_ratio) begin
|
||||
interpolation_counter <= 0;
|
||||
dac_int_ready <= 1'b1;
|
||||
end else begin
|
||||
interpolation_counter <= interpolation_counter + 1;
|
||||
dac_int_ready <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
dac_int_ready <= 1'b0;
|
||||
interpolation_counter <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
assign transfer_ready = start_sync_channels ?
|
||||
dma_valid & dma_valid_adjacent :
|
||||
dma_valid;
|
||||
assign transfer_start = !(en_start_trigger ^ trigger) & transfer_ready;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
stop_transfer <= transfer_sm == IDLE ? 1'b0 :
|
||||
stop_transfer |
|
||||
dma_transfer_suspend |
|
||||
(en_stop_trigger & trigger) |
|
||||
(sync_stop_channels & dma_valid & dma_valid_adjacent);
|
||||
end
|
||||
|
||||
// transfer state machine
|
||||
always @(posedge dac_clk) begin
|
||||
case (transfer_sm)
|
||||
IDLE: begin
|
||||
transfer <= 1'b0;
|
||||
if (dac_int_ready) begin
|
||||
transfer_sm_next <= WAIT;
|
||||
end
|
||||
end
|
||||
WAIT: begin
|
||||
transfer <= 1'b0;
|
||||
if (transfer_start) begin
|
||||
transfer_sm_next <= TRANSFER;
|
||||
end
|
||||
end
|
||||
TRANSFER: begin
|
||||
transfer <= 1'b1;
|
||||
if (stop_transfer) begin
|
||||
if (flush_dma_in) begin
|
||||
transfer_sm_next <= FLUSHING;
|
||||
end else begin
|
||||
transfer_sm_next <= WAIT;
|
||||
end
|
||||
end else if (dma_valid == 1'b0) begin
|
||||
transfer_sm_next <= IDLE;
|
||||
end
|
||||
end
|
||||
FLUSHING: begin
|
||||
transfer <= 1'b1;
|
||||
if (dma_valid == 1'b0) begin
|
||||
transfer_sm_next <= IDLE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
transfer_sm <= transfer_sm_next;
|
||||
end
|
||||
|
||||
assign flush_dma = transfer_sm_next == FLUSHING ? 1'b1 : raw_transfer_en & flush_dma_in;
|
||||
assign dma_ready = transfer_sm_next == TRANSFER ? dac_int_ready : flush_dma;
|
||||
assign underflow = dac_enable & dma_ready & ~dma_valid & !flush_dma;
|
||||
|
||||
assign dma_valid_ch = transfer | raw_transfer_en;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst == 1'b1) begin
|
||||
dma_valid_m <= 'd0;
|
||||
end else begin
|
||||
dma_valid_m <= {dma_valid_m[14:0], dma_valid_ch};
|
||||
end
|
||||
end
|
||||
|
||||
assign dac_valid_out = dma_valid_m[2];
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
case (filter_mask)
|
||||
3'b000: filter_enable <= 1'b0;
|
||||
default: filter_enable <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case (filter_enable)
|
||||
1'b0: dac_int_data = dac_data_corrected;
|
||||
default: dac_int_data = dac_cic_data[31:16];
|
||||
endcase
|
||||
|
||||
case (filter_mask)
|
||||
1'b0: dac_filt_int_valid = dac_valid_corrected & !dma_transfer_suspend;
|
||||
default: dac_filt_int_valid = dac_fir_valid;
|
||||
endcase
|
||||
|
||||
case (filter_mask)
|
||||
16'h1: interp_rate_cic = 16'd5;
|
||||
16'h2: interp_rate_cic = 16'd50;
|
||||
16'h3: interp_rate_cic = 16'd500;
|
||||
16'h6: interp_rate_cic = 16'd5000;
|
||||
16'h7: interp_rate_cic = 16'd50000;
|
||||
default: interp_rate_cic = 16'd1;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,32 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ip
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_dac_interpolate
|
||||
adi_ip_files axi_dac_interpolate [list \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/ad_iqcor.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"axi_dac_interpolate_constr.xdc" \
|
||||
"cic_interp.v" \
|
||||
"fir_interp.v" \
|
||||
"axi_dac_interpolate_reg.v" \
|
||||
"axi_dac_interpolate_filter.v" \
|
||||
"axi_dac_interpolate.v" ]
|
||||
|
||||
adi_ip_properties axi_dac_interpolate
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate} [ipx::current_core]
|
||||
|
||||
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,217 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_dac_interpolate_reg(
|
||||
|
||||
input clk,
|
||||
|
||||
output [31:0] dac_interpolation_ratio_a,
|
||||
output [ 2:0] dac_filter_mask_a,
|
||||
output [31:0] dac_interpolation_ratio_b,
|
||||
output [ 2:0] dac_filter_mask_b,
|
||||
output dma_transfer_suspend,
|
||||
output flush_dma_out,
|
||||
output [ 1:0] raw_transfer_en,
|
||||
output [15:0] dac_raw_ch_a_data,
|
||||
output [15:0] dac_raw_ch_b_data,
|
||||
output start_sync_channels,
|
||||
output stop_sync_channels,
|
||||
output dac_correction_enable_a,
|
||||
output dac_correction_enable_b,
|
||||
output [15:0] dac_correction_coefficient_a,
|
||||
output [15:0] dac_correction_coefficient_b,
|
||||
output [19:0] trigger_config,
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [ 4:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [ 4:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack
|
||||
);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [31:0] up_version = {16'h0002, /* MAJOR */
|
||||
8'h03, /* MINOR */
|
||||
8'h00}; /* PATCH */
|
||||
reg [31:0] up_scratch = 32'h0;
|
||||
|
||||
reg [31:0] up_interpolation_ratio_a = 32'h0;
|
||||
reg [ 2:0] up_filter_mask_a = 3'h0;
|
||||
reg [31:0] up_interpolation_ratio_b = 32'h0;
|
||||
reg [ 2:0] up_filter_mask_b = 3'h0;
|
||||
reg [ 5:0] up_flags = 6'ha;
|
||||
reg [ 1:0] up_config = 2'h0;
|
||||
reg [15:0] up_correction_coefficient_a = 16'h0;
|
||||
reg [15:0] up_correction_coefficient_b = 16'h0;
|
||||
reg [19:0] up_trigger_config = 20'h0;
|
||||
reg [15:0] up_dac_raw_ch_a_data;
|
||||
reg [15:0] up_dac_raw_ch_b_data;
|
||||
|
||||
wire [ 5:0] flags;
|
||||
|
||||
assign dma_transfer_suspend = flags[0];
|
||||
assign start_sync_channels = flags[1];
|
||||
assign stop_sync_channels = flags[2];
|
||||
assign flush_dma_out = flags[3];
|
||||
assign raw_transfer_en = flags[5:4]; //5-b; 4-a
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 'd0;
|
||||
up_scratch <= 'd0;
|
||||
up_interpolation_ratio_a <= 'd0;
|
||||
up_filter_mask_a <= 'd0;
|
||||
up_interpolation_ratio_b <= 'd0;
|
||||
up_filter_mask_b <= 'd0;
|
||||
up_flags <= 'ha;
|
||||
up_config <= 'd0;
|
||||
up_correction_coefficient_a <= 'd0;
|
||||
up_correction_coefficient_b <= 'd0;
|
||||
up_trigger_config <= 'd0;
|
||||
up_dac_raw_ch_a_data <= 16'd0;
|
||||
up_dac_raw_ch_b_data <= 16'd0;
|
||||
end else begin
|
||||
up_wack <= up_wreq;
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
|
||||
up_scratch <= up_wdata;
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
|
||||
up_interpolation_ratio_a <= up_wdata;
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
|
||||
up_filter_mask_a <= up_wdata[2:0];
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
|
||||
up_interpolation_ratio_b <= up_wdata;
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
|
||||
up_filter_mask_b <= up_wdata[2:0];
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
|
||||
up_flags <= up_wdata[5:0];
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin
|
||||
up_config <= up_wdata[1:0];
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h16)) begin
|
||||
up_correction_coefficient_a <= up_wdata[15:0];
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h17)) begin
|
||||
up_correction_coefficient_b <= up_wdata[15:0];
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h18)) begin
|
||||
up_trigger_config <= up_wdata[19:0];
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h19)) begin
|
||||
up_dac_raw_ch_a_data <= up_wdata[15:0];
|
||||
up_dac_raw_ch_b_data <= up_wdata[31:16];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_rack <= up_rreq;
|
||||
if (up_rreq == 1'b1) begin
|
||||
case (up_raddr[4:0])
|
||||
5'h0: up_rdata <= up_version;
|
||||
5'h1: up_rdata <= up_scratch;
|
||||
5'h10: up_rdata <= up_interpolation_ratio_a;
|
||||
5'h11: up_rdata <= {29'h0,up_filter_mask_a};
|
||||
5'h12: up_rdata <= up_interpolation_ratio_b;
|
||||
5'h13: up_rdata <= {29'h0,up_filter_mask_b};
|
||||
5'h14: up_rdata <= {26'h0,up_flags};
|
||||
5'h15: up_rdata <= {30'h0,up_config};
|
||||
5'h16: up_rdata <= {16'h0,up_correction_coefficient_a};
|
||||
5'h17: up_rdata <= {16'h0,up_correction_coefficient_b};
|
||||
5'h18: up_rdata <= {12'h0,up_trigger_config};
|
||||
5'h19: up_rdata <= {up_dac_raw_ch_b_data, up_dac_raw_ch_a_data};
|
||||
default: up_rdata <= 0;
|
||||
endcase
|
||||
end else begin
|
||||
up_rdata <= 32'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
up_xfer_cntrl #(
|
||||
.DATA_WIDTH(162)
|
||||
) i_xfer_cntrl (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_data_cntrl ({ up_config[1], // 1
|
||||
up_config[0], // 1
|
||||
up_correction_coefficient_b,// 16
|
||||
up_correction_coefficient_a,// 16
|
||||
up_trigger_config, // 20
|
||||
up_flags, // 6
|
||||
up_dac_raw_ch_a_data, // 16
|
||||
up_dac_raw_ch_b_data, // 16
|
||||
up_interpolation_ratio_b, // 32
|
||||
up_interpolation_ratio_a, // 32
|
||||
up_filter_mask_b, // 3
|
||||
up_filter_mask_a}), // 3
|
||||
|
||||
.up_xfer_done (),
|
||||
.d_rst (1'b0),
|
||||
.d_clk (clk),
|
||||
.d_data_cntrl ({ dac_correction_enable_b, // 1
|
||||
dac_correction_enable_a, // 1
|
||||
dac_correction_coefficient_b, // 16
|
||||
dac_correction_coefficient_a, // 16
|
||||
trigger_config, // 20
|
||||
flags, // 6
|
||||
dac_raw_ch_a_data, // 16
|
||||
dac_raw_ch_b_data, // 16
|
||||
dac_interpolation_ratio_b, // 32
|
||||
dac_interpolation_ratio_a, // 32
|
||||
dac_filter_mask_b, // 3
|
||||
dac_filter_mask_a})); // 3
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,604 @@
|
||||
// -------------------------------------------------------------
|
||||
//
|
||||
// Module: cic_interp
|
||||
// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
|
||||
// Generated on: 2016-07-05 11:08:04
|
||||
// -------------------------------------------------------------
|
||||
|
||||
// -------------------------------------------------------------
|
||||
// HDL Code Generation Options:
|
||||
//
|
||||
// OptimizeForHDL: on
|
||||
// EDAScriptGeneration: off
|
||||
// AddPipelineRegisters: on
|
||||
// Name: cic_interp
|
||||
// AddRatePort: on
|
||||
// InputDataType: numerictype(1,31,30)
|
||||
// TargetLanguage: Verilog
|
||||
// TestBenchName: cicinterpfilt_copy_tb
|
||||
// TestBenchStimulus: step ramp chirp noise
|
||||
// GenerateHDLTestBench: off
|
||||
|
||||
// -------------------------------------------------------------
|
||||
// HDL Implementation : Fully parallel
|
||||
// -------------------------------------------------------------
|
||||
// Filter Settings:
|
||||
//
|
||||
// Discrete-Time FIR Multirate Filter (real)
|
||||
// -----------------------------------------
|
||||
// Filter Structure : Cascaded Integrator-Comb Interpolator
|
||||
// Interpolation Factor : 50000
|
||||
// Differential Delay : 1
|
||||
// Number of Sections : 6
|
||||
// Stable : Yes
|
||||
// Linear Phase : No
|
||||
//
|
||||
// -------------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module cic_interp (
|
||||
input clk,
|
||||
input clk_enable,
|
||||
input reset,
|
||||
input signed [30:0] filter_in, //sfix31_En30
|
||||
input [15:0] rate, //ufix16
|
||||
input load_rate,
|
||||
output signed [109:0] filter_out, //sfix110_En30
|
||||
output ce_out
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
//Module Architecture: cic_interp
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Local Functions
|
||||
// Type Definitions
|
||||
// Constants
|
||||
parameter signed [35:0] zeroconst = 36'h000000000; //sfix36_En30
|
||||
// Signals
|
||||
wire [15:0] rate_unsigned; // ufix16
|
||||
reg [15:0] cur_count = 0; // ufix16
|
||||
wire phase_0; // boolean
|
||||
//
|
||||
reg signed [30:0] input_register = 0; // sfix31_En30
|
||||
// -- Section 1 Signals
|
||||
wire signed [30:0] section_in1; // sfix31_En30
|
||||
wire signed [31:0] section_cast1; // sfix32_En30
|
||||
reg signed [31:0] diff1 = 0; // sfix32_En30
|
||||
wire signed [31:0] section_out1; // sfix32_En30
|
||||
wire signed [31:0] sub_cast; // sfix32_En30
|
||||
wire signed [31:0] sub_cast_1; // sfix32_En30
|
||||
wire signed [32:0] sub_temp; // sfix33_En30
|
||||
reg signed [31:0] cic_pipeline1 = 0; // sfix32_En30
|
||||
// -- Section 2 Signals
|
||||
wire signed [31:0] section_in2; // sfix32_En30
|
||||
wire signed [32:0] section_cast2; // sfix33_En30
|
||||
reg signed [32:0] diff2 = 0; // sfix33_En30
|
||||
wire signed [32:0] section_out2; // sfix33_En30
|
||||
wire signed [32:0] sub_cast_2; // sfix33_En30
|
||||
wire signed [32:0] sub_cast_3; // sfix33_En30
|
||||
wire signed [33:0] sub_temp_1; // sfix34_En30
|
||||
reg signed [32:0] cic_pipeline2 = 0; // sfix33_En30
|
||||
// -- Section 3 Signals
|
||||
wire signed [32:0] section_in3; // sfix33_En30
|
||||
wire signed [33:0] section_cast3; // sfix34_En30
|
||||
reg signed [33:0] diff3 = 0; // sfix34_En30
|
||||
wire signed [33:0] section_out3; // sfix34_En30
|
||||
wire signed [33:0] sub_cast_4; // sfix34_En30
|
||||
wire signed [33:0] sub_cast_5; // sfix34_En30
|
||||
wire signed [34:0] sub_temp_2; // sfix35_En30
|
||||
reg signed [33:0] cic_pipeline3 = 0; // sfix34_En30
|
||||
// -- Section 4 Signals
|
||||
wire signed [33:0] section_in4; // sfix34_En30
|
||||
wire signed [34:0] section_cast4; // sfix35_En30
|
||||
reg signed [34:0] diff4 = 0; // sfix35_En30
|
||||
wire signed [34:0] section_out4; // sfix35_En30
|
||||
wire signed [34:0] sub_cast_6; // sfix35_En30
|
||||
wire signed [34:0] sub_cast_7; // sfix35_En30
|
||||
wire signed [35:0] sub_temp_3; // sfix36_En30
|
||||
reg signed [34:0] cic_pipeline4 = 0; // sfix35_En30
|
||||
// -- Section 5 Signals
|
||||
wire signed [34:0] section_in5; // sfix35_En30
|
||||
wire signed [35:0] section_cast5; // sfix36_En30
|
||||
reg signed [35:0] diff5 = 0; // sfix36_En30
|
||||
wire signed [35:0] section_out5; // sfix36_En30
|
||||
wire signed [35:0] sub_cast_8; // sfix36_En30
|
||||
wire signed [35:0] sub_cast_9; // sfix36_En30
|
||||
wire signed [36:0] sub_temp_4; // sfix37_En30
|
||||
reg signed [35:0] cic_pipeline5 = 0; // sfix36_En30
|
||||
// -- Section 6 Signals
|
||||
wire signed [35:0] section_in6; // sfix36_En30
|
||||
reg signed [35:0] diff6 = 0; // sfix36_En30
|
||||
wire signed [35:0] section_out6; // sfix36_En30
|
||||
wire signed [35:0] sub_cast_10; // sfix36_En30
|
||||
wire signed [35:0] sub_cast_11; // sfix36_En30
|
||||
wire signed [36:0] sub_temp_5; // sfix37_En30
|
||||
reg signed [35:0] cic_pipeline6 = 0; // sfix36_En30
|
||||
wire signed [35:0] upsampling; // sfix36_En30
|
||||
// -- Section 7 Signals
|
||||
wire signed [35:0] section_in7; // sfix36_En30
|
||||
wire signed [35:0] sum1; // sfix36_En30
|
||||
reg signed [35:0] section_out7 = 0; // sfix36_En30
|
||||
wire signed [35:0] add_cast; // sfix36_En30
|
||||
wire signed [35:0] add_cast_1; // sfix36_En30
|
||||
wire signed [36:0] add_temp; // sfix37_En30
|
||||
// -- Section 8 Signals
|
||||
wire signed [35:0] section_in8; // sfix36_En30
|
||||
wire signed [50:0] section_cast8; // sfix51_En30
|
||||
wire signed [50:0] sum2; // sfix51_En30
|
||||
reg signed [50:0] section_out8 = 0; // sfix51_En30
|
||||
wire signed [50:0] add_cast_2; // sfix51_En30
|
||||
wire signed [50:0] add_cast_3; // sfix51_En30
|
||||
wire signed [51:0] add_temp_1; // sfix52_En30
|
||||
// -- Section 9 Signals
|
||||
wire signed [50:0] section_in9; // sfix51_En30
|
||||
wire signed [65:0] section_cast9; // sfix66_En30
|
||||
wire signed [65:0] sum3; // sfix66_En30
|
||||
reg signed [65:0] section_out9 = 0; // sfix66_En30
|
||||
wire signed [65:0] add_cast_4; // sfix66_En30
|
||||
wire signed [65:0] add_cast_5; // sfix66_En30
|
||||
wire signed [66:0] add_temp_2; // sfix67_En30
|
||||
// -- Section 10 Signals
|
||||
wire signed [65:0] section_in10; // sfix66_En30
|
||||
wire signed [79:0] section_cast10; // sfix80_En30
|
||||
wire signed [79:0] sum4; // sfix80_En30
|
||||
reg signed [79:0] section_out10 = 0; // sfix80_En30
|
||||
wire signed [79:0] add_cast_6; // sfix80_En30
|
||||
wire signed [79:0] add_cast_7; // sfix80_En30
|
||||
wire signed [80:0] add_temp_3; // sfix81_En30
|
||||
// -- Section 11 Signals
|
||||
wire signed [79:0] section_in11; // sfix80_En30
|
||||
wire signed [94:0] section_cast11; // sfix95_En30
|
||||
wire signed [94:0] sum5; // sfix95_En30
|
||||
reg signed [94:0] section_out11 = 0; // sfix95_En30
|
||||
wire signed [94:0] add_cast_8; // sfix95_En30
|
||||
wire signed [94:0] add_cast_9; // sfix95_En30
|
||||
wire signed [95:0] add_temp_4; // sfix96_En30
|
||||
// -- Section 12 Signals
|
||||
wire signed [94:0] section_in12; // sfix95_En30
|
||||
wire signed [109:0] section_cast12; // sfix110_En30
|
||||
wire signed [109:0] sum6; // sfix110_En30
|
||||
reg signed [109:0] section_out12 = 0; // sfix110_En30
|
||||
wire signed [109:0] add_cast_10; // sfix110_En30
|
||||
wire signed [109:0] add_cast_11; // sfix110_En30
|
||||
wire signed [110:0] add_temp_5; // sfix111_En30
|
||||
reg [6:0] bitgain = 0; // ufix7
|
||||
wire signed [109:0] output_typeconvert; // sfix110_En30
|
||||
wire signed [109:0] muxinput_14; // sfix110_En16
|
||||
wire signed [109:0] muxinput_34; // sfix110_E4
|
||||
wire signed [109:0] muxinput_54; // sfix110_E24
|
||||
wire signed [109:0] muxinput_74; // sfix110_E44
|
||||
wire signed [109:0] muxinput_94; // sfix110_E64
|
||||
//
|
||||
reg signed [109:0] output_register = 0; // sfix110_En30
|
||||
|
||||
// Block Statements
|
||||
assign rate_unsigned = rate;
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: ce_output
|
||||
if (reset == 1'b1) begin
|
||||
cur_count <= 16'b0000000000000000;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
if (load_rate == 1'b1) begin
|
||||
cur_count <= 16'b0000000000000001;
|
||||
end
|
||||
else if (cur_count == rate_unsigned - 1) begin
|
||||
cur_count <= 16'b0000000000000000;
|
||||
end
|
||||
else begin
|
||||
cur_count <= cur_count + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // ce_output
|
||||
|
||||
assign phase_0 = (cur_count == 16'b0000000000000000 && clk_enable == 1'b1)? 1 : 0;
|
||||
|
||||
// ------------------ Input Register ------------------
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: input_reg_process
|
||||
if (reset == 1'b1) begin
|
||||
input_register <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
input_register <= filter_in;
|
||||
end
|
||||
end
|
||||
end // input_reg_process
|
||||
|
||||
// ------------------ Section # 1 : Comb ------------------
|
||||
|
||||
assign section_in1 = input_register;
|
||||
|
||||
assign section_cast1 = $signed({{1{section_in1[30]}}, section_in1});
|
||||
|
||||
assign sub_cast = section_cast1;
|
||||
assign sub_cast_1 = diff1;
|
||||
assign sub_temp = sub_cast - sub_cast_1;
|
||||
assign section_out1 = sub_temp[31:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section1
|
||||
if (reset == 1'b1) begin
|
||||
diff1 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
diff1 <= section_cast1;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section1
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section1
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline1 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
cic_pipeline1 <= section_out1;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section1
|
||||
|
||||
// ------------------ Section # 2 : Comb ------------------
|
||||
|
||||
assign section_in2 = cic_pipeline1;
|
||||
|
||||
assign section_cast2 = $signed({{1{section_in2[31]}}, section_in2});
|
||||
|
||||
assign sub_cast_2 = section_cast2;
|
||||
assign sub_cast_3 = diff2;
|
||||
assign sub_temp_1 = sub_cast_2 - sub_cast_3;
|
||||
assign section_out2 = sub_temp_1[32:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section2
|
||||
if (reset == 1'b1) begin
|
||||
diff2 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
diff2 <= section_cast2;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section2
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section2
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline2 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
cic_pipeline2 <= section_out2;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section2
|
||||
|
||||
// ------------------ Section # 3 : Comb ------------------
|
||||
|
||||
assign section_in3 = cic_pipeline2;
|
||||
|
||||
assign section_cast3 = $signed({{1{section_in3[32]}}, section_in3});
|
||||
|
||||
assign sub_cast_4 = section_cast3;
|
||||
assign sub_cast_5 = diff3;
|
||||
assign sub_temp_2 = sub_cast_4 - sub_cast_5;
|
||||
assign section_out3 = sub_temp_2[33:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section3
|
||||
if (reset == 1'b1) begin
|
||||
diff3 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
diff3 <= section_cast3;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section3
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section3
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline3 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
cic_pipeline3 <= section_out3;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section3
|
||||
|
||||
// ------------------ Section # 4 : Comb ------------------
|
||||
|
||||
assign section_in4 = cic_pipeline3;
|
||||
|
||||
assign section_cast4 = $signed({{1{section_in4[33]}}, section_in4});
|
||||
|
||||
assign sub_cast_6 = section_cast4;
|
||||
assign sub_cast_7 = diff4;
|
||||
assign sub_temp_3 = sub_cast_6 - sub_cast_7;
|
||||
assign section_out4 = sub_temp_3[34:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section4
|
||||
if (reset == 1'b1) begin
|
||||
diff4 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
diff4 <= section_cast4;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section4
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section4
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline4 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
cic_pipeline4 <= section_out4;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section4
|
||||
|
||||
// ------------------ Section # 5 : Comb ------------------
|
||||
|
||||
assign section_in5 = cic_pipeline4;
|
||||
|
||||
assign section_cast5 = $signed({{1{section_in5[34]}}, section_in5});
|
||||
|
||||
assign sub_cast_8 = section_cast5;
|
||||
assign sub_cast_9 = diff5;
|
||||
assign sub_temp_4 = sub_cast_8 - sub_cast_9;
|
||||
assign section_out5 = sub_temp_4[35:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section5
|
||||
if (reset == 1'b1) begin
|
||||
diff5 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
diff5 <= section_cast5;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section5
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section5
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline5 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
cic_pipeline5 <= section_out5;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section5
|
||||
|
||||
// ------------------ Section # 6 : Comb ------------------
|
||||
|
||||
assign section_in6 = cic_pipeline5;
|
||||
|
||||
assign sub_cast_10 = section_in6;
|
||||
assign sub_cast_11 = diff6;
|
||||
assign sub_temp_5 = sub_cast_10 - sub_cast_11;
|
||||
assign section_out6 = sub_temp_5[35:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section6
|
||||
if (reset == 1'b1) begin
|
||||
diff6 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
diff6 <= section_in6;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section6
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section6
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline6 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
cic_pipeline6 <= section_out6;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section6
|
||||
|
||||
assign upsampling = (phase_0 == 1'b1) ? cic_pipeline6 :
|
||||
zeroconst;
|
||||
// ------------------ Section # 7 : Integrator ------------------
|
||||
|
||||
assign section_in7 = upsampling;
|
||||
|
||||
assign add_cast = section_in7;
|
||||
assign add_cast_1 = section_out7;
|
||||
assign add_temp = add_cast + add_cast_1;
|
||||
assign sum1 = add_temp[35:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section7
|
||||
if (reset == 1'b1) begin
|
||||
section_out7 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out7 <= sum1;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section7
|
||||
|
||||
// ------------------ Section # 8 : Integrator ------------------
|
||||
|
||||
assign section_in8 = section_out7;
|
||||
|
||||
assign section_cast8 = $signed({{15{section_in8[35]}}, section_in8});
|
||||
|
||||
assign add_cast_2 = section_cast8;
|
||||
assign add_cast_3 = section_out8;
|
||||
assign add_temp_1 = add_cast_2 + add_cast_3;
|
||||
assign sum2 = add_temp_1[50:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section8
|
||||
if (reset == 1'b1) begin
|
||||
section_out8 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out8 <= sum2;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section8
|
||||
|
||||
// ------------------ Section # 9 : Integrator ------------------
|
||||
|
||||
assign section_in9 = section_out8;
|
||||
|
||||
assign section_cast9 = $signed({{15{section_in9[50]}}, section_in9});
|
||||
|
||||
assign add_cast_4 = section_cast9;
|
||||
assign add_cast_5 = section_out9;
|
||||
assign add_temp_2 = add_cast_4 + add_cast_5;
|
||||
assign sum3 = add_temp_2[65:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section9
|
||||
if (reset == 1'b1) begin
|
||||
section_out9 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out9 <= sum3;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section9
|
||||
|
||||
// ------------------ Section # 10 : Integrator ------------------
|
||||
|
||||
assign section_in10 = section_out9;
|
||||
|
||||
assign section_cast10 = $signed({{14{section_in10[65]}}, section_in10});
|
||||
|
||||
assign add_cast_6 = section_cast10;
|
||||
assign add_cast_7 = section_out10;
|
||||
assign add_temp_3 = add_cast_6 + add_cast_7;
|
||||
assign sum4 = add_temp_3[79:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section10
|
||||
if (reset == 1'b1) begin
|
||||
section_out10 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out10 <= sum4;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section10
|
||||
|
||||
// ------------------ Section # 11 : Integrator ------------------
|
||||
|
||||
assign section_in11 = section_out10;
|
||||
|
||||
assign section_cast11 = $signed({{15{section_in11[79]}}, section_in11});
|
||||
|
||||
assign add_cast_8 = section_cast11;
|
||||
assign add_cast_9 = section_out11;
|
||||
assign add_temp_4 = add_cast_8 + add_cast_9;
|
||||
assign sum5 = add_temp_4[94:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section11
|
||||
if (reset == 1'b1) begin
|
||||
section_out11 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out11 <= sum5;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section11
|
||||
|
||||
// ------------------ Section # 12 : Integrator ------------------
|
||||
|
||||
assign section_in12 = section_out11;
|
||||
|
||||
assign section_cast12 = $signed({{15{section_in12[94]}}, section_in12});
|
||||
|
||||
assign add_cast_10 = section_cast12;
|
||||
assign add_cast_11 = section_out12;
|
||||
assign add_temp_5 = add_cast_10 + add_cast_11;
|
||||
assign sum6 = add_temp_5[109:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section12
|
||||
if (reset == 1'b1) begin
|
||||
section_out12 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out12 <= sum6;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section12
|
||||
|
||||
always @(rate_unsigned)
|
||||
begin
|
||||
case(rate_unsigned)
|
||||
16'b0000000000000101 : bitgain = 7'b0001110;
|
||||
16'b0000000000110010 : bitgain = 7'b0100010;
|
||||
16'b0000000111110100 : bitgain = 7'b0110110;
|
||||
16'b0001001110001000 : bitgain = 7'b1001010;
|
||||
16'b1100001101010000 : bitgain = 7'b1011110;
|
||||
default : bitgain = 7'b1011110;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign muxinput_14 = $signed({{10{section_out12[109]}}, section_out12[109:10]});
|
||||
|
||||
assign muxinput_34 = $signed({{27{section_out12[109]}}, section_out12[109:27]});
|
||||
|
||||
assign muxinput_54 = $signed({{43{section_out12[109]}}, section_out12[109:43]});
|
||||
|
||||
assign muxinput_74 = $signed({{60{section_out12[109]}}, section_out12[109:60]});
|
||||
|
||||
assign muxinput_94 = $signed({{77{section_out12[109]}}, section_out12[109:77]});
|
||||
|
||||
assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 :
|
||||
(bitgain == 7'b0100010) ? muxinput_34 :
|
||||
(bitgain == 7'b0110110) ? muxinput_54 :
|
||||
(bitgain == 7'b1001010) ? muxinput_74 :
|
||||
muxinput_94;
|
||||
// ------------------ Output Register ------------------
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: output_reg_process
|
||||
if (reset == 1'b1) begin
|
||||
output_register <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
output_register <= output_typeconvert;
|
||||
end
|
||||
end
|
||||
end // output_reg_process
|
||||
|
||||
// Assignment Statements
|
||||
assign ce_out = phase_0;
|
||||
assign filter_out = output_register;
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,381 @@
|
||||
// -------------------------------------------------------------
|
||||
//
|
||||
// Module: fir_interp
|
||||
// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
|
||||
// Generated on: 2016-07-05 15:54:12
|
||||
// -------------------------------------------------------------
|
||||
|
||||
// -------------------------------------------------------------
|
||||
// HDL Code Generation Options:
|
||||
//
|
||||
// FIRAdderStyle: tree
|
||||
// OptimizeForHDL: on
|
||||
// EDAScriptGeneration: off
|
||||
// AddPipelineRegisters: on
|
||||
// Name: fir_interp
|
||||
// TargetLanguage: Verilog
|
||||
// TestBenchName: fo_copy_tb
|
||||
// TestBenchStimulus: step ramp chirp noise
|
||||
// GenerateHDLTestBench: off
|
||||
|
||||
// -------------------------------------------------------------
|
||||
// HDL Implementation : Fully parallel
|
||||
// Multipliers : 12
|
||||
// Folding Factor : 1
|
||||
// -------------------------------------------------------------
|
||||
// Filter Settings:
|
||||
//
|
||||
// Discrete-Time FIR Multirate Filter (real)
|
||||
// -----------------------------------------
|
||||
// Filter Structure : Direct-Form FIR Polyphase Interpolator
|
||||
// Interpolation Factor : 2
|
||||
// Polyphase Length : 12
|
||||
// Filter Length : 24
|
||||
// Stable : Yes
|
||||
// Linear Phase : Yes (Type 2)
|
||||
//
|
||||
// Arithmetic : fixed
|
||||
// Numerator : s16,15 -> [-1 1)
|
||||
// -------------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module fir_interp (
|
||||
input clk,
|
||||
input clk_enable,
|
||||
input reset,
|
||||
input signed [15:0] filter_in, //sfix16_En15
|
||||
output signed [35:0] filter_out, //sfix36_En30
|
||||
output ce_out
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
//Module Architecture: fir_interp
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Local Functions
|
||||
// Type Definitions
|
||||
// Constants
|
||||
parameter signed [15:0] coeffphase1_1 = 16'b1111111110101001; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_2 = 16'b1111111101111010; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_3 = 16'b0000010011111111; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_4 = 16'b1111101010101110; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_5 = 16'b1111001001101000; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_6 = 16'b0011011010110011; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_7 = 16'b0101011100111111; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_8 = 16'b0000110010011010; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_9 = 16'b1111000000000010; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_10 = 16'b0000001110101000; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_11 = 16'b0000000111110010; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase1_12 = 16'b1111111100011100; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_1 = 16'b1111111100011100; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_2 = 16'b0000000111110010; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_3 = 16'b0000001110101000; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_4 = 16'b1111000000000010; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_5 = 16'b0000110010011010; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_6 = 16'b0101011100111111; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_7 = 16'b0011011010110011; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_8 = 16'b1111001001101000; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_9 = 16'b1111101010101110; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_10 = 16'b0000010011111111; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_11 = 16'b1111111101111010; //sfix16_En15
|
||||
parameter signed [15:0] coeffphase2_12 = 16'b1111111110101001; //sfix16_En15
|
||||
|
||||
// Signals
|
||||
reg [1:0] cur_count = 0; // ufix2
|
||||
wire phase_1; // boolean
|
||||
reg signed [15:0] delay_pipeline [0:11]; // sfix16_En15
|
||||
wire signed [31:0] product; // sfix32_En30
|
||||
wire signed [15:0] product_mux; // sfix16_En15
|
||||
wire signed [31:0] product_1; // sfix32_En30
|
||||
wire signed [15:0] product_mux_1; // sfix16_En15
|
||||
wire signed [31:0] product_2; // sfix32_En30
|
||||
wire signed [15:0] product_mux_2; // sfix16_En15
|
||||
wire signed [31:0] product_3; // sfix32_En30
|
||||
wire signed [15:0] product_mux_3; // sfix16_En15
|
||||
wire signed [31:0] product_4; // sfix32_En30
|
||||
wire signed [15:0] product_mux_4; // sfix16_En15
|
||||
wire signed [31:0] product_5; // sfix32_En30
|
||||
wire signed [15:0] product_mux_5; // sfix16_En15
|
||||
wire signed [31:0] product_6; // sfix32_En30
|
||||
wire signed [15:0] product_mux_6; // sfix16_En15
|
||||
wire signed [31:0] product_7; // sfix32_En30
|
||||
wire signed [15:0] product_mux_7; // sfix16_En15
|
||||
wire signed [31:0] product_8; // sfix32_En30
|
||||
wire signed [15:0] product_mux_8; // sfix16_En15
|
||||
wire signed [31:0] product_9; // sfix32_En30
|
||||
wire signed [15:0] product_mux_9; // sfix16_En15
|
||||
wire signed [31:0] product_10; // sfix32_En30
|
||||
wire signed [15:0] product_mux_10; // sfix16_En15
|
||||
wire signed [31:0] product_11; // sfix32_En30
|
||||
wire signed [15:0] product_mux_11; // sfix16_En15
|
||||
wire signed [35:0] sumvector1 [0:5] ; // sfix36_En30
|
||||
wire signed [31:0] add_signext; // sfix32_En30
|
||||
wire signed [31:0] add_signext_1; // sfix32_En30
|
||||
wire signed [32:0] add_temp; // sfix33_En30
|
||||
wire signed [31:0] add_signext_2; // sfix32_En30
|
||||
wire signed [31:0] add_signext_3; // sfix32_En30
|
||||
wire signed [32:0] add_temp_1; // sfix33_En30
|
||||
wire signed [31:0] add_signext_4; // sfix32_En30
|
||||
wire signed [31:0] add_signext_5; // sfix32_En30
|
||||
wire signed [32:0] add_temp_2; // sfix33_En30
|
||||
wire signed [31:0] add_signext_6; // sfix32_En30
|
||||
wire signed [31:0] add_signext_7; // sfix32_En30
|
||||
wire signed [32:0] add_temp_3; // sfix33_En30
|
||||
wire signed [31:0] add_signext_8; // sfix32_En30
|
||||
wire signed [31:0] add_signext_9; // sfix32_En30
|
||||
wire signed [32:0] add_temp_4; // sfix33_En30
|
||||
wire signed [31:0] add_signext_10; // sfix32_En30
|
||||
wire signed [31:0] add_signext_11; // sfix32_En30
|
||||
wire signed [32:0] add_temp_5; // sfix33_En30
|
||||
reg signed [35:0] sumdelay_pipeline1 [0:5]; // sfix36_En30
|
||||
wire signed [35:0] sumvector2 [0:2] ; // sfix36_En30
|
||||
wire signed [35:0] add_signext_12; // sfix36_En30
|
||||
wire signed [35:0] add_signext_13; // sfix36_En30
|
||||
wire signed [36:0] add_temp_6; // sfix37_En30
|
||||
wire signed [35:0] add_signext_14; // sfix36_En30
|
||||
wire signed [35:0] add_signext_15; // sfix36_En30
|
||||
wire signed [36:0] add_temp_7; // sfix37_En30
|
||||
wire signed [35:0] add_signext_16; // sfix36_En30
|
||||
wire signed [35:0] add_signext_17; // sfix36_En30
|
||||
wire signed [36:0] add_temp_8; // sfix37_En30
|
||||
reg signed [35:0] sumdelay_pipeline2 [0:2]; // sfix36_En30
|
||||
wire signed [35:0] sumvector3 [0:1] ; // sfix36_En30
|
||||
wire signed [35:0] add_signext_18; // sfix36_En30
|
||||
wire signed [35:0] add_signext_19; // sfix36_En30
|
||||
wire signed [36:0] add_temp_9; // sfix37_En30
|
||||
reg signed [35:0] sumdelay_pipeline3 [0:1]; // sfix36_En30
|
||||
wire signed [35:0] sum4; // sfix36_En30
|
||||
wire signed [35:0] add_signext_20; // sfix36_En30
|
||||
wire signed [35:0] add_signext_21; // sfix36_En30
|
||||
wire signed [36:0] add_temp_10; // sfix37_En30
|
||||
reg signed [35:0] output_register = 0; // sfix36_En30
|
||||
|
||||
// Block Statements
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: ce_output
|
||||
if (reset == 1'b1) begin
|
||||
cur_count <= 2'b00;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
if (cur_count == 2'b01) begin
|
||||
cur_count <= 2'b00;
|
||||
end
|
||||
else begin
|
||||
cur_count <= cur_count + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // ce_output
|
||||
|
||||
assign phase_1 = (cur_count == 2'b01 && clk_enable == 1'b1)? 1 : 0;
|
||||
|
||||
// ---------------- Delay Registers ----------------
|
||||
|
||||
always @( posedge clk or posedge reset)
|
||||
begin: Delay_Pipeline_process
|
||||
if (reset == 1'b1) begin
|
||||
delay_pipeline[0] <= 0;
|
||||
delay_pipeline[1] <= 0;
|
||||
delay_pipeline[2] <= 0;
|
||||
delay_pipeline[3] <= 0;
|
||||
delay_pipeline[4] <= 0;
|
||||
delay_pipeline[5] <= 0;
|
||||
delay_pipeline[6] <= 0;
|
||||
delay_pipeline[7] <= 0;
|
||||
delay_pipeline[8] <= 0;
|
||||
delay_pipeline[9] <= 0;
|
||||
delay_pipeline[10] <= 0;
|
||||
delay_pipeline[11] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
delay_pipeline[0] <= filter_in;
|
||||
delay_pipeline[1] <= delay_pipeline[0];
|
||||
delay_pipeline[2] <= delay_pipeline[1];
|
||||
delay_pipeline[3] <= delay_pipeline[2];
|
||||
delay_pipeline[4] <= delay_pipeline[3];
|
||||
delay_pipeline[5] <= delay_pipeline[4];
|
||||
delay_pipeline[6] <= delay_pipeline[5];
|
||||
delay_pipeline[7] <= delay_pipeline[6];
|
||||
delay_pipeline[8] <= delay_pipeline[7];
|
||||
delay_pipeline[9] <= delay_pipeline[8];
|
||||
delay_pipeline[10] <= delay_pipeline[9];
|
||||
delay_pipeline[11] <= delay_pipeline[10];
|
||||
end
|
||||
end
|
||||
end // Delay_Pipeline_process
|
||||
|
||||
assign product_mux = (cur_count == 2'b00) ? coeffphase1_12 :
|
||||
coeffphase2_12;
|
||||
assign product = delay_pipeline[11] * product_mux;
|
||||
|
||||
assign product_mux_1 = (cur_count == 2'b00) ? coeffphase1_11 :
|
||||
coeffphase2_11;
|
||||
assign product_1 = delay_pipeline[10] * product_mux_1;
|
||||
|
||||
assign product_mux_2 = (cur_count == 2'b00) ? coeffphase1_10 :
|
||||
coeffphase2_10;
|
||||
assign product_2 = delay_pipeline[9] * product_mux_2;
|
||||
|
||||
assign product_mux_3 = (cur_count == 2'b00) ? coeffphase1_9 :
|
||||
coeffphase2_9;
|
||||
assign product_3 = delay_pipeline[8] * product_mux_3;
|
||||
|
||||
assign product_mux_4 = (cur_count == 2'b00) ? coeffphase1_8 :
|
||||
coeffphase2_8;
|
||||
assign product_4 = delay_pipeline[7] * product_mux_4;
|
||||
|
||||
assign product_mux_5 = (cur_count == 2'b00) ? coeffphase1_7 :
|
||||
coeffphase2_7;
|
||||
assign product_5 = delay_pipeline[6] * product_mux_5;
|
||||
|
||||
assign product_mux_6 = (cur_count == 2'b00) ? coeffphase1_6 :
|
||||
coeffphase2_6;
|
||||
assign product_6 = delay_pipeline[5] * product_mux_6;
|
||||
|
||||
assign product_mux_7 = (cur_count == 2'b00) ? coeffphase1_5 :
|
||||
coeffphase2_5;
|
||||
assign product_7 = delay_pipeline[4] * product_mux_7;
|
||||
|
||||
assign product_mux_8 = (cur_count == 2'b00) ? coeffphase1_4 :
|
||||
coeffphase2_4;
|
||||
assign product_8 = delay_pipeline[3] * product_mux_8;
|
||||
|
||||
assign product_mux_9 = (cur_count == 2'b00) ? coeffphase1_3 :
|
||||
coeffphase2_3;
|
||||
assign product_9 = delay_pipeline[2] * product_mux_9;
|
||||
|
||||
assign product_mux_10 = (cur_count == 2'b00) ? coeffphase1_2 :
|
||||
coeffphase2_2;
|
||||
assign product_10 = delay_pipeline[1] * product_mux_10;
|
||||
|
||||
assign product_mux_11 = (cur_count == 2'b00) ? coeffphase1_1 :
|
||||
coeffphase2_1;
|
||||
assign product_11 = delay_pipeline[0] * product_mux_11;
|
||||
|
||||
assign add_signext = product;
|
||||
assign add_signext_1 = product_1;
|
||||
assign add_temp = add_signext + add_signext_1;
|
||||
assign sumvector1[0] = $signed({{3{add_temp[32]}}, add_temp});
|
||||
|
||||
assign add_signext_2 = product_2;
|
||||
assign add_signext_3 = product_3;
|
||||
assign add_temp_1 = add_signext_2 + add_signext_3;
|
||||
assign sumvector1[1] = $signed({{3{add_temp_1[32]}}, add_temp_1});
|
||||
|
||||
assign add_signext_4 = product_4;
|
||||
assign add_signext_5 = product_5;
|
||||
assign add_temp_2 = add_signext_4 + add_signext_5;
|
||||
assign sumvector1[2] = $signed({{3{add_temp_2[32]}}, add_temp_2});
|
||||
|
||||
assign add_signext_6 = product_6;
|
||||
assign add_signext_7 = product_7;
|
||||
assign add_temp_3 = add_signext_6 + add_signext_7;
|
||||
assign sumvector1[3] = $signed({{3{add_temp_3[32]}}, add_temp_3});
|
||||
|
||||
assign add_signext_8 = product_8;
|
||||
assign add_signext_9 = product_9;
|
||||
assign add_temp_4 = add_signext_8 + add_signext_9;
|
||||
assign sumvector1[4] = $signed({{3{add_temp_4[32]}}, add_temp_4});
|
||||
|
||||
assign add_signext_10 = product_10;
|
||||
assign add_signext_11 = product_11;
|
||||
assign add_temp_5 = add_signext_10 + add_signext_11;
|
||||
assign sumvector1[5] = $signed({{3{add_temp_5[32]}}, add_temp_5});
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: sumdelay_pipeline_process1
|
||||
if (reset == 1'b1) begin
|
||||
sumdelay_pipeline1[0] <= 0;
|
||||
sumdelay_pipeline1[1] <= 0;
|
||||
sumdelay_pipeline1[2] <= 0;
|
||||
sumdelay_pipeline1[3] <= 0;
|
||||
sumdelay_pipeline1[4] <= 0;
|
||||
sumdelay_pipeline1[5] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
sumdelay_pipeline1[0] <= sumvector1[0];
|
||||
sumdelay_pipeline1[1] <= sumvector1[1];
|
||||
sumdelay_pipeline1[2] <= sumvector1[2];
|
||||
sumdelay_pipeline1[3] <= sumvector1[3];
|
||||
sumdelay_pipeline1[4] <= sumvector1[4];
|
||||
sumdelay_pipeline1[5] <= sumvector1[5];
|
||||
end
|
||||
end
|
||||
end // sumdelay_pipeline_process1
|
||||
|
||||
assign add_signext_12 = sumdelay_pipeline1[0];
|
||||
assign add_signext_13 = sumdelay_pipeline1[1];
|
||||
assign add_temp_6 = add_signext_12 + add_signext_13;
|
||||
assign sumvector2[0] = add_temp_6[35:0];
|
||||
|
||||
assign add_signext_14 = sumdelay_pipeline1[2];
|
||||
assign add_signext_15 = sumdelay_pipeline1[3];
|
||||
assign add_temp_7 = add_signext_14 + add_signext_15;
|
||||
assign sumvector2[1] = add_temp_7[35:0];
|
||||
|
||||
assign add_signext_16 = sumdelay_pipeline1[4];
|
||||
assign add_signext_17 = sumdelay_pipeline1[5];
|
||||
assign add_temp_8 = add_signext_16 + add_signext_17;
|
||||
assign sumvector2[2] = add_temp_8[35:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: sumdelay_pipeline_process2
|
||||
if (reset == 1'b1) begin
|
||||
sumdelay_pipeline2[0] <= 0;
|
||||
sumdelay_pipeline2[1] <= 0;
|
||||
sumdelay_pipeline2[2] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
sumdelay_pipeline2[0] <= sumvector2[0];
|
||||
sumdelay_pipeline2[1] <= sumvector2[1];
|
||||
sumdelay_pipeline2[2] <= sumvector2[2];
|
||||
end
|
||||
end
|
||||
end // sumdelay_pipeline_process2
|
||||
|
||||
assign add_signext_18 = sumdelay_pipeline2[0];
|
||||
assign add_signext_19 = sumdelay_pipeline2[1];
|
||||
assign add_temp_9 = add_signext_18 + add_signext_19;
|
||||
assign sumvector3[0] = add_temp_9[35:0];
|
||||
|
||||
assign sumvector3[1] = sumdelay_pipeline2[2];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: sumdelay_pipeline_process3
|
||||
if (reset == 1'b1) begin
|
||||
sumdelay_pipeline3[0] <= 0;
|
||||
sumdelay_pipeline3[1] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
sumdelay_pipeline3[0] <= sumvector3[0];
|
||||
sumdelay_pipeline3[1] <= sumvector3[1];
|
||||
end
|
||||
end
|
||||
end // sumdelay_pipeline_process3
|
||||
|
||||
assign add_signext_20 = sumdelay_pipeline3[0];
|
||||
assign add_signext_21 = sumdelay_pipeline3[1];
|
||||
assign add_temp_10 = add_signext_20 + add_signext_21;
|
||||
assign sum4 = add_temp_10[35:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: Output_Register_process
|
||||
if (reset == 1'b1) begin
|
||||
output_register <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
output_register <= sum4;
|
||||
end
|
||||
end
|
||||
end // Output_Register_process
|
||||
|
||||
// Assignment Statements
|
||||
assign ce_out = phase_1;
|
||||
assign filter_out = output_register;
|
||||
endmodule
|
||||
@@ -0,0 +1,43 @@
|
||||
clear all;
|
||||
close all;
|
||||
|
||||
interp_rate = 50000;
|
||||
|
||||
h_cic = dsp.CICInterpolator('InterpolationFactor', interp_rate, 'NumSections',6 );%, ...
|
||||
%'FixedPointDataType','Specify word and fraction lengths', ...
|
||||
%'SectionWordLengths', [12 20 28 35 43 51], ...
|
||||
%'SectionFractionLengths', [11 11 11 11 11 11], ...
|
||||
%'OutputWordLength', 12, ...
|
||||
%'OutputFractionLength', 11);
|
||||
|
||||
gainCIC = (h_cic.InterpolationFactor*h_cic.DifferentialDelay)^h_cic.NumSections
|
||||
[h1, w1] = h_cic.freqz();
|
||||
|
||||
fs = 1;
|
||||
fPass = 0.20;
|
||||
fStop = 0.50;
|
||||
ast = 70;
|
||||
prip = 0.05;
|
||||
CICCompInterp = dsp.CICCompensationInterpolator(h_cic, ...
|
||||
'InterpolationFactor',2,'PassbandFrequency',fPass, ...
|
||||
'StopbandFrequency',fStop,'StopbandAttenuation',ast, ...
|
||||
'SampleRate',fs);
|
||||
|
||||
[h2, w2] = CICCompInterp.freqz();
|
||||
CICCompInterp.coeffs()
|
||||
|
||||
FC = dsp.FilterCascade(CICCompInterp, h_cic);
|
||||
[h3, w3] = FC.freqz();
|
||||
|
||||
subplot(211); hold on;
|
||||
plot(w1/pi, 20*log10(abs(h1)/gainCIC));
|
||||
plot(w2/pi, 20*log10(abs(h2)));
|
||||
hold off; grid
|
||||
|
||||
subplot(212); plot(w3/pi, 20*log10(abs(h3)/gainCIC/sum(CICCompInterp.coeffs().Numerator))); grid
|
||||
|
||||
nt = numerictype(1,16,15);
|
||||
fdhdltool(CICCompInterp, nt);
|
||||
nt = numerictype(1,36,30);
|
||||
fdhdltool(h_cic,nt);
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "CORRECTION_DISABLE" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CORRECTION_DISABLE { PARAM_VALUE.CORRECTION_DISABLE } {
|
||||
# Procedure called to update CORRECTION_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CORRECTION_DISABLE { PARAM_VALUE.CORRECTION_DISABLE } {
|
||||
# Procedure called to validate CORRECTION_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.CORRECTION_DISABLE { MODELPARAM_VALUE.CORRECTION_DISABLE PARAM_VALUE.CORRECTION_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CORRECTION_DISABLE}] ${MODELPARAM_VALUE.CORRECTION_DISABLE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user