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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/axi_dmac/tb/axi_read_slave.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_read_slave #(
parameter DATA_WIDTH = 32,
parameter READ_ACCEPTANCE = 4,
parameter MIN_LATENCY = 48,
parameter MAX_LATENCY = 48
) (
input clk,
input reset,
input arvalid,
output arready,
input [31:0] araddr,
input [7:0] arlen,
input [2:0] arsize,
input [1:0] arburst,
input [2:0] arprot,
input [3:0] arcache,
output rvalid,
input rready,
output [DATA_WIDTH-1:0] rdata,
output [1:0] rresp,
output rlast
);
reg [DATA_WIDTH-1:0] data = 'h00;
wire [31:0] beat_addr;
assign rresp = 2'b00;
assign rdata = data;
always @(*) begin: gen_data
integer i;
for (i = 0; i < DATA_WIDTH; i = i + 8) begin
data[i+:8] <= beat_addr[7:0] + i / 8;
end
end
axi_slave #(
.DATA_WIDTH(DATA_WIDTH),
.ACCEPTANCE(READ_ACCEPTANCE),
.MIN_LATENCY(MIN_LATENCY),
.MAX_LATENCY(MAX_LATENCY)
) i_axi_slave (
.clk(clk),
.reset(reset),
.valid(arvalid),
.ready(arready),
.addr(araddr),
.len(arlen),
.size(arsize),
.burst(arburst),
.prot(arprot),
.cache(arcache),
.beat_stb(rvalid),
.beat_ack(rvalid & rready),
.beat_last(rlast),
.beat_addr(beat_addr));
endmodule
adi_library/axi_dmac/tb/axi_slave.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_slave #(
parameter DATA_WIDTH = 32,
parameter ACCEPTANCE = 3,
parameter MIN_LATENCY = 16,
parameter MAX_LATENCY = 32
) (
input clk,
input reset,
input valid,
output ready,
input [31:0] addr,
input [7:0] len,
input [2:0] size,
input [1:0] burst,
input [2:0] prot,
input [3:0] cache,
output beat_stb,
input beat_ack,
output [31:0] beat_addr,
output beat_last
);
reg [31:0] timestamp = 'h00;
always @(posedge clk) begin
if (reset == 1'b1) begin
timestamp <= 'h00;
end else begin
timestamp <= timestamp + 1'b1;
end
end
reg [32+32+8-1:0] req_fifo[0:15];
reg [3:0] req_fifo_rd = 'h00;
reg [3:0] req_fifo_wr = 'h00;
wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd;
assign ready = req_fifo_level < ACCEPTANCE;
always @(posedge clk) begin
if (reset == 1'b1) begin
req_fifo_wr <= 'h00;
end else begin
if (valid == 1'b1 && ready == 1'b1) begin
req_fifo[req_fifo_wr][71:40] <= timestamp + {$random} % (MAX_LATENCY - MIN_LATENCY + 1) + MIN_LATENCY;
req_fifo[req_fifo_wr][39:0] <= {addr,len};
req_fifo_wr <= req_fifo_wr + 1'b1;
end
end
end
reg [7:0] beat_counter = 'h00;
assign beat_stb = req_fifo_level != 0 && timestamp > req_fifo[req_fifo_rd][71:40];
assign beat_last = beat_stb ? beat_counter == req_fifo[req_fifo_rd][0+:8] : 1'b0;
assign beat_addr = req_fifo[req_fifo_rd][8+:32] + beat_counter * DATA_WIDTH / 8;
always @(posedge clk) begin
if (reset == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= 'h00;
end else begin
if (beat_ack == 1'b1) begin
if (beat_last == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= req_fifo_rd + 1'b1;
end else begin
beat_counter <= beat_counter + 1'b1;
end
end
end
end
endmodule
adi_library/axi_dmac/tb/axi_write_slave.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_write_slave #(
parameter DATA_WIDTH = 32,
parameter WRITE_ACCEPTANCE = 3
) (
input clk,
input reset,
input awvalid,
output awready,
input [31:0] awaddr,
input [7:0] awlen,
input [2:0] awsize,
input [1:0] awburst,
input [2:0] awprot,
input [3:0] awcache,
input wvalid,
output wready,
input [DATA_WIDTH-1:0] wdata,
input [DATA_WIDTH/8-1:0] wstrb,
input wlast,
output reg bvalid,
input bready,
output [1:0] bresp
);
wire beat_last;
axi_slave #(
.ACCEPTANCE(WRITE_ACCEPTANCE)
) i_axi_slave (
.clk(clk),
.reset(reset),
.valid(awvalid),
.ready(awready),
.addr(awaddr),
.len(awlen),
.size(awsize),
.burst(awburst),
.prot(awprot),
.cache(awcache),
.beat_stb(wready),
.beat_ack(wvalid & wready),
.beat_last(beat_last));
reg [4:0] resp_count = 'h00;
wire [4:0] resp_count_next;
reg [DATA_WIDTH-1:0] data_cmp = 'h00;
reg failed = 'b0;
assign bresp = 2'b00;
wire resp_count_dec = bvalid & bready;
wire resp_count_inc = wvalid & wready & beat_last;
assign resp_count_next = resp_count - resp_count_dec + resp_count_inc;
always @(posedge clk) begin
if (reset == 1'b1) begin
resp_count <= 'h00;
end else begin
resp_count <= resp_count - resp_count_dec + resp_count_inc;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
bvalid <= 1'b0;
end else if (bvalid == 1'b0 || bready == 1'b1) begin
if (resp_count_next != 'h00) begin
bvalid <= {$random} % 4 == 0;
end else begin
bvalid <= 1'b0;
end
end
end
integer byte_count;
always @(*) begin: count
integer i;
byte_count = 0;
for (i = 0; i < DATA_WIDTH / 8; i = i + 1) begin
byte_count = byte_count + wstrb[i];
end
end
always @(posedge clk) begin: gen_data_cmp
integer i;
if (reset) begin
for (i = 0; i < DATA_WIDTH; i = i + 8) begin
data_cmp[i+:8] <= i/8;
end
failed <= 'b0;
end else if (wvalid & wready) begin
for (i = 0; i < DATA_WIDTH; i = i + 8) begin
if (data_cmp[i+:8] !== wdata[i+:8] && wstrb[i/8] == 1'b1) begin
failed <= 1'b1;
end
data_cmp[i+:8] <= data_cmp[i+:8] + byte_count;
end
end
end
endmodule
adi_library/axi_dmac/tb/dma_read_shutdown_tb
Executable
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#!/bin/bash
SOURCE="$0.v"
SOURCE+=" axi_read_slave.v axi_slave.v"
SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../dmac_2d_transfer.v"
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"
SOURCE+=" ../dest_fifo_inf.v"
SOURCE+=" ../axi_dmac_response_manager.v"
SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
SOURCE+=" ../../util_cdc/sync_event.v"
SOURCE+=" ../../common/ad_mem_asym.v"
cd `dirname $0`
source ../../common/tb/run_tb.sh
adi_library/axi_dmac/tb/dma_read_shutdown_tb.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dma_read_shutdown_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`include "tb_base.v"
localparam TRANSFER_ADDR = 32'h80000000;
localparam TRANSFER_LEN = 24'h2ff;
reg fifo_clk = 1'b0;
wire awvalid;
wire awready;
wire [31:0] araddr;
wire [7:0] arlen;
wire [2:0] arsize;
wire [1:0] arburst;
wire [2:0] arprot;
wire [3:0] arcache;
wire rlast;
wire rvalid;
wire rready;
wire [1:0] rresp;
wire [31:0] rdata;
/* Twice as fast as the AXI clk so we have lots of read requests */
always @(*) #5 fifo_clk <= ~fifo_clk;
axi_read_slave #(
.DATA_WIDTH(32)
) i_read_slave (
.clk(clk),
.reset(reset),
.arvalid(arvalid),
.arready(arready),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arprot(arprot),
.arcache(arcache),
.rready(rready),
.rvalid(rvalid),
.rdata(rdata),
.rresp(rresp),
.rlast(rlast));
wire [11:0] dbg_status;
reg ctrl_enable = 1'b0;
initial begin
#1000
@(posedge clk) ctrl_enable <= 1'b1;
#3000
@(posedge clk) ctrl_enable <= 1'b0;
end
always @(posedge clk) begin
/*
* When disabled the DMA should eventually end up in an idle state and all
* requests that were sent out need to be accepted
*/
failed <= ctrl_enable == 1'b0 && (
dbg_status !== 12'h701 ||
i_read_slave.i_axi_slave.req_fifo_level !== 'h00);
end
axi_dmac_transfer #(
.DMA_TYPE_SRC(0),
.DMA_TYPE_DEST(2),
.DMA_DATA_WIDTH_SRC(32),
.DMA_DATA_WIDTH_DEST(32),
.FIFO_SIZE(8),
.DMA_LENGTH_ALIGN(2)
) i_transfer (
.m_src_axi_aclk (clk),
.m_src_axi_aresetn(resetn),
.m_axi_arvalid(arvalid),
.m_axi_arready(arready),
.m_axi_araddr(araddr),
.m_axi_arlen(arlen),
.m_axi_arsize(arsize),
.m_axi_arburst(arburst),
.m_axi_arprot(arprot),
.m_axi_arcache(arcache),
.m_axi_rready(rready),
.m_axi_rvalid(rvalid),
.m_axi_rdata(rdata),
.m_axi_rlast(rlast),
.m_axi_rresp(rresp),
.ctrl_clk(clk),
.ctrl_resetn(resetn),
.ctrl_enable(ctrl_enable),
.ctrl_pause(1'b0),
.req_eot(),
.req_valid(1'b1),
.req_ready(),
.req_dest_address(TRANSFER_ADDR[31:2]),
.req_src_address(TRANSFER_ADDR[31:2]),
.req_x_length(TRANSFER_LEN),
.req_y_length(24'h00),
.req_dest_stride(24'h00),
.req_src_stride(24'h00),
.req_sync_transfer_start(1'b0),
.req_last(1'b0),
.fifo_rd_clk(fifo_clk),
.fifo_rd_en(1'b1),
.fifo_rd_valid(),
.fifo_rd_underflow(),
.fifo_rd_dout(),
.dbg_status(dbg_status));
endmodule
adi_library/axi_dmac/tb/dma_read_tb
Executable
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#!/bin/bash
SOURCE="dma_read_tb.v"
SOURCE+=" axi_read_slave.v axi_slave.v"
SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"
SOURCE+=" ../dest_fifo_inf.v"
SOURCE+=" ../axi_dmac_response_manager.v"
SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
SOURCE+=" ../../util_cdc/sync_event.v"
SOURCE+=" ../../common/ad_mem_asym.v"
cd `dirname $0`
source ../../common/tb/run_tb.sh
adi_library/axi_dmac/tb/dma_read_tb.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dma_read_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
parameter WIDTH_DEST = 32;
parameter WIDTH_SRC = 32;
parameter REQ_LEN_INC = 4;
parameter REQ_LEN_INIT = 4;
`include "tb_base.v"
localparam TRANSFER_ADDR = 32'h80000000;
reg req_valid = 1'b1;
wire req_ready;
reg [23:0] req_length = REQ_LEN_INIT - 1;
wire awvalid;
wire awready;
wire [31:0] araddr;
wire [7:0] arlen;
wire [2:0] arsize;
wire [1:0] arburst;
wire [2:0] arprot;
wire [3:0] arcache;
wire rlast;
wire rvalid;
wire rready;
wire [1:0] rresp;
wire [WIDTH_SRC-1:0] rdata;
always @(posedge clk) begin
if (reset != 1'b1 && req_ready == 1'b1) begin
req_valid <= 1'b1;
req_length <= req_length + REQ_LEN_INC;
end
end
axi_read_slave #(
.DATA_WIDTH(WIDTH_SRC)
) i_read_slave (
.clk(clk),
.reset(reset),
.arvalid(arvalid),
.arready(arready),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arprot(arprot),
.arcache(arcache),
.rready(rready),
.rvalid(rvalid),
.rdata(rdata),
.rresp(rresp),
.rlast(rlast));
wire fifo_rd_en = 1'b1;
wire fifo_rd_valid;
wire fifo_rd_underflow;
wire [WIDTH_DEST-1:0] fifo_rd_dout;
reg [WIDTH_DEST-1:0] fifo_rd_dout_cmp = 'h00;
reg fifo_rd_dout_mismatch = 1'b0;
reg [23:0] fifo_rd_req_length = REQ_LEN_INIT;
reg [23:0] fifo_rd_beat_counter = 'h00;
axi_dmac_transfer #(
.DMA_TYPE_SRC(0),
.DMA_TYPE_DEST(2),
.DMA_DATA_WIDTH_SRC(WIDTH_SRC),
.DMA_DATA_WIDTH_DEST(WIDTH_DEST),
.DMA_LENGTH_ALIGN($clog2(WIDTH_DEST/8)),
.FIFO_SIZE(8)
) transfer (
.m_src_axi_aclk(clk),
.m_src_axi_aresetn(resetn),
.m_axi_arvalid(arvalid),
.m_axi_arready(arready),
.m_axi_araddr(araddr),
.m_axi_arlen(arlen),
.m_axi_arsize(arsize),
.m_axi_arburst(arburst),
.m_axi_arprot(arprot),
.m_axi_arcache(arcache),
.m_axi_rready(rready),
.m_axi_rvalid(rvalid),
.m_axi_rdata(rdata),
.m_axi_rlast(rlast),
.m_axi_rresp(rresp),
.ctrl_clk(clk),
.ctrl_resetn(resetn),
.ctrl_enable(1'b1),
.ctrl_pause(1'b0),
.req_eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_dest_address(TRANSFER_ADDR[31:$clog2(WIDTH_DEST/8)]),
.req_src_address(TRANSFER_ADDR[31:$clog2(WIDTH_SRC/8)]),
.req_x_length(req_length),
.req_y_length(24'h00),
.req_dest_stride(24'h00),
.req_src_stride(24'h00),
.req_sync_transfer_start(1'b0),
.fifo_rd_clk(clk),
.fifo_rd_en(fifo_rd_en),
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_underflow(fifo_rd_underflow),
.fifo_rd_dout(fifo_rd_dout));
always @(posedge clk) begin: dout
integer i;
if (reset == 1'b1) begin
for (i = 0; i < WIDTH_DEST; i = i + 8) begin
fifo_rd_dout_cmp[i+:8] <= TRANSFER_ADDR[7:0] + i / 8;
end
fifo_rd_dout_mismatch <= 1'b0;
fifo_rd_req_length <= REQ_LEN_INIT;
fifo_rd_beat_counter <= 'h00;
end else begin
fifo_rd_dout_mismatch <= 1'b0;
if (fifo_rd_valid == 1'b1) begin
if (fifo_rd_beat_counter + WIDTH_DEST / 8 < fifo_rd_req_length) begin
for (i = 0; i < WIDTH_DEST; i = i + 8) begin
fifo_rd_dout_cmp[i+:8] <= fifo_rd_dout_cmp[i+:8] + WIDTH_DEST / 8;
end
fifo_rd_beat_counter <= fifo_rd_beat_counter + WIDTH_DEST / 8;
end else begin
for (i = 0; i < WIDTH_DEST; i = i + 8) begin
fifo_rd_dout_cmp[i+:8] <= TRANSFER_ADDR[7:0] + i / 8;
end
fifo_rd_beat_counter <= 'h00;
fifo_rd_req_length <= fifo_rd_req_length + REQ_LEN_INC;
end
if (fifo_rd_dout_cmp != fifo_rd_dout) begin
fifo_rd_dout_mismatch <= 1'b1;
end
end
end
end
always @(posedge clk) begin
failed <= failed | fifo_rd_dout_mismatch;
end
endmodule
adi_library/axi_dmac/tb/dma_write_shutdown_tb
Executable
+19
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@@ -0,0 +1,19 @@
#!/bin/bash
SOURCE="$0.v"
SOURCE+=" axi_write_slave.v axi_slave.v"
SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../dmac_2d_transfer.v"
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"
SOURCE+=" ../src_fifo_inf.v"
SOURCE+=" ../axi_dmac_response_manager.v"
SOURCE+=" ../dest_axi_mm.v ../response_handler.v ../address_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
SOURCE+=" ../../util_cdc/sync_event.v"
SOURCE+=" ../../common/ad_mem_asym.v"
cd `dirname $0`
source ../../common/tb/run_tb.sh
adi_library/axi_dmac/tb/dma_write_shutdown_tb.v
+168
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@@ -0,0 +1,168 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dma_write_shutdown_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`include "tb_base.v"
localparam TRANSFER_ADDR = 32'h80000000;
localparam TRANSFER_LEN = 24'h2ff;
reg fifo_clk = 1'b0;
wire awvalid;
wire awready;
wire [31:0] awaddr;
wire [7:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
wire [2:0] awprot;
wire [3:0] awcache;
wire wlast;
wire wvalid;
wire wready;
wire [3:0] wstrb;
wire [31:0] wdata;
wire bready;
wire bvalid;
wire [1:0] bresp;
wire [11:0] dbg_status;
/* Twice as fast as the AXI clk so the FIFO fills up */
always @(*) #5 fifo_clk <= ~fifo_clk;
axi_write_slave #(
.DATA_WIDTH(32)
) i_write_slave (
.clk(clk),
.reset(reset),
.awvalid(awvalid),
.awready(awready),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awprot(awprot),
.awcache(awcache),
.wready(wready),
.wvalid(wvalid),
.wdata(wdata),
.wstrb(wstrb),
.wlast(wlast),
.bvalid(bvalid),
.bready(bready),
.bresp(bresp));
reg ctrl_enable = 1'b0;
initial begin
#1000
@(posedge clk) ctrl_enable <= 1'b1;
#3000
@(posedge clk) ctrl_enable <= 1'b0;
end
always @(posedge clk) begin
failed <= ctrl_enable == 1'b0 && (
dbg_status !== 12'h701 ||
i_write_slave.i_axi_slave.req_fifo_level !== 'h00);
end
axi_dmac_transfer #(
.DMA_DATA_WIDTH_SRC(32),
.DMA_DATA_WIDTH_DEST(32),
.FIFO_SIZE(8),
.DMA_LENGTH_ALIGN(2)
) i_transfer (
.m_dest_axi_aclk (clk),
.m_dest_axi_aresetn(resetn),
.m_axi_awvalid(awvalid),
.m_axi_awready(awready),
.m_axi_awaddr(awaddr),
.m_axi_awlen(awlen),
.m_axi_awsize(awsize),
.m_axi_awburst(awburst),
.m_axi_awprot(awprot),
.m_axi_awcache(awcache),
.m_axi_wready(wready),
.m_axi_wvalid(wvalid),
.m_axi_wdata(wdata),
.m_axi_wstrb(wstrb),
.m_axi_wlast(wlast),
.m_axi_bvalid(bvalid),
.m_axi_bready(bready),
.m_axi_bresp(bresp),
.ctrl_clk(clk),
.ctrl_resetn(resetn),
.ctrl_enable(ctrl_enable),
.ctrl_pause(1'b0),
.req_eot(),
.req_response_ready(1'b1),
.req_valid(1'b1),
.req_ready(),
.req_dest_address(TRANSFER_ADDR[31:2]),
.req_src_address(TRANSFER_ADDR[31:2]),
.req_x_length(TRANSFER_LEN),
.req_y_length(24'h00),
.req_dest_stride(24'h00),
.req_src_stride(24'h00),
.req_sync_transfer_start(1'b0),
.req_last(1'b0),
.fifo_wr_clk(fifo_clk),
.fifo_wr_en(1'b1),
.fifo_wr_din(32'h00),
.fifo_wr_sync(1'b1),
.fifo_wr_xfer_req(),
.dbg_status(dbg_status));
endmodule
adi_library/axi_dmac/tb/dma_write_tb
Executable
+18
View File
@@ -0,0 +1,18 @@
#!/bin/bash
SOURCE="dma_write_tb.v"
SOURCE+=" axi_write_slave.v axi_slave.v"
SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"
SOURCE+=" ../src_fifo_inf.v"
SOURCE+=" ../axi_dmac_response_manager.v"
SOURCE+=" ../dest_axi_mm.v ../response_handler.v ../address_generator.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
SOURCE+=" ../../util_cdc/sync_event.v"
SOURCE+=" ../../common/ad_mem_asym.v"
cd `dirname $0`
source ../../common/tb/run_tb.sh
adi_library/axi_dmac/tb/dma_write_tb.v
+190
View File
@@ -0,0 +1,190 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dma_write_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
parameter WIDTH_DEST = 32;
parameter WIDTH_SRC = 32;
parameter REQ_LEN_INC = 4;
parameter REQ_LEN_INIT = 4;
`include "tb_base.v"
localparam TRANSFER_ADDR = 32'h80000000;
reg req_valid = 1'b1;
wire req_ready;
reg [23:0] req_length = REQ_LEN_INIT - 1;
wire awvalid;
wire awready;
wire [31:0] awaddr;
wire [7:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
wire [2:0] awprot;
wire [3:0] awcache;
wire wlast;
wire wvalid;
wire wready;
wire [WIDTH_DEST/8-1:0] wstrb;
wire [WIDTH_DEST-1:0] wdata;
reg [WIDTH_SRC-1:0] fifo_wr_din = 'b0;
reg fifo_wr_rq = 'b0;
wire fifo_wr_xfer_req;
wire bready;
wire bvalid;
wire [1:0] bresp;
always @(posedge clk) begin
if (reset != 1'b1 && req_ready == 1'b1) begin
req_valid <= 1'b1;
req_length <= req_length + REQ_LEN_INC;
end
end
axi_write_slave #(
.DATA_WIDTH(WIDTH_DEST)
) i_write_slave (
.clk(clk),
.reset(reset),
.awvalid(awvalid),
.awready(awready),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awprot(awprot),
.awcache(awcache),
.wready(wready),
.wvalid(wvalid),
.wdata(wdata),
.wstrb(wstrb),
.wlast(wlast),
.bvalid(bvalid),
.bready(bready),
.bresp(bresp));
axi_dmac_transfer #(
.DMA_DATA_WIDTH_SRC(WIDTH_SRC),
.DMA_DATA_WIDTH_DEST(WIDTH_DEST),
.DMA_LENGTH_ALIGN($clog2(WIDTH_SRC/8))
) i_transfer (
.m_dest_axi_aclk (clk),
.m_dest_axi_aresetn(resetn),
.m_axi_awvalid(awvalid),
.m_axi_awready(awready),
.m_axi_awaddr(awaddr),
.m_axi_awlen(awlen),
.m_axi_awsize(awsize),
.m_axi_awburst(awburst),
.m_axi_awprot(awprot),
.m_axi_awcache(awcache),
.m_axi_wready(wready),
.m_axi_wvalid(wvalid),
.m_axi_wdata(wdata),
.m_axi_wstrb(wstrb),
.m_axi_wlast(wlast),
.m_axi_bvalid(bvalid),
.m_axi_bready(bready),
.m_axi_bresp(bresp),
.ctrl_clk(clk),
.ctrl_resetn(resetn),
.ctrl_enable(1'b1),
.ctrl_pause(1'b0),
.req_eot(eot),
.req_response_ready(1'b1),
.req_valid(req_valid),
.req_ready(req_ready),
.req_dest_address(TRANSFER_ADDR[31:$clog2(WIDTH_DEST/8)]),
.req_src_address(TRANSFER_ADDR[31:$clog2(WIDTH_SRC/8)]),
.req_x_length(req_length),
.req_y_length(24'h00),
.req_dest_stride(24'h00),
.req_src_stride(24'h00),
.req_sync_transfer_start(1'b0),
.fifo_wr_clk(clk),
.fifo_wr_en(fifo_wr_en),
.fifo_wr_din(fifo_wr_din),
.fifo_wr_overflow(fifo_wr_overflow),
.fifo_wr_sync(1'b1),
.fifo_wr_xfer_req(fifo_wr_xfer_req));
always @(posedge clk) begin: fifo_wr
integer i;
if (reset == 1'b1) begin
for (i = 0; i < WIDTH_SRC; i = i + 8) begin
fifo_wr_din[i+:8] <= i / 8;
end
fifo_wr_rq <= 'b0;
end else begin
if (fifo_wr_en == 1'b1) begin
for (i = 0; i < WIDTH_SRC; i = i + 8) begin
fifo_wr_din[i+:8] <= fifo_wr_din[i+:8] + WIDTH_SRC / 8;
end
end
fifo_wr_rq <= (($random % 4) == 0);
end
end
assign fifo_wr_en = fifo_wr_rq & fifo_wr_xfer_req;
always @(posedge clk) begin
if (reset) begin
failed <= 'b0;
end else begin
failed <= failed |
i_write_slave.failed |
fifo_wr_overflow;
end
end
endmodule
adi_library/axi_dmac/tb/regmap_tb
Executable
+10
View File
@@ -0,0 +1,10 @@
#!/bin/bash
SOURCE="regmap_tb.v"
SOURCE+=" ../axi_dmac_regmap.v ../axi_dmac_regmap_request.v"
SOURCE+=" ../../common/up_axi.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v"
SOURCE+=" ../../util_axis_fifo/util_axis_fifo_address_generator.v"
cd `dirname $0`
source ../../common/tb/run_tb.sh
adi_library/axi_dmac/tb/regmap_tb.v
+426
View File
@@ -0,0 +1,426 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module regmap_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`define TIMEOUT 1000000
`include "tb_base.v"
localparam DMA_LENGTH_WIDTH = 24;
localparam BYTES_PER_BEAT = 1;
localparam DMA_AXI_ADDR_WIDTH = 32;
localparam LENGTH_ALIGN = 2;
localparam LENGTH_MASK = {DMA_LENGTH_WIDTH{1'b1}};
localparam LENGTH_ALIGN_MASK = {LENGTH_ALIGN{1'b1}};
localparam STRIDE_MASK = {{DMA_LENGTH_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};
localparam ADDR_MASK = {{DMA_AXI_ADDR_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}};
localparam VAL_DBG_SRC_ADDR = 32'h76543210;
localparam VAL_DBG_DEST_ADDR = 32'hfedcba98;
localparam VAL_DBG_STATUS = 12'ha5;
localparam VAL_DBG_IDS0 = 32'h01234567;
localparam VAL_DBG_IDS1 = 32'h89abcdef;
localparam AW = 11;
localparam NUM_REGS = 'h200;
wire s_axi_aclk = clk;
wire s_axi_aresetn = ~reset;
reg s_axi_awvalid = 1'b0;
reg s_axi_wvalid = 1'b0;
reg [AW-1:0] s_axi_awaddr = 'h00;
reg [31:0] s_axi_wdata = 'h00;
wire [1:0] s_axi_bresp;
wire s_axi_awready;
wire s_axi_wready;
wire s_axi_bready = 1'b1;
wire [3:0] s_axi_wstrb = 4'b1111;
wire [2:0] s_axi_awprot = 3'b000;
wire [2:0] s_axi_arprot = 3'b000;
wire [1:0] s_axi_rresp;
wire [31:0] s_axi_rdata;
task write_reg;
input [31:0] addr;
input [31:0] value;
begin
@(posedge s_axi_aclk)
s_axi_awvalid <= 1'b1;
s_axi_wvalid <= 1'b1;
s_axi_awaddr <= addr;
s_axi_wdata <= value;
@(posedge s_axi_aclk)
while (s_axi_awvalid || s_axi_wvalid) begin
@(posedge s_axi_aclk)
if (s_axi_awready)
s_axi_awvalid <= 1'b0;
if (s_axi_wready)
s_axi_wvalid <= 1'b0;
end
end
endtask
reg [31:0] expected_reg_mem[0:NUM_REGS-1];
reg [AW-1:0] s_axi_araddr = 'h0;
reg s_axi_arvalid = 'h0;
reg s_axi_rready = 'h0;
wire s_axi_arready;
wire s_axi_rvalid;
task read_reg;
input [31:0] addr;
output [31:0] value;
begin
s_axi_arvalid <= 1'b1;
s_axi_araddr <= addr;
s_axi_rready <= 1'b1;
@(posedge s_axi_aclk) #0;
while (s_axi_arvalid) begin
if (s_axi_arready == 1'b1) begin
s_axi_arvalid <= 1'b0;
end
@(posedge s_axi_aclk) #0;
end
while (s_axi_rready) begin
if (s_axi_rvalid == 1'b1) begin
value <= s_axi_rdata;
s_axi_rready <= 1'b0;
end
@(posedge s_axi_aclk) #0;
end
end
endtask
task read_reg_check;
input [31:0] addr;
output match;
reg [31:0] value;
reg [31:0] expected;
input [255:0] message;
begin
read_reg(addr, value);
expected = expected_reg_mem[addr[11:2]];
match <= value === expected;
if (value !== expected) begin
$display("%0s: Register mismatch for %x. Expected %x, got %x",
message, addr, expected, value);
end
end
endtask
reg read_match = 1'b1;
always @(posedge clk) begin
if (read_match == 1'b0) begin
failed <= 1'b1;
end
end
task set_reset_reg_value;
input [31:0] addr;
input [31:0] value;
begin
expected_reg_mem[addr[AW-1:2]] <= value;
end
endtask
task initialize_expected_reg_mem;
integer i;
begin
for (i = 0; i < NUM_REGS; i = i + 1)
expected_reg_mem[i] <= 'h00;
/* Non zero power-on-reset values */
set_reset_reg_value('h00, 32'h00040361); /* PCORE version register */
set_reset_reg_value('h0c, 32'h444d4143); /* PCORE magic register */
set_reset_reg_value('h10, 32'h00002101); /* Interface Description*/
set_reset_reg_value('h80, 'h3); /* IRQ mask */
set_reset_reg_value('h40c, 'h3); /* Flags */
set_reset_reg_value('h418, LENGTH_ALIGN_MASK); /* Length alignment */
set_reset_reg_value('h434, VAL_DBG_DEST_ADDR);
set_reset_reg_value('h438, VAL_DBG_SRC_ADDR);
set_reset_reg_value('h43c, VAL_DBG_STATUS);
set_reset_reg_value('h440, VAL_DBG_IDS0);
set_reset_reg_value('h444, VAL_DBG_IDS1);
end
endtask
task check_all_registers;
input [255:0] message;
integer i;
begin
for (i = 0; i < NUM_REGS*4; i = i + 4) begin
read_reg_check(i, read_match, message);
end
end
endtask
task write_reg_and_update;
input [31:0] addr;
input [31:0] value;
integer i;
begin
write_reg(addr, value);
expected_reg_mem[addr[AW-1:2]] <= value;
end
endtask
task invert_register;
input [31:0] addr;
reg [31:0] value;
begin
read_reg(addr, value);
write_reg(addr, ~value);
end
endtask
task invert_all_registers;
integer i;
begin
for (i = 0; i < NUM_REGS*4; i = i + 4) begin
invert_register(i);
end
end
endtask
reg request_ready = 1'b0;
wire [31:BYTES_PER_BEAT] request_dest_address;
wire [31:BYTES_PER_BEAT] request_src_address;
wire [DMA_LENGTH_WIDTH-1:0] request_x_length;
wire [DMA_LENGTH_WIDTH-1:0] request_y_length;
wire [DMA_LENGTH_WIDTH-1:0] request_dest_stride;
wire [DMA_LENGTH_WIDTH-1:0] request_src_stride;
wire request_last;
reg response_eot = 1'b0;
wire [6:0] response_measured_burst_length = 'hff;
wire ctrl_enable;
wire ctrl_pause;
wire request_valid;
wire request_sync_transfer_start;
wire response_partial = 1'b1;
reg response_valid = 1'b0;
wire response_ready;
always @(posedge clk) begin
if (request_valid & request_ready) begin
response_valid <= 1'b1;
end else if (response_ready) begin
response_valid <= 1'b0;
end
end
integer i;
initial begin
initialize_expected_reg_mem();
@(posedge s_axi_aresetn)
set_reset_reg_value('h44c, 32'hxxxxxxxx);
set_reset_reg_value('h450, 2'bX);
check_all_registers("Initial");
/* Check scratch */
write_reg_and_update('h08, 32'h12345678);
check_all_registers("Scratch");
/* Check IRQ mask */
write_reg_and_update('h80, 32'h0);
check_all_registers("IRQ mask");
/* Check transfer registers */
write_reg_and_update('h40c, 'h7);
write_reg_and_update('h410, ADDR_MASK);
write_reg_and_update('h414, ADDR_MASK);
write_reg_and_update('h418, LENGTH_MASK);
write_reg_and_update('h41c, LENGTH_MASK);
write_reg_and_update('h420, STRIDE_MASK);
write_reg_and_update('h424, STRIDE_MASK);
check_all_registers("Transfer setup 1");
/* Check transfer registers */
write_reg_and_update('h40c, {$random} & 'h7);
write_reg_and_update('h410, {$random} & ADDR_MASK);
write_reg_and_update('h414, {$random} & ADDR_MASK);
write_reg_and_update('h418, {$random} & LENGTH_MASK | LENGTH_ALIGN_MASK);
write_reg_and_update('h41c, {$random} & LENGTH_MASK);
write_reg_and_update('h420, {$random} & STRIDE_MASK);
write_reg_and_update('h424, {$random} & STRIDE_MASK);
check_all_registers("Transfer setup 2");
/* Start transfer */
write_reg_and_update('h400, 'h01);
write_reg_and_update('h408, 'h01);
set_reset_reg_value('h428, 32'h00000000);
set_reset_reg_value('h448, 24'h000000);
set_reset_reg_value('h44c, 32'hxxxxxxxx);
set_reset_reg_value('h450, 2'bX);
check_all_registers("Transfer submitted");
@(posedge clk) request_ready <= 1'b1;
/* Interrupt pending */
set_reset_reg_value('h84, 'h01);
set_reset_reg_value('h88, 'h01);
/* Transfer ID */
set_reset_reg_value('h404, 'h01);
/* Tansfer pending */
set_reset_reg_value('h408, 'h00);
set_reset_reg_value('h428, 32'h80000000);
set_reset_reg_value('h448, 24'h000080);
set_reset_reg_value('h44c, 32'h00000080);
set_reset_reg_value('h450, 'h0);
check_all_registers("Transfer accepted");
@(posedge clk) response_eot <= 1'b1;
@(posedge clk) response_eot <= 1'b0;
/* Interrupt registers */
set_reset_reg_value('h84, 'h01);
set_reset_reg_value('h88, 'h01);
set_reset_reg_value('h428, 'h00);
set_reset_reg_value('h42c, 'h00);
set_reset_reg_value('h44c, 32'h00000080);
set_reset_reg_value('h450, 'h0);
set_reset_reg_value('h448, 24'h000080);
check_all_registers("Transfer completed");
/* Clear interrupts */
write_reg('h84, 'h01);
set_reset_reg_value('h84, 'h00);
set_reset_reg_value('h88, 'h00);
check_all_registers("Clear interrupts 1");
write_reg('h84, 'h02);
set_reset_reg_value('h84, 'h00);
set_reset_reg_value('h88, 'h00);
check_all_registers("Clear interrupts 2");
/* Check that reset works for all registers */
do_trigger_reset();
initialize_expected_reg_mem();
write_reg_and_update('h40c, 'h00);
set_reset_reg_value('h44c, 32'h00000080);
check_all_registers("Reset 1");
invert_all_registers();
do_trigger_reset();
write_reg_and_update('h40c, 'h00);
set_reset_reg_value('h44c, 32'h00000080);
check_all_registers("Reset 2");
end
axi_dmac_regmap #(
.ID(0),
.DISABLE_DEBUG_REGISTERS(0),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT),
.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.DMA_LENGTH_ALIGN(LENGTH_ALIGN),
.DMA_CYCLIC(1),
.BYTES_PER_BURST_WIDTH(7),
.HAS_DEST_ADDR(1),
.HAS_SRC_ADDR(1),
.DMA_2D_TRANSFER(1),
.SYNC_TRANSFER_START(0)
) i_axi (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awprot(s_axi_awprot),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wready(s_axi_wready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bready(s_axi_bready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arready(s_axi_arready),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
.ctrl_enable(ctrl_enable),
.ctrl_pause(ctrl_pause),
.request_valid(request_valid),
.request_ready(request_ready),
.request_dest_address(request_dest_address),
.request_src_address(request_src_address),
.request_x_length(request_x_length),
.request_y_length(request_y_length),
.request_dest_stride(request_dest_stride),
.request_src_stride(request_src_stride),
.request_last(request_last),
.request_sync_transfer_start(request_sync_transfer_start),
.irq(irq),
.response_eot(response_eot),
.response_measured_burst_length(response_measured_burst_length),
.response_partial(response_partial),
.response_valid(response_valid),
.response_ready(response_ready),
.dbg_src_addr(VAL_DBG_SRC_ADDR),
.dbg_dest_addr(VAL_DBG_DEST_ADDR),
.dbg_status(VAL_DBG_STATUS),
.dbg_ids0(VAL_DBG_IDS0),
.dbg_ids1(VAL_DBG_IDS1));
endmodule
adi_library/axi_dmac/tb/reset_manager_tb
Executable
+8
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@@ -0,0 +1,8 @@
#!/bin/bash
SOURCE="$0.v"
SOURCE+=" ../axi_dmac_reset_manager.v"
SOURCE+=" ../../util_cdc/sync_bits.v"
cd `dirname $0`
source ../../common/tb/run_tb.sh
adi_library/axi_dmac/tb/reset_manager_tb.v
+118
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module reset_manager_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`define TIMEOUT 1000000
`include "tb_base.v"
reg clk_a = 1'b0;
reg clk_b = 1'b0;
reg clk_c = 1'b0;
reg [5:0] resetn_shift = 'h0;
reg [10:0] counter = 'h00;
reg ctrl_enable = 1'b0;
reg ctrl_pause = 1'b0;
always #10 clk_a <= ~clk_a;
always #3 clk_b <= ~clk_b;
always #7 clk_c <= ~clk_c;
always @(posedge clk_a) begin
counter <= counter + 1'b1;
if (counter == 'h60 || counter == 'h150 || counter == 'h185) begin
ctrl_enable <= 1'b1;
end else if (counter == 'h100 || counter == 'h110 || counter == 'h180) begin
ctrl_enable <= 1'b0;
end
if (counter == 'h160) begin
ctrl_pause = 1'b1;
end else if (counter == 'h190) begin
ctrl_pause = 1'b0;
end
end
reg [15:0] req_enabled_shift;
wire req_enable;
wire req_enabled = req_enabled_shift[15];
reg [15:0] dest_enabled_shift;
wire dest_enable;
wire dest_enabled = dest_enabled_shift[15];
reg [15:0] src_enabled_shift;
wire src_enable;
wire src_enabled = src_enabled_shift[15];
always @(posedge clk_a) begin
req_enabled_shift <= {req_enabled_shift[14:0],req_enable};
end
always @(posedge clk_b) begin
dest_enabled_shift <= {dest_enabled_shift[14:0],dest_enable};
end
always @(posedge clk_c) begin
src_enabled_shift <= {src_enabled_shift[14:0],src_enable};
end
axi_dmac_reset_manager i_reset_manager (
.clk(clk_a),
.resetn(resetn),
.ctrl_pause(ctrl_pause),
.ctrl_enable(ctrl_enable),
.req_enable(req_enable),
.req_enabled(req_enabled),
.dest_clk(clk_b),
.dest_ext_resetn(1'b0),
.dest_enable(dest_enable),
.dest_enabled(dest_enabled),
.src_clk(clk_c),
.src_ext_resetn(1'b0),
.src_enable(src_enable),
.src_enabled(src_enabled));
endmodule
adi_library/axi_dmac/tb/tb_base.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
reg clk = 1'b0;
reg [3:0] reset_shift = 4'b1111;
reg trigger_reset = 1'b0;
wire reset;
wire resetn = ~reset;
reg failed = 1'b0;
initial
begin
$dumpfile (VCD_FILE);
$dumpvars;
`ifdef TIMEOUT
#`TIMEOUT
`else
#100000
`endif
if (failed == 1'b0)
$display("SUCCESS");
else
$display("FAILED");
$finish;
end
always @(*) #10 clk <= ~clk;
always @(posedge clk) begin
if (trigger_reset == 1'b1) begin
reset_shift <= 3'b111;
end else begin
reset_shift <= {reset_shift[2:0],1'b0};
end
end
assign reset = reset_shift[3];
task do_trigger_reset;
begin
@(posedge clk) trigger_reset <= 1'b1;
@(posedge clk) trigger_reset <= 1'b0;
end
endtask