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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
commit 315a673005
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adi_library/axi_fmcadc5_sync/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_fmcadc5_sync
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_fmcadc5_sync.v
GENERIC_DEPS += axi_fmcadc5_sync_calcor.v
XILINX_DEPS += ../xilinx/common/ad_data_out.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += axi_fmcadc5_sync_constr.xdc
XILINX_DEPS += axi_fmcadc5_sync_ip.tcl
include ../scripts/library.mk
adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// this module is a helper core for linux. as much as possible, try not to use this core.
// best thing to do is look at no-os and implement a proper frame work in linux.
// most controls are scattered around other cores, here we collect them to provide a common access.
`timescale 1ns/100ps
module axi_fmcadc5_sync #(
parameter integer ID = 0,
parameter [ 7:0] FPGA_TECHNOLOGY = 0,
parameter [ 7:0] FPGA_FAMILY = 0,
parameter [ 7:0] SPEED_GRADE = 0,
parameter [ 7:0] DEV_PACKAGE = 0,
parameter DELAY_REFCLK_FREQUENCY = 200
) (
// receive interface
input rx_clk,
output rx_sysref,
input rx_sync_0,
input rx_sync_1,
output rx_sysref_p,
output rx_sysref_n,
output rx_sync_0_p,
output rx_sync_0_n,
output rx_sync_1_p,
output rx_sync_1_n,
input rx_enable_0,
input [255:0] rx_data_0,
input rx_enable_1,
input [255:0] rx_data_1,
output rx_enable,
output [511:0] rx_data,
// calibration signal
output vcal,
// switching regulator clocks
output psync,
// delay interface
input delay_rst,
input delay_clk,
// spi override
input [ 7:0] spi_csn_o,
input spi_clk_o,
input spi_sdo_o,
output [ 7:0] spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 15:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 15:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot
);
// version
localparam [31:0] PCORE_VERSION = 32'h00040063;
// internal registers
reg [ 7:0] up_psync_count = 'd0;
reg up_psync = 'd0;
reg up_cal_done_t_m1 = 'd0;
reg up_cal_done_t_m2 = 'd0;
reg up_cal_done_t_m3 = 'd0;
reg [ 15:0] up_cal_max_0 = 'd0;
reg [ 15:0] up_cal_min_0 = 'd0;
reg [ 15:0] up_cal_max_1 = 'd0;
reg [ 15:0] up_cal_min_1 = 'd0;
reg up_cal_enable = 'd0;
reg up_cor_enable = 'd0;
reg up_cor_enable_t = 'd0;
reg [ 15:0] up_cor_scale_0 = 'd0;
reg [ 15:0] up_cor_offset_0 = 'd0;
reg [ 15:0] up_cor_scale_1 = 'd0;
reg [ 15:0] up_cor_offset_1 = 'd0;
reg [ 7:0] up_vcal_8 = 'd0;
reg up_vcal = 'd0;
reg [ 7:0] up_vcal_cnt = 'd0;
reg up_vcal_enable = 'd0;
reg up_sysref_ack_t_m1 = 'd0;
reg up_sysref_ack_t_m2 = 'd0;
reg up_sysref_ack_t_m3 = 'd0;
reg up_sysref_control_t = 'd0;
reg [ 1:0] up_sysref_mode_e = 'd0;
reg up_sysref_mode_i = 'd0;
reg up_sysref_req_t = 'd0;
reg up_sysref_status = 'd0;
reg up_sync_control_t = 'd0;
reg up_sync_mode = 'd0;
reg up_sync_disable_1 = 'd0;
reg up_sync_disable_0 = 'd0;
reg up_sync_status_t_m1 = 'd0;
reg up_sync_status_t_m2 = 'd0;
reg up_sync_status_t_m3 = 'd0;
reg up_sync_status_1 = 'd0;
reg up_sync_status_0 = 'd0;
reg up_delay_ld = 'd0;
reg [ 4:0] up_delay_wdata = 'd0;
reg [ 7:0] up_spi_csn_int = 'd0;
reg up_spi_clk_int = 'd0;
reg up_spi_mosi_int = 'd0;
reg up_spi_gnt = 'd0;
reg up_spi_req = 'd0;
reg [ 7:0] up_spi_csn = 'd0;
reg [ 5:0] up_spi_cnt = 'd0;
reg [ 31:0] up_spi_clk_32 = 'd0;
reg [ 31:0] up_spi_out_32 = 'd0;
reg [ 31:0] up_spi_in_32 = 'd0;
reg [ 7:0] up_spi_out = 'd0;
reg [ 31:0] up_scratch = 'd0;
reg [ 31:0] up_timer = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [ 31:0] up_rdata = 'd0;
reg rx_cal_enable_m1 = 'd0;
reg rx_cal_enable = 'd0;
reg rx_cor_enable_t_m1 = 'd0;
reg rx_cor_enable_t_m2 = 'd0;
reg rx_cor_enable_t_m3 = 'd0;
reg rx_cor_enable = 'd0;
reg [ 15:0] rx_cor_scale_0 = 'd0;
reg [ 15:0] rx_cor_offset_0 = 'd0;
reg [ 15:0] rx_cor_scale_1 = 'd0;
reg [ 15:0] rx_cor_offset_1 = 'd0;
reg [ 15:0] rx_cor_scale_d_0 = 'd0;
reg [ 15:0] rx_cor_offset_d_0 = 'd0;
reg [ 15:0] rx_cor_scale_d_1 = 'd0;
reg [ 15:0] rx_cor_offset_d_1 = 'd0;
reg [ 7:0] rx_sysref_cnt = 'd0;
reg rx_sysref_control_t_m1 = 'd0;
reg rx_sysref_control_t_m2 = 'd0;
reg rx_sysref_control_t_m3 = 'd0;
reg [ 1:0] rx_sysref_mode_e = 'd0;
reg rx_sysref_mode_i = 'd0;
reg rx_sysref_req_t_m1 = 'd0;
reg rx_sysref_req_t_m2 = 'd0;
reg rx_sysref_req_t_m3 = 'd0;
reg rx_sysref_req = 'd0;
reg rx_sysref_e = 'd0;
reg rx_sysref_i = 'd0;
reg rx_sysref_ack_t = 'd0;
reg rx_sysref_enb_e = 'd0;
reg rx_sysref_enb_i = 'd0;
reg rx_sync_control_t_m1 = 'd0;
reg rx_sync_control_t_m2 = 'd0;
reg rx_sync_control_t_m3 = 'd0;
reg rx_sync_mode = 'd0;
reg rx_sync_disable_1 = 'd0;
reg rx_sync_disable_0 = 'd0;
reg rx_sync_out_1 = 'd0;
reg rx_sync_out_0 = 'd0;
reg [ 7:0] rx_sync_cnt = 'd0;
reg rx_sync_hold_1 = 'd0;
reg rx_sync_hold_0 = 'd0;
reg rx_sync_status_t = 'd0;
reg rx_sync_status_1 = 'd0;
reg rx_sync_status_0 = 'd0;
// internal signals
wire up_cal_done_t_s;
wire up_sysref_ack_t_s;
wire up_sync_status_t_s;
wire up_spi_gnt_s;
wire [ 31:0] up_spi_out_32_s;
wire [ 7:0] up_spi_in_s;
wire rx_cor_enable_t_s;
wire rx_cal_done_t_s;
wire [ 15:0] rx_cal_max_0_s;
wire [ 15:0] rx_cal_min_0_s;
wire [ 15:0] rx_cal_max_1_s;
wire [ 15:0] rx_cal_min_1_s;
wire rx_sysref_control_t_s;
wire rx_sysref_req_t_s;
wire rx_sysref_enb_e_s;
wire rx_sync_control_t_s;
wire [ 4:0] up_delay_rdata_s;
wire up_delay_locked_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire up_rstn;
wire up_clk;
// signal name changes
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// switching regulator clocks (~602K)
assign psync = up_psync;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_psync_count <= 7'd0;
up_psync <= 1'b0;
end else begin
if (up_psync_count >= 7'h52) begin
up_psync_count <= 7'd0;
end else begin
up_psync_count <= up_psync_count + 1'b1;
end
if (up_psync_count >= 7'h4f) begin
up_psync <= ~up_psync;
end
end
end
// calibration (offset & gain only)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_cal_done_t_m1 <= 1'd0;
up_cal_done_t_m2 <= 1'd0;
up_cal_done_t_m3 <= 1'd0;
end else begin
up_cal_done_t_m1 <= rx_cal_done_t_s;
up_cal_done_t_m2 <= up_cal_done_t_m1;
up_cal_done_t_m3 <= up_cal_done_t_m2;
end
end
assign up_cal_done_t_s = up_cal_done_t_m3 ^ up_cal_done_t_m2;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_cal_max_0 <= 16'd0;
up_cal_min_0 <= 16'd0;
up_cal_max_1 <= 16'd0;
up_cal_min_1 <= 16'd0;
end else begin
if (up_cal_done_t_s == 1'b1) begin
up_cal_max_0 <= rx_cal_max_0_s;
up_cal_min_0 <= rx_cal_min_0_s;
up_cal_max_1 <= rx_cal_max_1_s;
up_cal_min_1 <= rx_cal_min_1_s;
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_cal_enable <= 1'd0;
up_cor_enable <= 1'd0;
up_cor_enable_t <= 1'd0;
up_cor_scale_0 <= 16'd0;
up_cor_offset_0 <= 16'd0;
up_cor_scale_1 <= 16'd0;
up_cor_offset_1 <= 16'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0060)) begin
up_cal_enable <= up_wdata_s[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0061)) begin
up_cor_enable <= up_wdata_s[0];
up_cor_enable_t <= ~up_cor_enable_t;
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0068)) begin
up_cor_scale_0 <= up_wdata_s[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0069)) begin
up_cor_offset_0 <= up_wdata_s[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h006a)) begin
up_cor_scale_1 <= up_wdata_s[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h006b)) begin
up_cor_offset_1 <= up_wdata_s[15:0];
end
end
end
// calibration signal register(s)
assign vcal = up_vcal;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_vcal_8 <= 8'd0;
up_vcal <= 1'd0;
up_vcal_cnt <= 8'd0;
up_vcal_enable <= 1'd0;
end else begin
if (up_vcal_8 >= up_vcal_cnt) begin
up_vcal_8 <= 8'd0;
up_vcal <= ~up_vcal & up_vcal_enable;
end else begin
up_vcal_8 <= up_vcal_8 + 1'b1;
up_vcal <= up_vcal;
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0050)) begin
up_vcal_cnt <= up_wdata_s[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0051)) begin
up_vcal_enable <= up_wdata_s[0];
end
end
end
// sysref register(s)
assign up_sysref_ack_t_s = up_sysref_ack_t_m3 ^ up_sysref_ack_t_m2;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_sysref_ack_t_m1 <= 1'd0;
up_sysref_ack_t_m2 <= 1'd0;
up_sysref_ack_t_m3 <= 1'd0;
end else begin
up_sysref_ack_t_m1 <= rx_sysref_ack_t;
up_sysref_ack_t_m2 <= up_sysref_ack_t_m1;
up_sysref_ack_t_m3 <= up_sysref_ack_t_m2;
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_sysref_control_t <= 1'd0;
up_sysref_mode_e <= 2'd0;
up_sysref_mode_i <= 1'd0;
up_sysref_req_t <= 1'd0;
up_sysref_status <= 1'b0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0040)) begin
up_sysref_control_t <= ~up_sysref_control_t;
up_sysref_mode_e <= up_wdata_s[5:4];
up_sysref_mode_i <= up_wdata_s[0];
end
if (up_sysref_status == 1'b1) begin
if (up_sysref_ack_t_s == 1'b1) begin
up_sysref_req_t <= up_sysref_req_t;
up_sysref_status <= 1'b0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0041)) begin
if (up_wdata_s[0] == 1'b1) begin
up_sysref_req_t <= ~up_sysref_req_t;
up_sysref_status <= 1'b1;
end
end
end
end
// sync register(s)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_sync_control_t <= 1'd0;
up_sync_mode <= 1'd0;
up_sync_disable_1 <= 1'd0;
up_sync_disable_0 <= 1'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0030)) begin
up_sync_control_t <= ~up_sync_control_t;
up_sync_mode <= up_wdata_s[2];
up_sync_disable_1 <= up_wdata_s[1];
up_sync_disable_0 <= up_wdata_s[0];
end
end
end
// simple current status (no persistence)
assign up_sync_status_t_s = up_sync_status_t_m3 ^ up_sync_status_t_m2;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_sync_status_t_m1 <= 1'd0;
up_sync_status_t_m2 <= 1'd0;
up_sync_status_t_m3 <= 1'd0;
up_sync_status_1 <= 1'd0;
up_sync_status_0 <= 1'd0;
end else begin
up_sync_status_t_m1 <= rx_sync_status_t;
up_sync_status_t_m2 <= up_sync_status_t_m1;
up_sync_status_t_m3 <= up_sync_status_t_m2;
if (up_sync_status_t_s == 1'b1) begin
up_sync_status_1 <= rx_sync_status_1;
up_sync_status_0 <= rx_sync_status_0;
end
end
end
// delay register(s)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_delay_ld <= 1'd0;
up_delay_wdata <= 5'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0020)) begin
up_delay_ld <= 1'b1;
end else begin
up_delay_ld <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0020)) begin
up_delay_wdata <= up_wdata_s[4:0];
end
end
end
// switching must be glitchless
assign spi_csn = up_spi_csn_int;
assign spi_clk = up_spi_clk_int;
assign spi_mosi = up_spi_mosi_int;
always @(negedge up_clk) begin
if (up_spi_gnt == 1'b1) begin
up_spi_csn_int <= up_spi_csn;
up_spi_clk_int <= up_spi_clk_32[31];
up_spi_mosi_int <= up_spi_out_32[31];
end else begin
up_spi_csn_int <= spi_csn_o;
up_spi_clk_int <= spi_clk_o;
up_spi_mosi_int <= spi_sdo_o;
end
end
assign up_spi_gnt_s = (&spi_csn_o) & ~spi_clk_o;
always @(posedge up_clk or negedge up_rstn) begin
if (up_rstn == 1'b0) begin
up_spi_gnt <= 1'd0;
end else begin
if (up_spi_gnt_s == 1'b1) begin
up_spi_gnt <= up_spi_req;
end
end
end
// spi data stretching
assign up_spi_out_32_s[31:28] = {4{up_wdata_s[7]}};
assign up_spi_out_32_s[27:24] = {4{up_wdata_s[6]}};
assign up_spi_out_32_s[23:20] = {4{up_wdata_s[5]}};
assign up_spi_out_32_s[19:16] = {4{up_wdata_s[4]}};
assign up_spi_out_32_s[15:12] = {4{up_wdata_s[3]}};
assign up_spi_out_32_s[11: 8] = {4{up_wdata_s[2]}};
assign up_spi_out_32_s[ 7: 4] = {4{up_wdata_s[1]}};
assign up_spi_out_32_s[ 3: 0] = {4{up_wdata_s[0]}};
assign up_spi_in_s[7] = up_spi_in_32[28];
assign up_spi_in_s[6] = up_spi_in_32[24];
assign up_spi_in_s[5] = up_spi_in_32[20];
assign up_spi_in_s[4] = up_spi_in_32[16];
assign up_spi_in_s[3] = up_spi_in_32[12];
assign up_spi_in_s[2] = up_spi_in_32[ 8];
assign up_spi_in_s[1] = up_spi_in_32[ 4];
assign up_spi_in_s[0] = up_spi_in_32[ 0];
// spi register(s)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_spi_req <= 1'd0;
up_spi_csn <= {8{1'b1}};
up_spi_cnt <= 6'd0;
up_spi_clk_32 <= 32'd0;
up_spi_out_32 <= 32'd0;
up_spi_in_32 <= 32'd0;
up_spi_out <= 8'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0010)) begin
up_spi_req <= up_wdata_s[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0012)) begin
up_spi_csn <= up_wdata_s[7:0];
end
if (up_spi_cnt[5] == 1'b1) begin
up_spi_cnt <= up_spi_cnt + 1'b1;
up_spi_clk_32 <= {up_spi_clk_32[30:0], 1'd0};
up_spi_out_32 <= {up_spi_out_32[30:0], 1'd0};
up_spi_in_32 <= {up_spi_in_32[30:0], spi_miso};
up_spi_out <= up_spi_out;
end else if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0013)) begin
up_spi_cnt <= 6'h20;
up_spi_clk_32 <= {8{4'h6}};
up_spi_out_32 <= up_spi_out_32_s;
up_spi_in_32 <= {31'd0, spi_miso};
up_spi_out <= up_wdata_s[7:0];
end
end
end
// scratch register(s)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_scratch <= 'd0;
up_timer <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0002)) begin
up_scratch <= up_wdata_s;
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0003)) begin
up_timer <= up_wdata_s;
end else if (up_timer > 0) begin
up_timer <= up_timer - 1'b1;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= up_wreq_s;
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr_s)
14'h0000: up_rdata <= PCORE_VERSION;
14'h0001: up_rdata <= ID;
14'h0002: up_rdata <= up_scratch;
14'h0003: up_rdata <= up_timer;
14'h0007: up_rdata <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
14'h0010: up_rdata <= {31'd0, up_spi_req};
14'h0011: up_rdata <= {31'd0, up_spi_gnt};
14'h0012: up_rdata <= {24'd0, up_spi_csn};
14'h0013: up_rdata <= {24'd0, up_spi_out};
14'h0014: up_rdata <= {24'd0, up_spi_in_s};
14'h0015: up_rdata <= {31'd0, up_spi_cnt[5]};
14'h0020: up_rdata <= {27'd0, up_delay_wdata};
14'h0021: up_rdata <= {27'd0, up_delay_rdata_s};
14'h0022: up_rdata <= {31'd0, up_delay_locked_s};
14'h0030: up_rdata <= {29'd0, up_sync_mode, up_sync_disable_1, up_sync_disable_0};
14'h0031: up_rdata <= {30'd0, up_sync_status_1, up_sync_status_0};
14'h0040: up_rdata <= {26'd0, up_sysref_mode_e, 3'b0, up_sysref_mode_i};
14'h0041: up_rdata <= {31'd0, up_sysref_status};
14'h0050: up_rdata <= {24'd0, up_vcal_cnt};
14'h0051: up_rdata <= {31'd0, up_vcal_enable};
14'h0060: up_rdata <= {30'd0, up_cal_enable};
14'h0061: up_rdata <= {30'd0, up_cor_enable};
14'h0064: up_rdata <= {16'd0, up_cal_max_0};
14'h0065: up_rdata <= {16'd0, up_cal_min_0};
14'h0066: up_rdata <= {16'd0, up_cal_max_1};
14'h0067: up_rdata <= {16'd0, up_cal_min_1};
14'h0068: up_rdata <= {16'd0, up_cor_scale_0};
14'h0069: up_rdata <= {16'd0, up_cor_offset_0};
14'h006a: up_rdata <= {16'd0, up_cor_scale_1};
14'h006b: up_rdata <= {16'd0, up_cor_offset_1};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// calibration at receive clock
always @(posedge rx_clk) begin
rx_cal_enable_m1 <= up_cal_enable;
rx_cal_enable <= rx_cal_enable_m1;
rx_cor_enable_t_m1 <= up_cor_enable_t;
rx_cor_enable_t_m2 <= rx_cor_enable_t_m1;
rx_cor_enable_t_m3 <= rx_cor_enable_t_m2;
end
assign rx_cor_enable_t_s = rx_cor_enable_t_m3 ^ rx_cor_enable_t_m2;
always @(posedge rx_clk) begin
if (rx_cor_enable_t_s == 1'b1) begin
rx_cor_enable <= up_cor_enable;
rx_cor_scale_0 <= up_cor_scale_0;
rx_cor_offset_0 <= up_cor_offset_0;
rx_cor_scale_1 <= up_cor_scale_1;
rx_cor_offset_1 <= up_cor_offset_1;
end
end
always @(posedge rx_clk) begin
if (rx_cor_enable == 1'b0) begin
rx_cor_scale_d_0 <= 16'h8000;
rx_cor_offset_d_0 <= 16'h0000;
rx_cor_scale_d_1 <= 16'h8000;
rx_cor_offset_d_1 <= 16'h0000;
end else begin
rx_cor_scale_d_0 <= rx_cor_scale_0;
rx_cor_offset_d_0 <= rx_cor_offset_0;
rx_cor_scale_d_1 <= rx_cor_scale_1;
rx_cor_offset_d_1 <= rx_cor_offset_1;
end
end
axi_fmcadc5_sync_calcor i_calcor (
.rx_clk (rx_clk),
.rx_enable_0 (rx_enable_0),
.rx_data_0 (rx_data_0),
.rx_enable_1 (rx_enable_1),
.rx_data_1 (rx_data_1),
.rx_enable (rx_enable),
.rx_data (rx_data),
.rx_cal_enable (rx_cal_enable),
.rx_cal_done_t (rx_cal_done_t_s),
.rx_cal_max_0 (rx_cal_max_0_s),
.rx_cal_min_0 (rx_cal_min_0_s),
.rx_cal_max_1 (rx_cal_max_1_s),
.rx_cal_min_1 (rx_cal_min_1_s),
.rx_cor_scale_0 (rx_cor_scale_d_0),
.rx_cor_offset_0 (rx_cor_offset_d_0),
.rx_cor_scale_1 (rx_cor_scale_d_1),
.rx_cor_offset_1 (rx_cor_offset_d_1));
// sysref-control at receive clock
always @(posedge rx_clk) begin
rx_sysref_cnt <= rx_sysref_cnt + 1'b1;
end
assign rx_sysref_control_t_s = rx_sysref_control_t_m3 ^ rx_sysref_control_t_m2;
assign rx_sysref_req_t_s = rx_sysref_req_t_m3 ^ rx_sysref_req_t_m2;
always @(posedge rx_clk) begin
rx_sysref_control_t_m1 <= up_sysref_control_t;
rx_sysref_control_t_m2 <= rx_sysref_control_t_m1;
rx_sysref_control_t_m3 <= rx_sysref_control_t_m2;
if (rx_sysref_control_t_s == 1'b1) begin
rx_sysref_mode_e <= up_sysref_mode_e;
rx_sysref_mode_i <= up_sysref_mode_i;
end
rx_sysref_req_t_m1 <= up_sysref_req_t;
rx_sysref_req_t_m2 <= rx_sysref_req_t_m1;
rx_sysref_req_t_m3 <= rx_sysref_req_t_m2;
if ((rx_sysref_cnt == 8'd0) || (rx_sysref_req_t_s == 1'b1)) begin
rx_sysref_req <= rx_sysref_req_t_s;
end
end
assign rx_sysref_enb_e_s = (rx_sysref_mode_e == 2'b10) ? rx_sysref_req :
((rx_sysref_mode_e == 2'b00) ? 1'b1 : 1'b0);
always @(posedge rx_clk) begin
rx_sysref_e <= rx_sysref_cnt[7] & rx_sysref_enb_e;
rx_sysref_i <= rx_sysref_cnt[7] & rx_sysref_enb_i;
if (rx_sysref_cnt == 8'd0) begin
if (rx_sysref_enb_e == 1'b1) begin
rx_sysref_ack_t <= ~rx_sysref_ack_t;
end
rx_sysref_enb_e <= rx_sysref_enb_e_s;
rx_sysref_enb_i <= ~rx_sysref_mode_i;
end
end
// sync-control at receive clock
assign rx_sync_control_t_s = rx_sync_control_t_m3 ^ rx_sync_control_t_m2;
always @(posedge rx_clk) begin
rx_sync_control_t_m1 <= up_sync_control_t;
rx_sync_control_t_m2 <= rx_sync_control_t_m1;
rx_sync_control_t_m3 <= rx_sync_control_t_m2;
if (rx_sync_control_t_s == 1'b1) begin
rx_sync_mode <= up_sync_mode;
rx_sync_disable_1 <= up_sync_disable_1;
rx_sync_disable_0 <= up_sync_disable_0;
end
if (rx_sync_mode == 1'b1) begin
rx_sync_out_1 <= ~rx_sync_disable_1 & rx_sync_1 & rx_sync_0;
rx_sync_out_0 <= ~rx_sync_disable_0 & rx_sync_1 & rx_sync_0;
end else begin
rx_sync_out_1 <= ~rx_sync_disable_1 & rx_sync_1;
rx_sync_out_0 <= ~rx_sync_disable_0 & rx_sync_0;
end
end
always @(posedge rx_clk) begin
rx_sync_cnt <= rx_sync_cnt + 1'b1;
if ((rx_sync_cnt == 8'd0) || (rx_sync_1 == 1'b0)) begin
rx_sync_hold_1 <= rx_sync_1;
end
if ((rx_sync_cnt == 8'd0) || (rx_sync_0 == 1'b0)) begin
rx_sync_hold_0 <= rx_sync_0;
end
if (rx_sync_cnt == 8'd0) begin
rx_sync_status_t <= ~rx_sync_status_t;
rx_sync_status_1 <= rx_sync_hold_1;
rx_sync_status_0 <= rx_sync_hold_0;
end
end
// sync buffers
OBUFDS i_obufds_rx_sync_1 (
.I (rx_sync_out_1),
.O (rx_sync_1_p),
.OB (rx_sync_1_n));
OBUFDS i_obufds_rx_sync_0 (
.I (rx_sync_out_0),
.O (rx_sync_0_p),
.OB (rx_sync_0_n));
// sysref delay control
assign rx_sysref = rx_sysref_i;
ad_data_out #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.SINGLE_ENDED (0),
.IODELAY_ENABLE (1),
.IODELAY_CTRL (1),
.IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_rx_sysref (
.tx_clk (rx_clk),
.tx_data_p (rx_sysref_e),
.tx_data_n (rx_sysref_e),
.tx_data_out_p (rx_sysref_p),
.tx_data_out_n (rx_sysref_n),
.up_clk (up_clk),
.up_dld (up_delay_ld),
.up_dwdata (up_delay_wdata),
.up_drdata (up_delay_rdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (up_delay_locked_s));
// up == micro("u") processor
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr
+440
View File
@@ -0,0 +1,440 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
+325
View File
@@ -0,0 +1,325 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// poor man's version of calibration & correction (scale & offset only)
// assumes linear frequency response on all discrete components
// looking for a rich man's version? fidus.com (FSF-AD15000A)
`timescale 1ns/100ps
module axi_fmcadc5_sync_calcor (
// receive interface
input rx_clk,
input rx_enable_0,
input [255:0] rx_data_0,
input rx_enable_1,
input [255:0] rx_data_1,
output rx_enable,
output [511:0] rx_data,
// calibration signals
input rx_cal_enable,
output rx_cal_done_t,
output [ 15:0] rx_cal_max_0,
output [ 15:0] rx_cal_min_0,
output [ 15:0] rx_cal_max_1,
output [ 15:0] rx_cal_min_1,
input [ 15:0] rx_cor_scale_0,
input [ 15:0] rx_cor_offset_0,
input [ 15:0] rx_cor_scale_1,
input [ 15:0] rx_cor_offset_1
);
// internal registers
reg rx_enable_int = 'd0;
reg [ 15:0] rx_cor_data_0[0:15];
reg [ 15:0] rx_cor_data_1[0:15];
reg rx_cal_done_int_t = 'd0;
reg [ 15:0] rx_cal_max_0_6 = 'd0;
reg [ 15:0] rx_cal_min_0_6 = 'd0;
reg [ 15:0] rx_cal_max_1_6 = 'd0;
reg [ 15:0] rx_cal_min_1_6 = 'd0;
reg [ 15:0] rx_cal_max_0_5 = 'd0;
reg [ 15:0] rx_cal_min_0_5 = 'd0;
reg [ 15:0] rx_cal_max_1_5 = 'd0;
reg [ 15:0] rx_cal_min_1_5 = 'd0;
reg [ 15:0] rx_cal_max_0_4[0:1];
reg [ 15:0] rx_cal_min_0_4[0:1];
reg [ 15:0] rx_cal_max_1_4[0:1];
reg [ 15:0] rx_cal_min_1_4[0:1];
reg [ 15:0] rx_cal_max_0_3[0:3];
reg [ 15:0] rx_cal_min_0_3[0:3];
reg [ 15:0] rx_cal_max_1_3[0:3];
reg [ 15:0] rx_cal_min_1_3[0:3];
reg [ 15:0] rx_cal_max_0_2[0:7];
reg [ 15:0] rx_cal_min_0_2[0:7];
reg [ 15:0] rx_cal_max_1_2[0:7];
reg [ 15:0] rx_cal_min_1_2[0:7];
reg [ 15:0] rx_cal_max_0_1[0:15];
reg [ 15:0] rx_cal_min_0_1[0:15];
reg [ 15:0] rx_cal_max_1_1[0:15];
reg [ 15:0] rx_cal_min_1_1[0:15];
// internal signals
wire [ 33:0] rx_cor_data_0_s[0:15];
wire [ 33:0] rx_cor_data_1_s[0:15];
wire [ 15:0] rx_data_0_s[0:15];
wire [ 15:0] rx_data_1_s[0:15];
// iterations
genvar n;
// offset & gain
assign rx_enable = rx_enable_int;
always @(posedge rx_clk) begin
rx_enable_int = rx_enable_0 & rx_enable_1;
end
generate
for (n = 0; n <= 15; n = n + 1) begin: g_rx_cal_data
assign rx_data[((n*32)+15):((n*32)+ 0)] = rx_cor_data_0_s[n][30:15];
assign rx_data[((n*32)+31):((n*32)+16)] = rx_cor_data_1_s[n][30:15];
end
endgenerate
// gain
generate
for (n = 0; n <= 15; n = n + 1) begin: g_rx_gain
ad_mul #(
.DELAY_DATA_WIDTH(1)
) i_rx_gain_0 (
.clk (rx_clk),
.data_a ({rx_cor_data_0[n][15], rx_cor_data_0[n]}),
.data_b ({1'b0, rx_cor_scale_0}),
.data_p (rx_cor_data_0_s[n]),
.ddata_in (1'd0),
.ddata_out ());
ad_mul #(
.DELAY_DATA_WIDTH(1)
) i_rx_gain_1 (
.clk (rx_clk),
.data_a ({rx_cor_data_1[n][15], rx_cor_data_1[n]}),
.data_b ({1'b0, rx_cor_scale_1}),
.data_p (rx_cor_data_1_s[n]),
.ddata_in (1'd0),
.ddata_out ());
end
endgenerate
// offset
generate
for (n = 0; n <= 15; n = n + 1) begin: g_rx_offset
always @(posedge rx_clk) begin
rx_cor_data_0[n] <= rx_data_0_s[n] + rx_cor_offset_0;
rx_cor_data_1[n] <= rx_data_1_s[n] + rx_cor_offset_1;
end
end
endgenerate
// calibration peaks (average would be better)
assign rx_cal_done_t = rx_cal_done_int_t;
assign rx_cal_max_0 = rx_cal_max_0_6;
assign rx_cal_min_0 = rx_cal_min_0_6;
assign rx_cal_max_1 = rx_cal_max_1_6;
assign rx_cal_min_1 = rx_cal_min_1_6;
always @(posedge rx_clk) begin
if (rx_cal_enable == 1'b1) begin
rx_cal_done_int_t <= ~rx_cal_done_int_t;
rx_cal_max_0_6 <= rx_cal_max_0_5;
rx_cal_min_0_6 <= rx_cal_min_0_5;
rx_cal_max_1_6 <= rx_cal_max_1_5;
rx_cal_min_1_6 <= rx_cal_min_1_5;
end
end
// run-time peaks
always @(posedge rx_clk) begin
if (rx_cal_max_0_4[1] > rx_cal_max_0_4[0]) begin
rx_cal_max_0_5 <= rx_cal_max_0_4[1];
end else begin
rx_cal_max_0_5 <= rx_cal_max_0_4[0];
end
if (rx_cal_min_0_4[1] < rx_cal_min_0_4[0]) begin
rx_cal_min_0_5 <= rx_cal_min_0_4[1];
end else begin
rx_cal_min_0_5 <= rx_cal_min_0_4[0];
end
if (rx_cal_max_1_4[1] > rx_cal_max_1_4[0]) begin
rx_cal_max_1_5 <= rx_cal_max_1_4[1];
end else begin
rx_cal_max_1_5 <= rx_cal_max_1_4[0];
end
if (rx_cal_min_1_4[1] < rx_cal_min_1_4[0]) begin
rx_cal_min_1_5 <= rx_cal_min_1_4[1];
end else begin
rx_cal_min_1_5 <= rx_cal_min_1_4[0];
end
end
// peak iterations
generate
for (n = 0; n <= 1; n = n + 1) begin: g_rx_peak_4
always @(posedge rx_clk) begin
if (rx_cal_max_0_3[((n*2)+1)] > rx_cal_max_0_3[(n*2)]) begin
rx_cal_max_0_4[n] <= rx_cal_max_0_3[((n*2)+1)];
end else begin
rx_cal_max_0_4[n] <= rx_cal_max_0_3[(n*2)];
end
if (rx_cal_min_0_3[((n*2)+1)] < rx_cal_min_0_3[(n*2)]) begin
rx_cal_min_0_4[n] <= rx_cal_min_0_3[((n*2)+1)];
end else begin
rx_cal_min_0_4[n] <= rx_cal_min_0_3[(n*2)];
end
if (rx_cal_max_1_3[((n*2)+1)] > rx_cal_max_1_3[(n*2)]) begin
rx_cal_max_1_4[n] <= rx_cal_max_1_3[((n*2)+1)];
end else begin
rx_cal_max_1_4[n] <= rx_cal_max_1_3[(n*2)];
end
if (rx_cal_min_1_3[((n*2)+1)] < rx_cal_min_1_3[(n*2)]) begin
rx_cal_min_1_4[n] <= rx_cal_min_1_3[((n*2)+1)];
end else begin
rx_cal_min_1_4[n] <= rx_cal_min_1_3[(n*2)];
end
end
end
endgenerate
generate
for (n = 0; n <= 3; n = n + 1) begin: g_rx_peak_3
always @(posedge rx_clk) begin
if (rx_cal_max_0_2[((n*2)+1)] > rx_cal_max_0_2[(n*2)]) begin
rx_cal_max_0_3[n] <= rx_cal_max_0_2[((n*2)+1)];
end else begin
rx_cal_max_0_3[n] <= rx_cal_max_0_2[(n*2)];
end
if (rx_cal_min_0_2[((n*2)+1)] < rx_cal_min_0_2[(n*2)]) begin
rx_cal_min_0_3[n] <= rx_cal_min_0_2[((n*2)+1)];
end else begin
rx_cal_min_0_3[n] <= rx_cal_min_0_2[(n*2)];
end
if (rx_cal_max_1_2[((n*2)+1)] > rx_cal_max_1_2[(n*2)]) begin
rx_cal_max_1_3[n] <= rx_cal_max_1_2[((n*2)+1)];
end else begin
rx_cal_max_1_3[n] <= rx_cal_max_1_2[(n*2)];
end
if (rx_cal_min_1_2[((n*2)+1)] < rx_cal_min_1_2[(n*2)]) begin
rx_cal_min_1_3[n] <= rx_cal_min_1_2[((n*2)+1)];
end else begin
rx_cal_min_1_3[n] <= rx_cal_min_1_2[(n*2)];
end
end
end
endgenerate
generate
for (n = 0; n <= 7; n = n + 1) begin: g_rx_peak_2
always @(posedge rx_clk) begin
if (rx_cal_max_0_1[((n*2)+1)] > rx_cal_max_0_1[(n*2)]) begin
rx_cal_max_0_2[n] <= rx_cal_max_0_1[((n*2)+1)];
end else begin
rx_cal_max_0_2[n] <= rx_cal_max_0_1[(n*2)];
end
if (rx_cal_min_0_1[((n*2)+1)] < rx_cal_min_0_1[(n*2)]) begin
rx_cal_min_0_2[n] <= rx_cal_min_0_1[((n*2)+1)];
end else begin
rx_cal_min_0_2[n] <= rx_cal_min_0_1[(n*2)];
end
if (rx_cal_max_1_1[((n*2)+1)] > rx_cal_max_1_1[(n*2)]) begin
rx_cal_max_1_2[n] <= rx_cal_max_1_1[((n*2)+1)];
end else begin
rx_cal_max_1_2[n] <= rx_cal_max_1_1[(n*2)];
end
if (rx_cal_min_1_1[((n*2)+1)] < rx_cal_min_1_1[(n*2)]) begin
rx_cal_min_1_2[n] <= rx_cal_min_1_1[((n*2)+1)];
end else begin
rx_cal_min_1_2[n] <= rx_cal_min_1_1[(n*2)];
end
end
end
endgenerate
generate
for (n = 0; n <= 15; n = n + 1) begin: g_rx_peak_1
always @(posedge rx_clk) begin
if (rx_cal_enable == 1'b0) begin
rx_cal_max_0_1[n] <= 16'h0000;
end else if ((rx_data_0_s[n] > rx_cal_max_0_1[n]) &&
(rx_data_0_s[n][15] == 1'b0)) begin
rx_cal_max_0_1[n] <= rx_data_0_s[n];
end
if (rx_cal_enable == 1'b0) begin
rx_cal_min_0_1[n] <= 16'hffff;
end else if ((rx_data_0_s[n] < rx_cal_min_0_1[n]) &&
(rx_data_0_s[n][15] == 1'b1)) begin
rx_cal_min_0_1[n] <= rx_data_0_s[n];
end
if (rx_cal_enable == 1'b0) begin
rx_cal_max_1_1[n] <= 16'h0000;
end else if ((rx_data_1_s[n] > rx_cal_max_1_1[n]) &&
(rx_data_1_s[n][15] == 1'b0)) begin
rx_cal_max_1_1[n] <= rx_data_1_s[n];
end
if (rx_cal_enable == 1'b0) begin
rx_cal_min_1_1[n] <= 16'hffff;
end else if ((rx_data_1_s[n] < rx_cal_min_1_1[n]) &&
(rx_data_1_s[n][15] == 1'b1)) begin
rx_cal_min_1_1[n] <= rx_data_1_s[n];
end
end
end
endgenerate
generate
for (n = 0; n <= 15; n = n + 1) begin: g_rx_data
assign rx_data_0_s[n] = {{4{rx_data_0[((n*16)+11)]}}, rx_data_0[((n*16)+11):(n*16)]};
assign rx_data_1_s[n] = {{4{rx_data_1[((n*16)+11)]}}, rx_data_1[((n*16)+11):(n*16)]};
end
endgenerate
endmodule
adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc
+50
View File
@@ -0,0 +1,50 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_cal_done_t_m1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sysref_ack_t_m1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_status_t_m1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_status_1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_status_0* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_cal_enable_m1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_cor_enable_t_m1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_control_t_m1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_mode_e* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_mode_i* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_req_t_m1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_control_t_m1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_mode* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_cal_done_t_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_cal_max_0* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_cal_min_0* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_cal_max_1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_cal_min_1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_sysref_ack_t_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_sync_status_t_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_sync_status_1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_sync_status_0* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_cal_enable_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_enable_t_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_enable* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_scale_0* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_offset_0* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_scale_1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_offset_1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_control_t_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_mode_e* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_mode_i* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_req_t_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_control_t_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_mode* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}]
# Define spi clock
create_generated_clock -name forwarded_spi_clk \
-source [get_pins -hier up_spi_clk_int_reg/C] \
-divide_by 2 [get_pins -hier up_spi_clk_int_reg/Q]
adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
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###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_fmcadc5_sync
adi_ip_files axi_fmcadc5_sync [list \
"$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_fmcadc5_sync_constr.xdc" \
"axi_fmcadc5_sync_calcor.v" \
"axi_fmcadc5_sync.v" ]
adi_ip_properties axi_fmcadc5_sync
adi_init_bd_tcl
adi_ip_bd axi_fmcadc5_sync "bd/bd.tcl"
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface delay_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/axi_fmcadc5_sync/bd/bd.tcl
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# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
DEV_PACKAGE \
SPEED_GRADE \
FPGA_FAMILY \
FPGA_TECHNOLOGY"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
adi_library/axi_fmcadc5_sync/component.xml
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adi_library/axi_fmcadc5_sync/temporary_case_dependencies.mk
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CLEAN_TARGET += bd
CLEAN_TARGET += temporary_case_dependencies.mk
adi_library/axi_fmcadc5_sync/xgui/axi_fmcadc5_sync_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0}
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
#Adding Group
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
}
proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
# Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
# Procedure called to validate DELAY_REFCLK_FREQUENCY
return true
}
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to validate DEV_PACKAGE
return true
}
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to validate FPGA_FAMILY
return true
}
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to validate FPGA_TECHNOLOGY
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to validate SPEED_GRADE
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
}
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
}
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
}
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
}
proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY}
}