initial commit, add dds_par module
This commit is contained in:
@@ -0,0 +1,977 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:name>s_axi_awvalid</spirit:name>
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<spirit:name>s_axi_rready</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_arvalid</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_arprot</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
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|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_arready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_rvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_rresp</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_rdata</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>s_axi_rready</spirit:name>
|
||||
<spirit:wire>
|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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||||
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|
||||
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|
||||
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|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
|
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||||
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||||
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||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
<spirit:name>tia_chsel</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
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||||
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|
||||
<spirit:left spirit:format="long">7</spirit:left>
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||||
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||||
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|
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<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
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||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>irq</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
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||||
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
<spirit:name>ID</spirit:name>
|
||||
<spirit:displayName>Id</spirit:displayName>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>ASYNC_CLK_EN</spirit:name>
|
||||
<spirit:displayName>Async Clk En</spirit:displayName>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>PULSE_WIDTH</spirit:name>
|
||||
<spirit:displayName>Pulse Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_WIDTH">7</spirit:value>
|
||||
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|
||||
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|
||||
<spirit:name>PULSE_PERIOD</spirit:name>
|
||||
<spirit:displayName>Pulse Period</spirit:displayName>
|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
<spirit:name>choice_list_74b5137e</spirit:name>
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
<spirit:name>../axi_pulse_gen/axi_pulse_gen_constr.ttcl</spirit:name>
|
||||
<spirit:userFileType>ttcl</spirit:userFileType>
|
||||
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|
||||
<spirit:file>
|
||||
<spirit:name>../xilinx/common/up_clock_mon_constr.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_laser_driver_constr.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_laser_driver_regmap.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
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|
||||
<spirit:file>
|
||||
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|
||||
<spirit:fileType>verilogSource</spirit:fileType>
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||||
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|
||||
<spirit:file>
|
||||
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||||
<spirit:fileType>verilogSource</spirit:fileType>
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||||
<spirit:userFileType>CHECKSUM_8a5a13b8</spirit:userFileType>
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|
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|
||||
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Reference in New Issue
Block a user