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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/axi_logic_analyzer/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_logic_analyzer
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_logic_analyzer.v
GENERIC_DEPS += axi_logic_analyzer_reg.v
GENERIC_DEPS += axi_logic_analyzer_trigger.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_logic_analyzer_constr.xdc
XILINX_DEPS += axi_logic_analyzer_ip.tcl
include ../scripts/library.mk
adi_library/axi_logic_analyzer/axi_logic_analyzer.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_logic_analyzer (
// interface
input clk,
output clk_out,
input [15:0] data_i,
output reg [15:0] data_o,
output [15:0] data_t,
input [ 1:0] trigger_i,
output adc_valid,
output reg [15:0] adc_data,
input [15:0] dac_data,
input dac_valid,
output reg dac_read,
input [ 2:0] external_rate,
input external_valid,
input external_decimation_en,
input trigger_in,
output trigger_out,
output trigger_out_adc,
output [31:0] fifo_depth,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 6:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 6:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready
);
// internal registers
reg [15:0] data_r = 'd0;
reg [ 1:0] trigger_m1 = 'd0;
reg [31:0] downsampler_counter_la = 'd0;
reg [31:0] upsampler_counter_pg = 'd0;
reg sample_valid_la = 'd0;
reg [15:0] io_selection; // 1 - input, 0 - output
reg [31:0] delay_counter = 'd0;
reg triggered = 'd0;
reg up_triggered;
reg up_triggered_d1;
reg up_triggered_d2;
reg up_triggered_set;
reg up_triggered_reset;
reg up_triggered_reset_d1;
reg up_triggered_reset_d2;
reg streaming_on;
reg [ 1:0] trigger_i_m1 = 2'd0;
reg [ 1:0] trigger_i_m2 = 2'd0;
reg [ 1:0] trigger_i_m3 = 2'd0;
reg trigger_adc_m1 = 1'd0;
reg trigger_adc_m2 = 1'd0;
reg trigger_la_m2 = 1'd0;
reg pg_trigered = 1'd0;
reg [ 1:0] any_edge_trigger = 1'd0;
reg [ 1:0] rise_edge_trigger = 1'd0;
reg [ 1:0] fall_edge_trigger = 1'd0;
reg [ 1:0] high_level_trigger = 1'd0;
reg [ 1:0] low_level_trigger = 1'd0;
reg [31:0] trigger_holdoff_counter = 32'd0;
reg [ 3:0] adc_data_delay = 4'd0;
reg [16:0] data_fixed_delay [0:15];
reg [15:0] data_dynamic_delay [0:15];
// internal signals
wire up_clk;
wire up_rstn;
wire [ 4:0] up_waddr;
wire [31:0] up_wdata;
wire up_wack;
wire up_wreq;
wire up_rack;
wire [31:0] up_rdata;
wire up_rreq;
wire [ 4:0] up_raddr;
wire reset;
wire [31:0] divider_counter_la;
wire [31:0] divider_counter_pg;
wire [17:0] edge_detect_enable;
wire [17:0] rise_edge_enable;
wire [17:0] fall_edge_enable;
wire [17:0] low_level_enable;
wire [17:0] high_level_enable;
wire [ 6:0] trigger_logic; // 0-OR,1-AND
wire clock_select;
wire [15:0] overwrite_enable;
wire [15:0] overwrite_data;
wire [15:0] io_selection_s; // 1 - input, 0 - output
wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain
wire trigger_out_s;
wire [31:0] trigger_delay;
wire trigger_out_delayed;
wire [19:0] pg_trigger_config;
wire [ 1:0] pg_en_trigger_pins;
wire pg_en_trigger_adc;
wire pg_en_trigger_la;
wire [ 1:0] pg_low_level;
wire [ 1:0] pg_high_level;
wire [ 1:0] pg_any_edge;
wire [ 1:0] pg_rise_edge;
wire [ 1:0] pg_fall_edge;
wire [31:0] trigger_holdoff;
wire trigger_out_holdoff;
wire streaming;
wire [ 3:0] in_data_delay;
wire [ 3:0] up_data_delay;
wire master_delay_ctrl;
wire [ 9:0] data_delay_control;
wire [15:0] adc_data_mn;
genvar i;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign trigger_out = trigger_delay == 32'h0 ? trigger_out_holdoff | streaming_on : trigger_out_delayed | streaming_on;
assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
always @(posedge clk_out) begin
if (trigger_delay == 0) begin
if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin
streaming_on <= 1'b1;
end else if (streaming == 1'b0) begin
streaming_on <= 1'b0;
end
end else begin
if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_delayed == 1'b1) begin
streaming_on <= 1'b1;
end else if (streaming == 1'b0) begin
streaming_on <= 1'b0;
end
end
end
always @(posedge clk_out) begin
if (sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin
up_triggered_set <= 1'b1;
end else if (up_triggered_reset == 1'b1) begin
up_triggered_set <= 1'b0;
end
up_triggered_reset_d1 <= up_triggered;
up_triggered_reset_d2 <= up_triggered_reset_d1;
up_triggered_reset <= up_triggered_reset_d2;
end
always @(posedge up_clk) begin
up_triggered_d1 <= up_triggered_set;
up_triggered_d2 <= up_triggered_d1;
up_triggered <= up_triggered_d2;
end
generate
for (i = 0 ; i < 16; i = i + 1) begin
assign data_t[i] = od_pp_n[i] ? io_selection[i] | data_o[i] : io_selection[i];
always @(posedge clk_out) begin
data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
end
always @(posedge clk_out) begin
if(dac_valid == 1'b1) begin
data_r[i] <= dac_data[i];
end
if (io_selection_s[i] == 1'b1) begin
io_selection[i] <= 1'b1;
end else begin
if(dac_valid == 1'b1 || overwrite_enable[i] == 1'b1) begin
io_selection[i] <= 1'b0;
end
end
end
end
endgenerate
BUFGMUX_CTRL BUFGMUX_CTRL_inst (
.O (clk_out),
.I0 (clk),
.I1 (data_i[0]),
.S (clock_select));
// - synchronization
// - compensate for m2k adc path delay
// 17 clock cycles delay
generate
for (i = 0 ; i < 16; i = i + 1) begin
always @(posedge clk_out) begin
if (reset == 1'b1) begin
data_fixed_delay[i] <= 'd0;
end else begin
data_fixed_delay[i] <= {data_fixed_delay[i][15:0], data_i[i]};
end
end
end
// dynamic sample delay (1 to 16)
for (i = 0 ; i < 16; i = i + 1) begin
always @(posedge clk_out) begin
if (sample_valid_la == 1'b1) begin
data_dynamic_delay[i] <= {data_dynamic_delay[i][14:0], data_fixed_delay[i][16]};
end
end
assign adc_data_mn[i] = data_dynamic_delay[i][in_data_delay[3:0]];
end
endgenerate
// adc path 'rate delay' given by axi_adc_decimate
always @(posedge clk_out) begin
case (external_rate)
3'd0: adc_data_delay <= 4'd1; // 100MSPS
3'd1: adc_data_delay <= 4'd3; // 10MSPS
default: adc_data_delay <= 4'd1; // <= 1MSPS
endcase
end
assign up_data_delay = data_delay_control[3:0];
assign rate_gen_select = data_delay_control[8];
// select if the delay taps number is chosen by the user or automatically
assign master_delay_ctrl = data_delay_control[9];
assign in_data_delay = master_delay_ctrl ? up_data_delay :
external_decimation_en ? 4'd0 : adc_data_delay;
always @(posedge clk_out) begin
if (sample_valid_la == 1'b1) begin
adc_data <= adc_data_mn;
end
end
assign adc_valid = sample_valid_la;
always @(posedge clk_out) begin
trigger_m1 <= trigger_i;
end
// downsampler logic analyzer
always @(posedge clk_out) begin
if (reset == 1'b1) begin
sample_valid_la <= 1'b0;
downsampler_counter_la <= 32'h0;
end else begin
if (rate_gen_select) begin
downsampler_counter_la <= 32'h0;
sample_valid_la <= external_valid;
end else if (downsampler_counter_la < divider_counter_la ) begin
downsampler_counter_la <= downsampler_counter_la + 1;
sample_valid_la <= 1'b0;
end else begin
downsampler_counter_la <= 32'h0;
sample_valid_la <= 1'b1;
end
end
end
// pattern generator instrument triggering
assign pg_any_edge = pg_trigger_config[1:0];
assign pg_rise_edge = pg_trigger_config[3:2];
assign pg_fall_edge = pg_trigger_config[5:4];
assign pg_low_level = pg_trigger_config[7:6];
assign pg_high_level = pg_trigger_config[9:8];
assign pg_en_trigger_pins = pg_trigger_config[17:16];
assign pg_en_trigger_adc = pg_trigger_config[18];
assign pg_en_trigger_la = pg_trigger_config[19];
assign trigger_active = |pg_trigger_config[19:16];
assign trigger = (ext_trigger & pg_en_trigger_pins) |
(trigger_adc_m2 & pg_en_trigger_adc) |
(trigger_out_s & pg_en_trigger_la);
assign ext_trigger = |(any_edge_trigger |
rise_edge_trigger |
fall_edge_trigger |
high_level_trigger |
low_level_trigger);
// sync
always @(posedge clk) begin
trigger_i_m1 <= trigger_i;
trigger_i_m2 <= trigger_i_m1;
trigger_i_m3 <= trigger_i_m2;
trigger_adc_m1 <= trigger_in;
trigger_adc_m2 <= trigger_adc_m1;
end
always @(posedge clk) begin
any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & pg_any_edge;
rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & pg_rise_edge;
fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & pg_fall_edge;
high_level_trigger <= trigger_i_m3 & pg_high_level;
low_level_trigger <= ~trigger_i_m3 & pg_low_level;
end
// upsampler pattern generator
always @(posedge clk_out) begin
if (reset == 1'b1) begin
upsampler_counter_pg <= 32'h0;
dac_read <= 1'b0;
end else begin
dac_read <= 1'b0;
pg_trigered <= trigger_active ? (trigger | pg_trigered) : 1'b0;
if (trigger_active & !pg_trigered) begin
upsampler_counter_pg <= 32'h0;
dac_read <= 1'b0;
end else if (upsampler_counter_pg < divider_counter_pg) begin
upsampler_counter_pg <= upsampler_counter_pg + 1;
end else begin
upsampler_counter_pg <= 32'h0;
dac_read <= 1'b1;
end
end
end
always @(posedge clk_out) begin
if(trigger_delay == 32'h0) begin
delay_counter <= 32'h0;
end else begin
if (adc_valid == 1'b1) begin
triggered <= trigger_out_holdoff | triggered;
if (delay_counter == 32'h0) begin
delay_counter <= trigger_delay;
triggered <= 1'b0;
end else begin
if(triggered == 1'b1 || trigger_out_holdoff == 1'b1) begin
delay_counter <= delay_counter - 1;
end
end
end
end
end
// hold off trigger
assign trigger_out_holdoff = (trigger_holdoff_counter != 0) ? 0 : trigger_out_s;
assign holdoff_cnt_en = |trigger_holdoff;
always @(posedge clk) begin
if (reset == 1'b1) begin
trigger_holdoff_counter <= 0;
end else begin
if (trigger_holdoff_counter != 0) begin
trigger_holdoff_counter <= trigger_holdoff_counter - 1'b1;
end else if (trigger_out_holdoff == 1'b1) begin
trigger_holdoff_counter <= trigger_holdoff;
end else begin
trigger_holdoff_counter <= trigger_holdoff_counter;
end
end
end
axi_logic_analyzer_trigger i_trigger (
.clk (clk_out),
.reset (reset),
.data (adc_data_mn),
.data_valid(sample_valid_la),
.trigger_i (trigger_m1),
.trigger_in (trigger_in),
.edge_detect_enable (edge_detect_enable),
.rise_edge_enable (rise_edge_enable),
.fall_edge_enable (fall_edge_enable),
.low_level_enable (low_level_enable),
.high_level_enable (high_level_enable),
.trigger_logic (trigger_logic),
.trigger_out_adc (trigger_out_adc),
.trigger_out (trigger_out_s));
axi_logic_analyzer_reg i_registers (
.clk (clk_out),
.reset (reset),
.divider_counter_la (divider_counter_la),
.divider_counter_pg (divider_counter_pg),
.io_selection (io_selection_s),
.edge_detect_enable (edge_detect_enable),
.rise_edge_enable (rise_edge_enable),
.fall_edge_enable (fall_edge_enable),
.low_level_enable (low_level_enable),
.high_level_enable (high_level_enable),
.fifo_depth (fifo_depth),
.trigger_delay (trigger_delay),
.trigger_holdoff (trigger_holdoff),
.trigger_logic (trigger_logic),
.clock_select (clock_select),
.overwrite_enable (overwrite_enable),
.overwrite_data (overwrite_data),
.input_data (adc_data_mn),
.od_pp_n (od_pp_n),
.triggered (up_triggered),
.pg_trigger_config (pg_trigger_config),
.streaming(streaming),
.data_delay_control (data_delay_control),
// bus interface
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
// axi interface
up_axi #(
.AXI_ADDRESS_WIDTH(7)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
adi_library/axi_logic_analyzer/axi_logic_analyzer.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_logic_analyzer/axi_logic_analyzer.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="064d702b8d7042568c313ac549b03a87"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../common/ad_rst.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_logic_analyzer_reg.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_logic_analyzer_trigger.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_axi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_xfer_cntrl.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_xfer_status.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_logic_analyzer.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_logic_analyzer"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../xilinx/common/up_xfer_cntrl_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../xilinx/common/up_xfer_status_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_logic_analyzer_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc
+15
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@@ -0,0 +1,15 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *data_fixed_delay*}]
set_false_path -to [get_pins BUFGMUX_CTRL_inst/S*]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *data_fixed_delay* && IS_SEQUENTIAL}]
adi_library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl
+32
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@@ -0,0 +1,32 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_logic_analyzer
adi_ip_files axi_logic_analyzer [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"axi_logic_analyzer_constr.xdc" \
"axi_logic_analyzer_reg.v" \
"axi_logic_analyzer_trigger.v" \
"axi_logic_analyzer.v" ]
adi_ip_properties axi_logic_analyzer
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_logic_analyzer} [ipx::current_core]
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface clk_out xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/axi_logic_analyzer/axi_logic_analyzer_reg.v
+314
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@@ -0,0 +1,314 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_logic_analyzer_reg (
input clk,
output reset,
output [31:0] divider_counter_la,
output [31:0] divider_counter_pg,
output [15:0] io_selection,
output [17:0] edge_detect_enable,
output [17:0] rise_edge_enable,
output [17:0] fall_edge_enable,
output [17:0] low_level_enable,
output [17:0] high_level_enable,
output [31:0] fifo_depth,
output [31:0] trigger_delay,
output [ 6:0] trigger_logic,
output clock_select,
output [15:0] overwrite_enable,
output [15:0] overwrite_data,
input [15:0] input_data,
output [15:0] od_pp_n,
output [31:0] trigger_holdoff,
output [19:0] pg_trigger_config,
input triggered,
output streaming,
output [ 9:0] data_delay_control,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 4:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 4:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack
);
// internal registers
reg [31:0] up_version = 32'h00020100;
reg [31:0] up_scratch = 0;
reg [31:0] up_divider_counter_la = 0;
reg [31:0] up_divider_counter_pg = 0;
reg [15:0] up_io_selection = 16'h0;
reg [17:0] up_edge_detect_enable = 0;
reg [17:0] up_rise_edge_enable = 0;
reg [17:0] up_fall_edge_enable = 0;
reg [17:0] up_low_level_enable = 0;
reg [17:0] up_high_level_enable = 0;
reg [31:0] up_fifo_depth = 0;
reg [31:0] up_trigger_delay = 0;
reg [ 6:0] up_trigger_logic = 0;
reg up_clock_select = 0;
reg [15:0] up_overwrite_enable = 0;
reg [15:0] up_overwrite_data = 0;
reg [15:0] up_od_pp_n = 0;
reg [31:0] up_trigger_holdoff = 32'h0;
reg [19:0] up_pg_trigger_config = 20'h0;
reg up_triggered = 0;
reg up_streaming = 0;
reg [ 9:0] up_data_delay_control = 10'd0;
wire [15:0] up_input_data;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_divider_counter_la <= 'd0;
up_divider_counter_pg <= 'd0;
up_edge_detect_enable <= 'd0;
up_rise_edge_enable <= 'd0;
up_fall_edge_enable <= 'd0;
up_low_level_enable <= 'd0;
up_high_level_enable <= 'd0;
up_fifo_depth <= 'd0;
up_trigger_delay <= 'd0;
up_trigger_logic <= 'd0;
up_clock_select <= 'd0;
up_overwrite_enable <= 'd0;
up_overwrite_data <= 'd0;
up_io_selection <= 16'h0;
up_od_pp_n <= 16'h0;
up_triggered <= 1'd0;
up_streaming <= 1'd0;
up_trigger_holdoff <= 32'h0;
up_pg_trigger_config <= 20'd0;
up_data_delay_control <= 10'h0;
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
up_scratch <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
up_divider_counter_la <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
up_divider_counter_pg <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
up_io_selection <= up_wdata[15:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
up_edge_detect_enable <= up_wdata[17:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h6)) begin
up_rise_edge_enable <= up_wdata[17:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h7)) begin
up_fall_edge_enable <= up_wdata[17:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h8)) begin
up_low_level_enable <= up_wdata[17:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h9)) begin
up_high_level_enable <= up_wdata[17:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
up_fifo_depth <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
up_trigger_logic <= up_wdata[6:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hc)) begin
up_clock_select <= up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hd)) begin
up_overwrite_enable <= up_wdata[15:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin
up_overwrite_data <= up_wdata[15:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_od_pp_n <= up_wdata[15:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_trigger_delay <= up_wdata;
end
if (triggered == 1'b1) begin
up_triggered <= 1'b1;
end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
up_triggered <= up_triggered & ~up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
up_streaming <= up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
up_trigger_holdoff <= up_wdata[31:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin
up_pg_trigger_config <= up_wdata[19:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h16)) begin
up_data_delay_control <= up_wdata[9:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr[4:0])
5'h0: up_rdata <= up_version;
5'h1: up_rdata <= up_scratch;
5'h2: up_rdata <= up_divider_counter_la;
5'h3: up_rdata <= up_divider_counter_pg;
5'h4: up_rdata <= {16'h0,up_io_selection};
5'h5: up_rdata <= {14'h0,up_edge_detect_enable};
5'h6: up_rdata <= {14'h0,up_rise_edge_enable};
5'h7: up_rdata <= {14'h0,up_fall_edge_enable};
5'h8: up_rdata <= {14'h0,up_low_level_enable};
5'h9: up_rdata <= {14'h0,up_high_level_enable};
5'ha: up_rdata <= up_fifo_depth;
5'hb: up_rdata <= {25'h0,up_trigger_logic};
5'hc: up_rdata <= {31'h0,up_clock_select};
5'hd: up_rdata <= {16'h0,up_overwrite_enable};
5'he: up_rdata <= {16'h0,up_overwrite_data};
5'hf: up_rdata <= {16'h0,up_input_data};
5'h10: up_rdata <= {16'h0,up_od_pp_n};
5'h11: up_rdata <= up_trigger_delay;
5'h12: up_rdata <= {31'h0,up_triggered};
5'h13: up_rdata <= {31'h0,up_streaming};
5'h14: up_rdata <= up_trigger_holdoff;
5'h15: up_rdata <= {12'h0,up_pg_trigger_config};
5'h16: up_rdata <= {22'h0,up_data_delay_control};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
ad_rst i_core_rst_reg (
.rst_async(~up_rstn),
.clk(clk),
.rstn(),
.rst(reset));
up_xfer_cntrl #(
.DATA_WIDTH(353)
) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_streaming, // 1
up_od_pp_n, // 16
up_overwrite_data, // 16
up_overwrite_enable, // 16
up_clock_select, // 1
up_trigger_logic, // 7
up_fifo_depth, // 32
up_trigger_delay, // 32
up_trigger_holdoff, // 32
up_high_level_enable, // 18
up_low_level_enable, // 18
up_fall_edge_enable, // 18
up_rise_edge_enable, // 18
up_edge_detect_enable, // 18
up_io_selection, // 16
up_pg_trigger_config, // 20
up_divider_counter_pg, // 32
up_divider_counter_la, // 32
up_data_delay_control}), // 10
.up_xfer_done (),
.d_rst (1'b0),
.d_clk (clk),
.d_data_cntrl ({ streaming, // 1
od_pp_n, // 16
overwrite_data, // 16
overwrite_enable, // 16
clock_select, // 1
trigger_logic, // 7
fifo_depth, // 32
trigger_delay, // 32
trigger_holdoff, // 32
high_level_enable, // 18
low_level_enable, // 18
fall_edge_enable, // 18
rise_edge_enable, // 18
edge_detect_enable, // 18
io_selection, // 16
pg_trigger_config, // 20
divider_counter_pg, // 32
divider_counter_la, // 32
data_delay_control})); // 10
up_xfer_status #(
.DATA_WIDTH(16)
) i_xfer_status (
// up interface
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_status(up_input_data),
// device interface
.d_rst(1'd0),
.d_clk(clk),
.d_data_status(input_data));
endmodule
adi_library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
+187
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_logic_analyzer_trigger (
input clk,
input reset,
input [15:0] data,
input data_valid,
input [ 1:0] trigger_i,
input trigger_in,
input [17:0] edge_detect_enable,
input [17:0] rise_edge_enable,
input [17:0] fall_edge_enable,
input [17:0] low_level_enable,
input [17:0] high_level_enable,
input [ 6:0] trigger_logic,
output reg trigger_out,
output reg trigger_out_adc
);
reg [ 1:0] ext_t_m = 'd0;
reg [ 1:0] ext_t_low_level_hold = 'd0;
reg [ 1:0] ext_t_high_level_hold = 'd0;
reg [ 1:0] ext_t_edge_detect_hold = 'd0;
reg [ 1:0] ext_t_rise_edge_hold = 'd0;
reg [ 1:0] ext_t_fall_edge_hold = 'd0;
reg ext_t_low_level_ack = 'd0;
reg ext_t_high_level_ack = 'd0;
reg ext_t_edge_detect_ack = 'd0;
reg ext_t_rise_edge_ack = 'd0;
reg ext_t_fall_edge_ack = 'd0;
reg [ 15:0] data_m1 = 'd0;
reg [ 15:0] low_level = 'd0;
reg [ 15:0] high_level = 'd0;
reg [ 15:0] edge_detect = 'd0;
reg [ 15:0] rise_edge = 'd0;
reg [ 15:0] fall_edge = 'd0;
reg [ 15:0] low_level_m = 'd0;
reg [ 15:0] high_level_m = 'd0;
reg [ 15:0] edge_detect_m = 'd0;
reg [ 15:0] rise_edge_m = 'd0;
reg [ 15:0] fall_edge_m = 'd0;
reg trigger_active;
reg trigger_active_mux;
reg trigger_active_d1;
always @(posedge clk) begin
if (data_valid == 1'b1) begin
trigger_active_d1 <= trigger_active_mux;
trigger_out <= trigger_active_d1;
trigger_out_adc <= trigger_active_mux;
end
end
// trigger logic:
// 0 OR
// 1 AND
always @(posedge clk) begin
if (data_valid == 1'b1) begin
case (trigger_logic[0])
0: trigger_active = |(({ext_t_edge_detect_hold, edge_detect_m} & edge_detect_enable) |
({ext_t_rise_edge_hold, rise_edge_m} & rise_edge_enable) |
({ext_t_fall_edge_hold, fall_edge_m} & fall_edge_enable) |
({ext_t_low_level_hold, low_level_m} & low_level_enable) |
({ext_t_high_level_hold , high_level_m} & high_level_enable));
1: trigger_active = &(({ext_t_edge_detect_hold, edge_detect_m} | ~edge_detect_enable) &
({ext_t_rise_edge_hold, rise_edge_m} | ~rise_edge_enable) &
({ext_t_fall_edge_hold, fall_edge_m} | ~fall_edge_enable) &
({ext_t_low_level_hold, low_level_m} | ~low_level_enable) &
({ext_t_high_level_hold , high_level_m} | ~high_level_enable));
default: trigger_active = 1'b1;
endcase
end
end
always @(*) begin
case (trigger_logic[6:4])
3'd0: trigger_active_mux = trigger_active;
3'd1: trigger_active_mux = trigger_in;
3'd2: trigger_active_mux = trigger_active & trigger_in;
3'd3: trigger_active_mux = trigger_active | trigger_in;
3'd4: trigger_active_mux = trigger_active ^ trigger_in;
3'd7: trigger_active_mux = 1'b0; // trigger disable
default: trigger_active_mux = 1'b0;
endcase
end
always @(posedge clk) begin
if (reset == 1'b1) begin
data_m1 <= 'd0;
edge_detect <= 'd0;
rise_edge <= 'd0;
fall_edge <= 'd0;
low_level <= 'd0;
high_level <= 'd0;
end else begin
if (data_valid == 1'b1) begin
data_m1 <= data;
edge_detect <= data_m1 ^ data;
rise_edge <= (data_m1 ^ data) & data;
fall_edge <= (data_m1 ^ data) & ~data;
low_level <= ~data;
high_level <= data;
edge_detect_m <= edge_detect;
rise_edge_m <= rise_edge;
fall_edge_m <= fall_edge;
low_level_m <= low_level;
high_level_m <= high_level;
end
end
end
// external trigger detect
always @(posedge clk) begin
if (reset == 1'b1) begin
ext_t_m <= 'd0;
ext_t_edge_detect_hold <= 'd0;
ext_t_rise_edge_hold <= 'd0;
ext_t_fall_edge_hold <= 'd0;
ext_t_low_level_hold <= 'd0;
ext_t_high_level_hold <= 'd0;
end else begin
ext_t_m <= trigger_i;
ext_t_edge_detect_hold <= ext_t_edge_detect_ack ? 2'b0 :
(ext_t_m ^ trigger_i) | ext_t_edge_detect_hold;
ext_t_rise_edge_hold <= ext_t_rise_edge_ack ? 2'b0 :
((ext_t_m ^ trigger_i) & trigger_i) | ext_t_rise_edge_hold;
ext_t_fall_edge_hold <= ext_t_fall_edge_ack ? 2'b0 :
((ext_t_m ^ trigger_i) & ~trigger_i) | ext_t_fall_edge_hold;
ext_t_low_level_hold <= ext_t_low_level_ack ? 2'b0 :
(~trigger_i) | ext_t_low_level_hold;
ext_t_high_level_hold <= ext_t_high_level_ack ? 2'b0 :
(trigger_i) | ext_t_high_level_hold;
ext_t_edge_detect_ack <= data_valid & ( |ext_t_edge_detect_hold);
ext_t_rise_edge_ack <= data_valid & ( |ext_t_rise_edge_hold);
ext_t_fall_edge_ack <= data_valid & ( |ext_t_fall_edge_hold);
ext_t_low_level_ack <= data_valid & ( |ext_t_low_level_hold);
ext_t_high_level_ack <= data_valid & ( |ext_t_high_level_hold);
end
end
endmodule
adi_library/axi_logic_analyzer/component.xml
+1079
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adi_library/axi_logic_analyzer/xgui/axi_logic_analyzer_v1_0.tcl
+10
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}