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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
commit 315a673005
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adi_library/axi_ltc2387/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_ltc2387
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ltc2387.v
GENERIC_DEPS += axi_ltc2387_channel.v
GENERIC_DEPS += axi_ltc2387_if.v
XILINX_DEPS += ../xilinx/common/ad_data_clk.v
XILINX_DEPS += ../xilinx/common/ad_data_in.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ltc2387_ip.tcl
include ../scripts/library.mk
adi_library/axi_ltc2387/axi_ltc2387.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ltc2387 #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 1,
parameter FPGA_FAMILY = 1,
parameter SPEED_GRADE = 1,
parameter DEV_PACKAGE = 1,
parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter IODELAY_CTRL = 1,
parameter DELAY_REFCLK_FREQUENCY = 200,
parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0,
parameter ADC_INIT_DELAY = 22,
parameter ADC_RES = 16,
parameter OUT_RES = 16,
parameter TWOLANES = 1
) (
input delay_clk,
// adc interface
input ref_clk,
input clk_gate,
input dco_p,
input dco_n,
input da_p,
input da_n,
input db_p,
input db_n,
// dma interface
output adc_valid,
output [OUT_RES-1:0] adc_data,
input adc_dovf,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot
);
// internal signals
wire [15:0] adc_data_s;
wire adc_or_s;
wire [ 1:0] up_dld_s;
wire [ 9:0] up_dwdata_s;
wire [ 9:0] up_drdata_s;
wire delay_locked_s;
wire up_status_pn_err_s;
wire up_status_pn_oos_s;
wire up_status_or_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
// internal signals
wire adc_rst;
wire adc_clk;
wire adc_enable;
wire up_clk;
wire up_rstn;
wire delay_rst;
wire adc_valid_ch_s;
wire [ADC_RES-1:0] adc_data_ch_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk = ref_clk;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 32'd0;
up_rack <= 1'd0;
up_wack <= 1'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
// main (device interface)
axi_ltc2387_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
.RESOLUTION (ADC_RES),
.IODELAY_CTRL (IODELAY_CTRL),
.TWOLANES (TWOLANES)
) i_if (
.clk (ref_clk),
.clk_gate (clk_gate),
.da_p (da_p),
.da_n (da_n),
.db_p (db_p),
.db_n (db_n),
.dco_p (dco_p),
.dco_n (dco_n),
.adc_valid (adc_valid_ch_s),
.adc_data (adc_data_ch_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// channel
axi_ltc2387_channel #(
.ADC_RES (ADC_RES),
.OUT_RES (OUT_RES),
.TWOLANES (TWOLANES),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE)
) i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data_in (adc_data_ch_s),
.adc_valid_in (adc_valid_ch_s),
.adc_enable (adc_enable),
.adc_valid (adc_valid),
.adc_data (adc_data),
.up_adc_pn_err (up_status_pn_err_s),
.up_adc_pn_oos (up_status_pn_oos_s),
.up_adc_or (up_status_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// adc delay control
up_delay_cntrl #(
.INIT_DELAY (ADC_INIT_DELAY),
.DATA_WIDTH (2),
.BASE_ADDRESS (6'h02)
) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// common processor control
up_adc_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (0),
.COMMON_ID (6'h00),
.DRP_DISABLE (6'h00),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.GPIO_DISABLE (0),
.START_CODE_DISABLE (0)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (delay_locked_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (32'b1),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (),
.adc_ext_sync_arm(),
.adc_ext_sync_disarm(),
.adc_ext_sync_manual_req(),
.adc_num_lanes (),
.adc_custom_control(),
.adc_crc_enable (),
.adc_sdr_ddr_n (),
.adc_symb_op (),
.adc_symb_8_16b (),
.up_pps_rcounter (32'd0),
.up_pps_status (1'd0),
.up_pps_irq_mask (),
.up_adc_r1_mode (),
.up_adc_ce (),
.up_status_pn_err (up_status_pn_err_s),
.up_status_pn_oos (up_status_pn_oos_s),
.up_status_or (up_status_or_s),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'b0),
.up_drp_ready (1'b0),
.up_drp_locked (1'b1),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
adi_library/axi_ltc2387/axi_ltc2387.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ltc2387/axi_ltc2387.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="e25bfd3e41704cb68e3f927df2ba1fe6"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
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<Filter Type="Srcs"/>
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</FileInfo>
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<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_ltc2387"/>
</Config>
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<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
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</Project>
adi_library/axi_ltc2387/axi_ltc2387_channel.v
+210
View File
@@ -0,0 +1,210 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ltc2387_channel #(
parameter ADC_RES = 16,
parameter OUT_RES = 16,
parameter TWOLANES = 1,
parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0
) (
// adc interface
input adc_clk,
input adc_rst,
input adc_valid_in,
input [ADC_RES-1:0] adc_data_in,
// dma interface
output adc_enable,
output adc_valid,
output [OUT_RES-1:0] adc_data,
// error monitoring
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack
);
// internal signals
wire adc_dfmt_valid_s;
wire [15:0] adc_dfmt_data_s;
wire adc_dcfilter_valid_s;
wire adc_iqcor_enb_s;
wire adc_dcfilt_enb_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
wire [15:0] adc_iqcor_coeff_1_s;
wire [15:0] adc_iqcor_coeff_2_s;
wire [ 3:0] adc_pnseq_sel_s;
wire [ 3:0] adc_data_sel_s;
reg adc_pn_err;
wire adc_pn_err_s;
wire [ADC_RES-1:0] test_pattern;
wire [15:0] expected_pattern;
assign adc_pn_err_s = adc_pn_err;
// expected pattern
generate
if (TWOLANES == 1) begin
assign expected_pattern = 16'b1100110000111111;
end else begin
assign expected_pattern = 16'b1010000001111111;
end
if (ADC_RES == 16) begin
assign test_pattern = expected_pattern;
end else if (ADC_RES == 18) begin
assign test_pattern = expected_pattern << 2;
end
endgenerate
always @(posedge adc_clk) begin
if (test_pattern == adc_data) begin
adc_pn_err <= 1'b0;
end else begin
adc_pn_err <= 1'b1;
end
end
// min DMA bus width according to ADC_RES
generate
if (ADC_RES == 18) begin
ad_datafmt #(
.DATA_WIDTH (18),
.BITS_PER_SAMPLE (32),
.DISABLE (DATAFORMAT_DISABLE)
) i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid_in),
.data (adc_data_in),
.valid_out (adc_valid),
.data_out (adc_data),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end else if (ADC_RES == 16) begin
assign adc_data = adc_data_in;
assign adc_valid = adc_valid_in;
end else begin
assign adc_data = 'd0;
assign adc_valid = 1'd0;
end
endgenerate
// adc channel regmap
up_adc_channel #(
.CHANNEL_ID (0),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (1'b1),
.IQCORRECTION_DISABLE (1'b1)
) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (adc_iqcor_enb_s),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (1'b0),
.adc_or (1'b0),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
adi_library/axi_ltc2387/axi_ltc2387_if.v
+236
View File
@@ -0,0 +1,236 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
`timescale 1ns/100ps
module axi_ltc2387_if #(
parameter FPGA_TECHNOLOGY = 1,
parameter IO_DELAY_GROUP = "adc_if_delay_group",
parameter IODELAY_CTRL = 1,
parameter DELAY_REFCLK_FREQUENCY = 200,
parameter [0:0] TWOLANES = 1, // 0 for Single Lane, 1 for Two Lanes
parameter RESOLUTION = 16 // 16 or 18 bits
) (
// delay interface
input up_clk,
input [ 1:0] up_dld,
input [ 9:0] up_dwdata,
output [ 9:0] up_drdata,
input delay_clk,
input delay_rst,
output delay_locked,
// adc interface
input clk,
input clk_gate,
input dco_p,
input dco_n,
input da_p,
input da_n,
input db_p,
input db_n,
output adc_valid,
output reg [RESOLUTION-1:0] adc_data
);
localparam ONE_L_WIDTH = (RESOLUTION == 18) ? 9 : 8;
localparam TWO_L_WIDTH = (RESOLUTION == 18) ? 5 : 4;
localparam WIDTH = (TWOLANES == 0) ? ONE_L_WIDTH : TWO_L_WIDTH;
// internal wires
wire da_p_int_s;
wire da_n_int_s;
wire db_p_int_s;
wire db_n_int_s;
wire dco;
wire dco_s;
wire [17:0] adc_data_int;
// internal registers
reg [WIDTH:0] adc_data_da_p = 'b0;
reg [WIDTH:0] adc_data_da_n = 'b0;
reg [WIDTH:0] adc_data_db_p = 'b0;
reg [WIDTH:0] adc_data_db_n = 'b0;
reg [2:0] clk_gate_d = 'b0;
// assignments
// adc_valid is 1 for the current sample that is sent
assign adc_valid = clk_gate_d[1] & ~clk_gate_d[0];
always @(posedge clk) begin
clk_gate_d <= {clk_gate_d[1:0], clk_gate};
if (clk_gate_d[1] == 1'b1 && clk_gate_d[0] == 1'b0) begin
if (RESOLUTION == 18) begin
adc_data <= adc_data_int;
end else begin
adc_data <= adc_data_int[15:0];
end
end
end
always @(posedge dco) begin
adc_data_da_p <= {adc_data_da_p[WIDTH-1:0], da_p_int_s};
adc_data_da_n <= {adc_data_da_n[WIDTH-1:0], da_n_int_s};
adc_data_db_p <= {adc_data_db_p[WIDTH-1:0], db_p_int_s};
adc_data_db_n <= {adc_data_db_n[WIDTH-1:0], db_n_int_s};
end
// bits rearrangement
if (!TWOLANES) begin
assign adc_data_int[17] = adc_data_da_p[7];
assign adc_data_int[16] = adc_data_da_n[7];
assign adc_data_int[15] = adc_data_da_p[6];
assign adc_data_int[14] = adc_data_da_n[6];
assign adc_data_int[13] = adc_data_da_p[5];
assign adc_data_int[12] = adc_data_da_n[5];
assign adc_data_int[11] = adc_data_da_p[4];
assign adc_data_int[10] = adc_data_da_n[4];
assign adc_data_int[9] = adc_data_da_p[3];
assign adc_data_int[8] = adc_data_da_n[3];
assign adc_data_int[7] = adc_data_da_p[2];
assign adc_data_int[6] = adc_data_da_n[2];
assign adc_data_int[5] = adc_data_da_p[1];
assign adc_data_int[4] = adc_data_da_n[1];
assign adc_data_int[3] = adc_data_da_p[0];
assign adc_data_int[2] = adc_data_da_n[0];
assign adc_data_int[1] = da_p_int_s;
assign adc_data_int[0] = da_n_int_s;
end else begin
if (RESOLUTION == 18) begin
assign adc_data_int[17] = adc_data_da_p[3];
assign adc_data_int[16] = adc_data_db_p[3];
assign adc_data_int[15] = adc_data_da_n[3];
assign adc_data_int[14] = adc_data_db_n[3];
assign adc_data_int[13] = adc_data_da_p[2];
assign adc_data_int[12] = adc_data_db_p[2];
assign adc_data_int[11] = adc_data_da_n[2];
assign adc_data_int[10] = adc_data_db_n[2];
assign adc_data_int[9] = adc_data_da_p[1];
assign adc_data_int[8] = adc_data_db_p[1];
assign adc_data_int[7] = adc_data_da_n[1];
assign adc_data_int[6] = adc_data_db_n[1];
assign adc_data_int[5] = adc_data_da_p[0];
assign adc_data_int[4] = adc_data_db_p[0];
assign adc_data_int[3] = adc_data_da_n[0];
assign adc_data_int[2] = adc_data_db_n[0];
assign adc_data_int[1] = da_p_int_s;
assign adc_data_int[0] = db_p_int_s;
end else begin
assign adc_data_int[15] = adc_data_da_p[2];
assign adc_data_int[14] = adc_data_db_p[2];
assign adc_data_int[13] = adc_data_da_n[2];
assign adc_data_int[12] = adc_data_db_n[2];
assign adc_data_int[11] = adc_data_da_p[1];
assign adc_data_int[10] = adc_data_db_p[1];
assign adc_data_int[9] = adc_data_da_n[1];
assign adc_data_int[8] = adc_data_db_n[1];
assign adc_data_int[7] = adc_data_da_p[0];
assign adc_data_int[6] = adc_data_db_p[0];
assign adc_data_int[5] = adc_data_da_n[0];
assign adc_data_int[4] = adc_data_db_n[0];
assign adc_data_int[3] = da_p_int_s;
assign adc_data_int[2] = db_p_int_s;
assign adc_data_int[1] = da_n_int_s;
assign adc_data_int[0] = db_n_int_s;
end
end
// data interface - differential to single ended
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IDDR_CLK_EDGE ("OPPOSITE_EDGE"),
.IODELAY_CTRL (IODELAY_CTRL),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_rx_da (
.rx_clk (dco),
.rx_data_in_p (da_p),
.rx_data_in_n (da_n),
.rx_data_p (da_p_int_s),
.rx_data_n (da_n_int_s),
.up_clk (up_clk),
.up_dld (up_dld[0]),
.up_dwdata (up_dwdata[4:0]),
.up_drdata (up_drdata[4:0]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
ad_data_in #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.IDDR_CLK_EDGE ("OPPOSITE_EDGE"),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP),
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
) i_rx_db (
.rx_clk (dco),
.rx_data_in_p (db_p),
.rx_data_in_n (db_n),
.rx_data_p (db_p_int_s),
.rx_data_n (db_n_int_s),
.up_clk (up_clk),
.up_dld (up_dld[1]),
.up_dwdata (up_dwdata[9:5]),
.up_drdata (up_drdata[9:5]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// clock
IBUFGDS i_rx_clk_ibuf (
.I (dco_p),
.IB (dco_n),
.O (dco_s));
BUFR i_clk_gbuf (
.CLR (1'b0),
.CE (1'b1),
.I (dco_s),
.O (dco));
endmodule
adi_library/axi_ltc2387/axi_ltc2387_ip.tcl
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###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_ltc2387
adi_ip_files axi_ltc2387 [list \
"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"axi_ltc2387_if.v" \
"axi_ltc2387_channel.v" \
"axi_ltc2387.v" ]
adi_ip_properties axi_ltc2387
ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dco_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dco_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
set cc [ipx::current_core]
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
ipgui::add_param -name "ADC_RES" -component $cc -parent $page0
set_property -dict [list \
"display_name" "ADC resolution" \
"tooltip" "ADC resolution" \
] [ipgui::get_guiparamspec -name "ADC_RES" -component $cc]
set_property -dict [list \
"value_validation_type" "list" \
"value_validation_list" "16 18" \
] \
[ipx::get_user_parameters ADC_RES -of_objects $cc]
ipgui::add_param -name "OUT_RES" -component $cc -parent $page0
set_property -dict [list \
"display_name" "Output data width" \
"tooltip" "Memory interface" \
] [ipgui::get_guiparamspec -name "OUT_RES" -component $cc]
set_property -dict [list \
"value_validation_type" "list" \
"value_validation_list" "16 32" \
] \
[ipx::get_user_parameters OUT_RES -of_objects $cc]
ipx::save_core [ipx::current_core]
adi_library/axi_ltc2387/component.xml
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adi_library/axi_ltc2387/xgui/axi_ltc2387_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "ADC_INIT_DELAY" -parent ${Page_0}
ipgui::add_param $IPINST -name "ADC_RES" -parent ${Page_0}
ipgui::add_param $IPINST -name "DATAFORMAT_DISABLE" -parent ${Page_0}
ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0}
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${Page_0}
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${Page_0}
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${Page_0}
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
ipgui::add_param $IPINST -name "IODELAY_CTRL" -parent ${Page_0}
ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0}
ipgui::add_param $IPINST -name "OUT_RES" -parent ${Page_0}
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${Page_0}
ipgui::add_param $IPINST -name "TWOLANES" -parent ${Page_0}
ipgui::add_param $IPINST -name "USERPORTS_DISABLE" -parent ${Page_0}
}
proc update_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } {
# Procedure called to update ADC_INIT_DELAY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } {
# Procedure called to validate ADC_INIT_DELAY
return true
}
proc update_PARAM_VALUE.ADC_RES { PARAM_VALUE.ADC_RES } {
# Procedure called to update ADC_RES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ADC_RES { PARAM_VALUE.ADC_RES } {
# Procedure called to validate ADC_RES
return true
}
proc update_PARAM_VALUE.DATAFORMAT_DISABLE { PARAM_VALUE.DATAFORMAT_DISABLE } {
# Procedure called to update DATAFORMAT_DISABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DATAFORMAT_DISABLE { PARAM_VALUE.DATAFORMAT_DISABLE } {
# Procedure called to validate DATAFORMAT_DISABLE
return true
}
proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
# Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
# Procedure called to validate DELAY_REFCLK_FREQUENCY
return true
}
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to validate DEV_PACKAGE
return true
}
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to validate FPGA_FAMILY
return true
}
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to validate FPGA_TECHNOLOGY
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } {
# Procedure called to update IODELAY_CTRL when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } {
# Procedure called to validate IODELAY_CTRL
return true
}
proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
# Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
# Procedure called to validate IO_DELAY_GROUP
return true
}
proc update_PARAM_VALUE.OUT_RES { PARAM_VALUE.OUT_RES } {
# Procedure called to update OUT_RES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.OUT_RES { PARAM_VALUE.OUT_RES } {
# Procedure called to validate OUT_RES
return true
}
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to validate SPEED_GRADE
return true
}
proc update_PARAM_VALUE.TWOLANES { PARAM_VALUE.TWOLANES } {
# Procedure called to update TWOLANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TWOLANES { PARAM_VALUE.TWOLANES } {
# Procedure called to validate TWOLANES
return true
}
proc update_PARAM_VALUE.USERPORTS_DISABLE { PARAM_VALUE.USERPORTS_DISABLE } {
# Procedure called to update USERPORTS_DISABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.USERPORTS_DISABLE { PARAM_VALUE.USERPORTS_DISABLE } {
# Procedure called to validate USERPORTS_DISABLE
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
}
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
}
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
}
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
}
proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP}
}
proc update_MODELPARAM_VALUE.IODELAY_CTRL { MODELPARAM_VALUE.IODELAY_CTRL PARAM_VALUE.IODELAY_CTRL } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IODELAY_CTRL}] ${MODELPARAM_VALUE.IODELAY_CTRL}
}
proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY}
}
proc update_MODELPARAM_VALUE.USERPORTS_DISABLE { MODELPARAM_VALUE.USERPORTS_DISABLE PARAM_VALUE.USERPORTS_DISABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.USERPORTS_DISABLE}] ${MODELPARAM_VALUE.USERPORTS_DISABLE}
}
proc update_MODELPARAM_VALUE.DATAFORMAT_DISABLE { MODELPARAM_VALUE.DATAFORMAT_DISABLE PARAM_VALUE.DATAFORMAT_DISABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DATAFORMAT_DISABLE}] ${MODELPARAM_VALUE.DATAFORMAT_DISABLE}
}
proc update_MODELPARAM_VALUE.ADC_INIT_DELAY { MODELPARAM_VALUE.ADC_INIT_DELAY PARAM_VALUE.ADC_INIT_DELAY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ADC_INIT_DELAY}] ${MODELPARAM_VALUE.ADC_INIT_DELAY}
}
proc update_MODELPARAM_VALUE.ADC_RES { MODELPARAM_VALUE.ADC_RES PARAM_VALUE.ADC_RES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ADC_RES}] ${MODELPARAM_VALUE.ADC_RES}
}
proc update_MODELPARAM_VALUE.OUT_RES { MODELPARAM_VALUE.OUT_RES PARAM_VALUE.OUT_RES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.OUT_RES}] ${MODELPARAM_VALUE.OUT_RES}
}
proc update_MODELPARAM_VALUE.TWOLANES { MODELPARAM_VALUE.TWOLANES PARAM_VALUE.TWOLANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TWOLANES}] ${MODELPARAM_VALUE.TWOLANES}
}