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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/axi_pwm_gen/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_pwm_gen
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_pwm_gen.sv
GENERIC_DEPS += axi_pwm_gen_1.v
GENERIC_DEPS += axi_pwm_gen_regmap.sv
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += axi_pwm_gen_constr.ttcl
XILINX_DEPS += axi_pwm_gen_ip.tcl
XILINX_LIB_DEPS += util_cdc
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../util_cdc/sync_bits.v
INTEL_DEPS += ../util_cdc/sync_data.v
INTEL_DEPS += axi_pwm_gen_constr.sdc
INTEL_DEPS += axi_pwm_gen_hw.tcl
include ../scripts/library.mk
adi_library/axi_pwm_gen/axi_pwm_gen.sv
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_pwm_gen #(
parameter ID = 0,
parameter ASYNC_CLK_EN = 1,
parameter N_PWMS = 1,
parameter PWM_EXT_SYNC = 0,
parameter EXT_ASYNC_SYNC = 0,
parameter PULSE_0_WIDTH = 7,
parameter PULSE_1_WIDTH = 7,
parameter PULSE_2_WIDTH = 7,
parameter PULSE_3_WIDTH = 7,
parameter PULSE_4_WIDTH = 7,
parameter PULSE_5_WIDTH = 7,
parameter PULSE_6_WIDTH = 7,
parameter PULSE_7_WIDTH = 7,
parameter PULSE_8_WIDTH = 7,
parameter PULSE_9_WIDTH = 7,
parameter PULSE_10_WIDTH = 7,
parameter PULSE_11_WIDTH = 7,
parameter PULSE_12_WIDTH = 7,
parameter PULSE_13_WIDTH = 7,
parameter PULSE_14_WIDTH = 7,
parameter PULSE_15_WIDTH = 7,
parameter PULSE_0_PERIOD = 10,
parameter PULSE_1_PERIOD = 10,
parameter PULSE_2_PERIOD = 10,
parameter PULSE_3_PERIOD = 10,
parameter PULSE_4_PERIOD = 10,
parameter PULSE_5_PERIOD = 10,
parameter PULSE_6_PERIOD = 10,
parameter PULSE_7_PERIOD = 10,
parameter PULSE_8_PERIOD = 10,
parameter PULSE_9_PERIOD = 10,
parameter PULSE_10_PERIOD = 10,
parameter PULSE_11_PERIOD = 10,
parameter PULSE_12_PERIOD = 10,
parameter PULSE_13_PERIOD = 10,
parameter PULSE_14_PERIOD = 10,
parameter PULSE_15_PERIOD = 10,
parameter PULSE_0_OFFSET = 0,
parameter PULSE_1_OFFSET = 0,
parameter PULSE_2_OFFSET = 0,
parameter PULSE_3_OFFSET = 0,
parameter PULSE_4_OFFSET = 0,
parameter PULSE_5_OFFSET = 0,
parameter PULSE_6_OFFSET = 0,
parameter PULSE_7_OFFSET = 0,
parameter PULSE_8_OFFSET = 0,
parameter PULSE_9_OFFSET = 0,
parameter PULSE_10_OFFSET = 0,
parameter PULSE_11_OFFSET = 0,
parameter PULSE_12_OFFSET = 0,
parameter PULSE_13_OFFSET = 0,
parameter PULSE_14_OFFSET = 0,
parameter PULSE_15_OFFSET = 0
) (
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input ext_clk,
input ext_sync,
output pwm_0,
output pwm_1,
output pwm_2,
output pwm_3,
output pwm_4,
output pwm_5,
output pwm_6,
output pwm_7,
output pwm_8,
output pwm_9,
output pwm_10,
output pwm_11,
output pwm_12,
output pwm_13,
output pwm_14,
output pwm_15
);
// local parameters
localparam PWMS = N_PWMS-1;
localparam [31:0] CORE_VERSION = {16'h0002, /* MAJOR */
8'h00, /* MINOR */
8'h00}; /* PATCH */
localparam [31:0] CORE_MAGIC = 32'h601a3471; // PLSG
localparam reg [31:0] PULSE_WIDTH_G[15:0] = '{PULSE_0_WIDTH,
PULSE_1_WIDTH,
PULSE_2_WIDTH,
PULSE_3_WIDTH,
PULSE_4_WIDTH,
PULSE_5_WIDTH,
PULSE_6_WIDTH,
PULSE_7_WIDTH,
PULSE_8_WIDTH,
PULSE_9_WIDTH,
PULSE_10_WIDTH,
PULSE_11_WIDTH,
PULSE_12_WIDTH,
PULSE_13_WIDTH,
PULSE_14_WIDTH,
PULSE_15_WIDTH};
localparam reg [31:0] PULSE_PERIOD_G[0:15] = '{PULSE_0_PERIOD,
PULSE_1_PERIOD,
PULSE_2_PERIOD,
PULSE_3_PERIOD,
PULSE_4_PERIOD,
PULSE_5_PERIOD,
PULSE_6_PERIOD,
PULSE_7_PERIOD,
PULSE_8_PERIOD,
PULSE_9_PERIOD,
PULSE_10_PERIOD,
PULSE_11_PERIOD,
PULSE_12_PERIOD,
PULSE_13_PERIOD,
PULSE_14_PERIOD,
PULSE_15_PERIOD};
localparam reg [31:0] PULSE_OFFSET_G[0:15] = '{PULSE_0_OFFSET,
PULSE_1_OFFSET,
PULSE_2_OFFSET,
PULSE_3_OFFSET,
PULSE_4_OFFSET,
PULSE_5_OFFSET,
PULSE_6_OFFSET,
PULSE_7_OFFSET,
PULSE_8_OFFSET,
PULSE_9_OFFSET,
PULSE_10_OFFSET,
PULSE_11_OFFSET,
PULSE_12_OFFSET,
PULSE_13_OFFSET,
PULSE_14_OFFSET,
PULSE_15_OFFSET};
// internal registers
reg [PWMS:0] sync;
reg [31:0] offset_cnt = 32'd0;
reg offset_alignment = 1'b0;
reg pause_cnt_d = 1'b0;
// internal signals
wire clk;
wire up_clk;
wire up_rstn;
wire up_rreq_s;
wire up_wack_s;
wire up_rack_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire [ 15:0] pwm;
wire [ 31:0] pwm_width_s[0:PWMS];
wire [ 31:0] pwm_period_s[0:PWMS];
wire [ 31:0] pwm_offset_s[0:PWMS];
wire [ 15:0] pwm_armed;
wire load_config_s;
wire pwm_gen_resetn;
wire ext_sync_s;
wire pause_cnt;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
axi_pwm_gen_regmap #(
.ID (ID),
.ASYNC_CLK_EN (ASYNC_CLK_EN),
.CORE_MAGIC (CORE_MAGIC),
.CORE_VERSION (CORE_VERSION),
.N_PWMS (PWMS),
.PULSE_WIDTH_G (PULSE_WIDTH_G),
.PULSE_PERIOD_G (PULSE_PERIOD_G),
.PULSE_OFFSET_G (PULSE_OFFSET_G)
) i_regmap (
.ext_clk (ext_clk),
.clk_out (clk),
.pwm_gen_resetn (pwm_gen_resetn),
.pwm_width (pwm_width_s),
.pwm_period (pwm_period_s),
.pwm_offset (pwm_offset_s),
.load_config (load_config_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// external sync
generate
reg ext_sync_m0 = 1'b1;
reg ext_sync_m1 = 1'b1;
if (EXT_ASYNC_SYNC) begin
always @(posedge clk) begin
if (pwm_gen_resetn == 1'b0) begin
ext_sync_m0 <= 1'b1;
ext_sync_m1 <= 1'b1;
end else begin
ext_sync_m0 <= (PWM_EXT_SYNC == 1) ? ext_sync : 0;
ext_sync_m1 <= ext_sync_m0;
end
end
assign ext_sync_s = ext_sync_m1;
end else begin
assign ext_sync_s = (PWM_EXT_SYNC == 1) ? ext_sync : 0;
end
endgenerate
// offset counter
always @(posedge clk) begin
if (offset_alignment == 1'b1 || pwm_gen_resetn == 1'b0) begin
offset_cnt <= 32'd0;
end else begin
offset_cnt <= offset_cnt + 1'b1;
end
if (pwm_gen_resetn == 1'b0) begin
offset_alignment <= 1'b0;
end else begin
// when using external sync an offset alignment can be done only
// after all pwm counters are paused(load_config)/reseated
offset_alignment <= (load_config_s == 1'b1) ? 1'b1 :
offset_alignment &
(ext_sync_s ? 1'b1 : !pause_cnt);
end
end
assign pause_cnt = ((pwm_armed[1] |
pwm_armed[2] |
pwm_armed[3] |
pwm_armed[4] |
pwm_armed[5] |
pwm_armed[6] |
pwm_armed[7] |
pwm_armed[8] |
pwm_armed[9] |
pwm_armed[10] |
pwm_armed[11] |
pwm_armed[12] |
pwm_armed[13] |
pwm_armed[14] |
pwm_armed[15] ) ? 1'b1 : 1'b0);
genvar i;
generate
for (i = 0; i <= 15; i = i + 1) begin: pwm_cnt
if (i <= PWMS) begin
axi_pwm_gen_1 #(
.PULSE_WIDTH (PULSE_WIDTH_G[i]),
.PULSE_PERIOD (PULSE_PERIOD_G[i])
) i_axi_pwm_gen_1 (
.clk (clk),
.rstn (pwm_gen_resetn),
.pulse_width (pwm_width_s[i]),
.pulse_period (pwm_period_s[i]),
.load_config (load_config_s),
.sync (sync[i]),
.pulse (pwm[i]),
.pulse_armed (pwm_armed[i]));
always @(posedge clk) begin
if (pwm_gen_resetn == 1'b0) begin
sync[i] <= 1'b1;
end else begin
sync[i] <= (offset_cnt == pwm_offset_s[i]) ? offset_alignment : 1'b1;
end
end
end else begin
assign pwm[i] = 1'b0;
assign pwm_armed[i] = 1'b0;
end
end
endgenerate
assign pwm_0 = pwm[0];
assign pwm_1 = pwm[1];
assign pwm_2 = pwm[2];
assign pwm_3 = pwm[3];
assign pwm_4 = pwm[4];
assign pwm_5 = pwm[5];
assign pwm_6 = pwm[6];
assign pwm_7 = pwm[7];
assign pwm_8 = pwm[8];
assign pwm_9 = pwm[9];
assign pwm_10 = pwm[10];
assign pwm_11 = pwm[11];
assign pwm_12 = pwm[12];
assign pwm_13 = pwm[13];
assign pwm_14 = pwm[14];
assign pwm_15 = pwm[15];
up_axi #(
.AXI_ADDRESS_WIDTH(16)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
adi_library/axi_pwm_gen/axi_pwm_gen.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_pwm_gen/axi_pwm_gen.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="c1f58724adcf46cba87c475145902d53"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../common/ad_rst.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_pwm_gen_1.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../common/up_axi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_pwm_gen_regmap.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_pwm_gen.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_pwm_gen_constr.ttcl"/>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_pwm_gen"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/axi_pwm_gen/axi_pwm_gen_1.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_pwm_gen_1 #(
// the width and period are defined in number of clock cycles
parameter PULSE_WIDTH = 7,
parameter PULSE_PERIOD = 100000000
) (
input clk,
input rstn,
input [31:0] pulse_width,
input [31:0] pulse_period,
input load_config,
input sync,
output pulse,
output pulse_armed
);
// internal registers
reg [31:0] pulse_period_cnt = 32'h0;
reg [31:0] pulse_period_read = PULSE_PERIOD;
reg [31:0] pulse_width_read = PULSE_WIDTH;
reg [31:0] pulse_period_d = PULSE_PERIOD;
reg [31:0] pulse_width_d = PULSE_WIDTH;
reg phase_align_armed = 1'b1;
reg pulse_i = 1'b0;
reg busy = 1'b0;
// internal wires
wire phase_align;
wire end_of_period;
wire end_of_pulse;
wire pulse_enable;
// enable pwm
assign pulse_enable = (pulse_period_d != 32'd0) ? 1'b1 : 1'b0;
// flop the desired period
always @(posedge clk) begin
if (rstn == 1'b0) begin
pulse_period_d <= pulse_period;
pulse_width_d <= pulse_width;
pulse_period_read <= pulse_period;
pulse_width_read <= pulse_width;
end else begin
// load the input period/width values
if (load_config) begin
pulse_period_read <= pulse_period;
pulse_width_read <= pulse_width;
end
// update the current period/width at the end of the period
if (end_of_period | ~pulse_enable) begin
pulse_period_d <= pulse_period_read;
pulse_width_d <= pulse_width_read;
end
end
end
// phase align to the first sync pulse until another load_config
always @(posedge clk) begin
if (rstn == 1'b0) begin
phase_align_armed <= 1'b1;
end else begin
if (load_config == 1'b1) begin
phase_align_armed <= sync;
end else begin
phase_align_armed <= phase_align_armed & sync;
end
end
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
busy <= 1'b0;
end else begin
if (end_of_period) begin
busy <= 1'b0;
end else if ( ~(phase_align_armed & sync)) begin
busy <= 1'b1;
end
end
end
assign phase_align = phase_align_armed & sync & busy;
// a free running counter
always @(posedge clk) begin
if (rstn == 1'b0 || phase_align == 1'b1 || end_of_period == 1'b1) begin
pulse_period_cnt <= 32'd1;
end else begin
if (pulse_enable == 1'b1) begin
pulse_period_cnt <= pulse_period_cnt + 1'b1;
end
end
end
assign end_of_period = (pulse_period_cnt == pulse_period_d) ? 1'b1 : 1'b0;
assign end_of_pulse = (pulse_period_cnt == pulse_width_d) ? 1'b1 : 1'b0;
// generate pulse with a specified width
always @ (posedge clk) begin
if ((rstn == 1'b0) || (end_of_pulse == 1'b1)) begin
pulse_i <= 1'b0;
end else if ((end_of_period == 1'b1 || phase_align == 1'b1) && pulse_enable == 1'b1) begin
pulse_i <= 1'b1;
end
end
assign pulse = pulse_i & !(phase_align_armed & sync);
assign pulse_armed = phase_align_armed;
endmodule
adi_library/axi_pwm_gen/axi_pwm_gen_constr.sdc
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###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
set script_dir [file dirname [info script]]
source "$script_dir/util_cdc_constr.tcl"
set_false_path -to [get_registers *axi_pwm_gen_regmap*cdc_sync_stage1*]
set_false_path -to [get_registers *axi_pwm_gen_regmap*sync_data*out_data*]
adi_library/axi_pwm_gen/axi_pwm_gen_constr.ttcl
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###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
# SPDX short identifier: ADIBSD
###############################################################################
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName [ttcl_add $ComponentName "_constr"] :>
<: setFileExtension ".xdc" :>
<: setFileProcessingOrder late :>
<: set async_clock [getBooleanValue "ASYNC_CLK_EN"] :>
## False path definitions for ASYNC mode
<: if { $async_clock } { :>
set_property ASYNC_REG TRUE \
[get_cells -hier {*cdc_sync_stage1_reg*}] \
[get_cells -hier {*cdc_sync_stage2_reg*}]
set_false_path -from [get_cells -hierarchical * -filter {NAME=~*i_pwm_props/cdc_hold_reg*}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_pwm_props/out_data_reg*}] \
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_pwm_props/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_pwm_props/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_pwm_props/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_pwm_props/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}]
<: } :>
adi_library/axi_pwm_gen/axi_pwm_gen_hw.tcl
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###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ip
package require qsys 14.0
package require quartus::device
source ../../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
ad_ip_create axi_pwm_gen {AXI PWM GEN}
ad_ip_files axi_pwm_gen [list \
$ad_hdl_dir/library/util_cdc/sync_data.v \
$ad_hdl_dir/library/util_cdc/sync_bits.v \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
axi_pwm_gen_constr.sdc \
axi_pwm_gen_regmap.sv \
axi_pwm_gen_1.v \
axi_pwm_gen.sv]
# parameters
ad_ip_parameter ID INTEGER 0
ad_ip_parameter ASYNC_CLK_EN INTEGER 1
ad_ip_parameter N_PWMS INTEGER 1
ad_ip_parameter PWM_EXT_SYNC INTEGER 0
ad_ip_parameter EXT_ASYNC_SYNC INTEGER 0
ad_ip_parameter PULSE_0_WIDTH INTEGER 7
ad_ip_parameter PULSE_1_WIDTH INTEGER 7
ad_ip_parameter PULSE_2_WIDTH INTEGER 7
ad_ip_parameter PULSE_3_WIDTH INTEGER 7
ad_ip_parameter PULSE_4_WIDTH INTEGER 7
ad_ip_parameter PULSE_5_WIDTH INTEGER 7
ad_ip_parameter PULSE_6_WIDTH INTEGER 7
ad_ip_parameter PULSE_7_WIDTH INTEGER 7
ad_ip_parameter PULSE_8_WIDTH INTEGER 7
ad_ip_parameter PULSE_9_WIDTH INTEGER 7
ad_ip_parameter PULSE_10_WIDTH INTEGER 7
ad_ip_parameter PULSE_11_WIDTH INTEGER 7
ad_ip_parameter PULSE_12_WIDTH INTEGER 7
ad_ip_parameter PULSE_13_WIDTH INTEGER 7
ad_ip_parameter PULSE_14_WIDTH INTEGER 7
ad_ip_parameter PULSE_15_WIDTH INTEGER 7
ad_ip_parameter PULSE_0_PERIOD INTEGER 10
ad_ip_parameter PULSE_1_PERIOD INTEGER 10
ad_ip_parameter PULSE_2_PERIOD INTEGER 10
ad_ip_parameter PULSE_3_PERIOD INTEGER 10
ad_ip_parameter PULSE_4_PERIOD INTEGER 10
ad_ip_parameter PULSE_5_PERIOD INTEGER 10
ad_ip_parameter PULSE_6_PERIOD INTEGER 10
ad_ip_parameter PULSE_7_PERIOD INTEGER 10
ad_ip_parameter PULSE_8_PERIOD INTEGER 10
ad_ip_parameter PULSE_9_PERIOD INTEGER 10
ad_ip_parameter PULSE_10_PERIOD INTEGER 10
ad_ip_parameter PULSE_11_PERIOD INTEGER 10
ad_ip_parameter PULSE_12_PERIOD INTEGER 10
ad_ip_parameter PULSE_13_PERIOD INTEGER 10
ad_ip_parameter PULSE_14_PERIOD INTEGER 10
ad_ip_parameter PULSE_15_PERIOD INTEGER 10
ad_ip_parameter PULSE_0_OFFSET INTEGER 0
ad_ip_parameter PULSE_1_OFFSET INTEGER 0
ad_ip_parameter PULSE_2_OFFSET INTEGER 0
ad_ip_parameter PULSE_3_OFFSET INTEGER 0
ad_ip_parameter PULSE_4_OFFSET INTEGER 0
ad_ip_parameter PULSE_5_OFFSET INTEGER 0
ad_ip_parameter PULSE_6_OFFSET INTEGER 0
ad_ip_parameter PULSE_7_OFFSET INTEGER 0
ad_ip_parameter PULSE_8_OFFSET INTEGER 0
ad_ip_parameter PULSE_9_OFFSET INTEGER 0
ad_ip_parameter PULSE_10_OFFSET INTEGER 0
ad_ip_parameter PULSE_11_OFFSET INTEGER 0
ad_ip_parameter PULSE_12_OFFSET INTEGER 0
ad_ip_parameter PULSE_13_OFFSET INTEGER 0
ad_ip_parameter PULSE_14_OFFSET INTEGER 0
ad_ip_parameter PULSE_15_OFFSET INTEGER 0
# interfaces
# axi
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16
# external clock and external sync
ad_interface clock ext_clk input 1
ad_interface signal ext_sync input 1
# output signals
for {set i 0} {$i < 16} {incr i} {
ad_interface signal pwm_$i output 1 if_pwm
}
adi_library/axi_pwm_gen/axi_pwm_gen_ip.tcl
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###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_pwm_gen
adi_ip_files axi_pwm_gen [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"axi_pwm_gen_constr.ttcl" \
"axi_pwm_gen_regmap.sv" \
"axi_pwm_gen_1.v" \
"axi_pwm_gen.sv"]
adi_ip_properties axi_pwm_gen
adi_ip_ttcl axi_pwm_gen "axi_pwm_gen_constr.ttcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen} [ipx::current_core]
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set cc [ipx::current_core]
set_property display_name "ADI AXI PWM Generator" $cc
set_property description "ADI AXI PWM Generator" $cc
## define ext_clk port as a clock interface
adi_add_bus ext_clk slave \
"xilinx.com:signal:clock_rtl:1.0" \
"xilinx.com:signal:clock:1.0" \
[list {"ext_clk" "CLK"} ]
adi_set_ports_dependency "ext_clk" \
"(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)" 0
## Parameter validation
set_property -dict [list \
"value_format" "bool" \
"value" "true" \
] \
[ipx::get_user_parameters ASYNC_CLK_EN -of_objects $cc]
set_property -dict [list \
"value_format" "bool" \
"value" "true" \
] \
[ipx::get_hdl_parameters ASYNC_CLK_EN -of_objects $cc]
## Customize XGUI layout
## Remove the automatically generated GUI page
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
ipx::save_core $cc
## Create a new GUI page
ipgui::add_page -name {AXI PWM Generator} -component $cc -display_name {AXI PWM Generator}
set page0 [ipgui::get_pagespec -name "AXI PWM Generator" -component $cc]
ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0
set_property -dict [list \
"display_name" "ASYNC_CLK_EN" \
"tooltip" "External clock for the counter" \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc]
ipgui::add_param -name "EXT_ASYNC_SYNC" -component $cc -parent $page0
set_property -dict [list \
"display_name" "External sync signal is asynchronous" \
"tooltip" "NOTE: If active the ext_sync will be delayed 2 clock cycles." \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc]
ipgui::add_param -name "N_PWMS" -component $cc -parent $page0
set_property -dict [list \
"display_name" "Number of pwms" \
] [ipgui::get_guiparamspec -name "N_PWMS" -component $cc]
ipgui::add_param -name "PWM_EXT_SYNC" -component $cc -parent $page0
set_property -dict [list \
"display_name" "External sync" \
"tooltip" "NOTE: If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before deaserting the ext_sync" \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "PWM_EXT_SYNC" -component $cc]
ipgui::add_param -name "EXT_ASYNC_SYNC" -component $cc -parent $page0
set_property -dict [list \
"display_name" "External sync signal is asynchronous" \
"tooltip" "NOTE: If active the ext_sync will be delayed 2 clock cycles." \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc]
# Maximum 16 pwms
for {set i 0} {$i < 16} {incr i} {
ipgui::add_param -name "PULSE_${i}_WIDTH" -component $cc -parent $page0
set_property -dict [list \
"display_name" "PULSE $i width" \
"tooltip" "PULSE width of the generated signal. The unit interval is the system or external clock period." \
] [ipgui::get_guiparamspec -name "PULSE_${i}_WIDTH" -component $cc]
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "0" \
"value_validation_range_maximum" "2147483647" \
] \
[ipx::get_user_parameters PULSE_${i}_WIDTH -of_objects $cc]
ipgui::add_param -name "PULSE_${i}_PERIOD" -component $cc -parent $page0
set_property -dict [list \
"display_name" "PULSE ${i} period" \
"tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \
] [ipgui::get_guiparamspec -name "PULSE_${i}_PERIOD" -component $cc]
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "0" \
"value_validation_range_maximum" "2147483647" \
] \
[ipx::get_user_parameters PULSE_${i}_PERIOD -of_objects $cc]
ipgui::add_param -name "PULSE_${i}_OFFSET" -component $cc -parent $page0
set_property -dict [list \
"display_name" "PULSE ${i} offset" \
"tooltip" "Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period." \
] [ipgui::get_guiparamspec -name "PULSE_${i}_OFFSET" -component $cc]
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "0" \
"value_validation_range_maximum" "2147483647" \
] \
[ipx::get_user_parameters PULSE_${i}_OFFSET -of_objects $cc]
}
for {set i 0} {$i < 16} {incr i} {
adi_set_ports_dependency "pwm_$i" \
"(spirit:decode(id('MODELPARAM_VALUE.N_PWMS')) > $i)"
}
adi_set_ports_dependency "ext_sync" \
"(spirit:decode(id('MODELPARAM_VALUE.PWM_EXT_SYNC')) == 1)"
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects $cc]
## Save the modifications
ipx::create_xgui_files $cc
ipx::save_core $cc
adi_library/axi_pwm_gen/axi_pwm_gen_regmap.sv
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_pwm_gen_regmap #(
parameter ID = 0,
parameter CORE_MAGIC = 0,
parameter CORE_VERSION = 0,
parameter ASYNC_CLK_EN = 1,
parameter N_PWMS = 0,
parameter reg [31:0] PULSE_WIDTH_G[0:15] = '{16{32'd0}},
parameter reg [31:0] PULSE_PERIOD_G[0:15] = '{16{32'd0}},
parameter reg [31:0] PULSE_OFFSET_G[0:15] = '{16{32'd0}}
) (
// external clock
input ext_clk,
// control and status signals
output clk_out,
output pwm_gen_resetn,
output [31:0] pwm_width[0:N_PWMS],
output [31:0] pwm_period[0:N_PWMS],
output [31:0] pwm_offset[0:N_PWMS],
output load_config,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack
);
// internal registers
reg [31:0] up_scratch = 'd0;
reg [31:0] up_pwm_width[0:N_PWMS] = PULSE_WIDTH_G[0:N_PWMS];
reg [31:0] up_pwm_period[0:N_PWMS] = PULSE_PERIOD_G[0:N_PWMS];
reg [31:0] up_pwm_offset[0:N_PWMS] = PULSE_OFFSET_G[0:N_PWMS];
reg up_load_config = 1'b0;
reg up_reset = 1'b1;
genvar n;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_pwm_width = PULSE_WIDTH_G[0:N_PWMS];
up_pwm_period = PULSE_PERIOD_G[0:N_PWMS];
up_pwm_offset = PULSE_OFFSET_G[0:N_PWMS];
up_load_config <= 1'b0;
up_reset <= 1'b1;
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr == 14'h2)) begin
up_scratch <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr == 14'h4)) begin
up_reset <= up_wdata[0];
up_load_config <= up_wdata[1];
end else begin
up_load_config <= 1'b0;
end
for (int i = 0; i <= N_PWMS; i++) begin
if ((up_wreq == 1'b1) && (up_waddr == 14'h10 + i)) begin
up_pwm_period[i] <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr == 14'h20 + i)) begin
up_pwm_width[i] <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr == 14'h30 + i)) begin
up_pwm_offset[i] <= up_wdata;
end
end
end
end
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq;
if (up_rreq == 1'b1) begin
if (up_raddr[13:4] == 10'd0) begin
case (up_raddr)
14'h0: up_rdata <= CORE_VERSION;
14'h1: up_rdata <= ID;
14'h2: up_rdata <= up_scratch;
14'h3: up_rdata <= CORE_MAGIC;
14'h4: up_rdata <= up_reset;
14'h5: up_rdata <= N_PWMS +1;
default: up_rdata <= 0;
endcase
end else if (up_raddr[3:0] > N_PWMS) begin
up_rdata <= 32'b0;
end else if (up_raddr[13:4] == 10'd1) begin
up_rdata <= up_pwm_period[up_raddr[3:0]];
end else if (up_raddr[13:4] == 10'd2) begin
up_rdata <= up_pwm_width[up_raddr[3:0]];
end else if (up_raddr[13:4] == 10'd3) begin
up_rdata <= up_pwm_offset[up_raddr[3:0]];
end
end else begin
up_rdata <= 32'd0;
end
end
end
generate
if (ASYNC_CLK_EN) begin : counter_external_clock
assign clk_out = ext_clk;
ad_rst i_d_rst_reg (
.rst_async (up_reset),
.clk (clk_out),
.rstn (pwm_gen_resetn),
.rst ());
for (n = 0; n <= N_PWMS; n = n + 1) begin: up_to_adc_cdc
sync_data #(
.NUM_OF_BITS (96),
.ASYNC_CLK (1))
i_pwm_props (
.in_clk (up_clk),
.in_data ({up_pwm_period[n],
up_pwm_width[n],
up_pwm_offset[n]}),
.out_clk (clk_out),
.out_data ({pwm_period[n],
pwm_width[n],
pwm_offset[n]}));
end
sync_event #(
.NUM_OF_EVENTS (1),
.ASYNC_CLK (1)
) i_load_config_sync (
.in_clk (up_clk),
.in_event (up_load_config),
.out_clk (clk_out),
.out_event (load_config));
end else begin : counter_sys_clock // counter is running on system clk
assign clk_out = up_clk;
assign pwm_gen_resetn = ~up_reset;
for (n = 0; n <= N_PWMS; n = n + 1) begin: up_cd
assign pwm_period[n] = up_pwm_period[n];
assign pwm_width[n] = up_pwm_width[n];
assign pwm_offset[n] = up_pwm_offset[n];
end
assign load_config = up_load_config;
end
endgenerate
endmodule
adi_library/axi_pwm_gen/component.xml
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adi_library/axi_pwm_gen/xgui/axi_pwm_gen_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set AXI_PWM_Generator [ipgui::add_page $IPINST -name "AXI PWM Generator"]
set ASYNC_CLK_EN [ipgui::add_param $IPINST -name "ASYNC_CLK_EN" -parent ${AXI_PWM_Generator}]
set_property tooltip {External clock for the counter} ${ASYNC_CLK_EN}
set EXT_ASYNC_SYNC [ipgui::add_param $IPINST -name "EXT_ASYNC_SYNC" -parent ${AXI_PWM_Generator} -widget checkBox]
set_property tooltip {NOTE: If active the ext_sync will be delayed 2 clock cycles.} ${EXT_ASYNC_SYNC}
ipgui::add_param $IPINST -name "N_PWMS" -parent ${AXI_PWM_Generator}
set PWM_EXT_SYNC [ipgui::add_param $IPINST -name "PWM_EXT_SYNC" -parent ${AXI_PWM_Generator} -widget checkBox]
set_property tooltip {NOTE: If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before deaserting the ext_sync} ${PWM_EXT_SYNC}
set PULSE_0_WIDTH [ipgui::add_param $IPINST -name "PULSE_0_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_0_WIDTH}
set PULSE_0_PERIOD [ipgui::add_param $IPINST -name "PULSE_0_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_0_PERIOD}
set PULSE_0_OFFSET [ipgui::add_param $IPINST -name "PULSE_0_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_0_OFFSET}
set PULSE_1_WIDTH [ipgui::add_param $IPINST -name "PULSE_1_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_1_WIDTH}
set PULSE_1_PERIOD [ipgui::add_param $IPINST -name "PULSE_1_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_1_PERIOD}
set PULSE_1_OFFSET [ipgui::add_param $IPINST -name "PULSE_1_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_1_OFFSET}
set PULSE_2_WIDTH [ipgui::add_param $IPINST -name "PULSE_2_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_2_WIDTH}
set PULSE_2_PERIOD [ipgui::add_param $IPINST -name "PULSE_2_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_2_PERIOD}
set PULSE_2_OFFSET [ipgui::add_param $IPINST -name "PULSE_2_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_2_OFFSET}
set PULSE_3_WIDTH [ipgui::add_param $IPINST -name "PULSE_3_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_3_WIDTH}
set PULSE_3_PERIOD [ipgui::add_param $IPINST -name "PULSE_3_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_3_PERIOD}
set PULSE_3_OFFSET [ipgui::add_param $IPINST -name "PULSE_3_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_3_OFFSET}
set PULSE_4_WIDTH [ipgui::add_param $IPINST -name "PULSE_4_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_4_WIDTH}
set PULSE_4_PERIOD [ipgui::add_param $IPINST -name "PULSE_4_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_4_PERIOD}
set PULSE_4_OFFSET [ipgui::add_param $IPINST -name "PULSE_4_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_4_OFFSET}
set PULSE_5_WIDTH [ipgui::add_param $IPINST -name "PULSE_5_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_5_WIDTH}
set PULSE_5_PERIOD [ipgui::add_param $IPINST -name "PULSE_5_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_5_PERIOD}
set PULSE_5_OFFSET [ipgui::add_param $IPINST -name "PULSE_5_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_5_OFFSET}
set PULSE_6_WIDTH [ipgui::add_param $IPINST -name "PULSE_6_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_6_WIDTH}
set PULSE_6_PERIOD [ipgui::add_param $IPINST -name "PULSE_6_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_6_PERIOD}
set PULSE_6_OFFSET [ipgui::add_param $IPINST -name "PULSE_6_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_6_OFFSET}
set PULSE_7_WIDTH [ipgui::add_param $IPINST -name "PULSE_7_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_7_WIDTH}
set PULSE_7_PERIOD [ipgui::add_param $IPINST -name "PULSE_7_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_7_PERIOD}
set PULSE_7_OFFSET [ipgui::add_param $IPINST -name "PULSE_7_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_7_OFFSET}
set PULSE_8_WIDTH [ipgui::add_param $IPINST -name "PULSE_8_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_8_WIDTH}
set PULSE_8_PERIOD [ipgui::add_param $IPINST -name "PULSE_8_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_8_PERIOD}
set PULSE_8_OFFSET [ipgui::add_param $IPINST -name "PULSE_8_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_8_OFFSET}
set PULSE_9_WIDTH [ipgui::add_param $IPINST -name "PULSE_9_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_9_WIDTH}
set PULSE_9_PERIOD [ipgui::add_param $IPINST -name "PULSE_9_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_9_PERIOD}
set PULSE_9_OFFSET [ipgui::add_param $IPINST -name "PULSE_9_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_9_OFFSET}
set PULSE_10_WIDTH [ipgui::add_param $IPINST -name "PULSE_10_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_10_WIDTH}
set PULSE_10_PERIOD [ipgui::add_param $IPINST -name "PULSE_10_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_10_PERIOD}
set PULSE_10_OFFSET [ipgui::add_param $IPINST -name "PULSE_10_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_10_OFFSET}
set PULSE_11_WIDTH [ipgui::add_param $IPINST -name "PULSE_11_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_11_WIDTH}
set PULSE_11_PERIOD [ipgui::add_param $IPINST -name "PULSE_11_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_11_PERIOD}
set PULSE_11_OFFSET [ipgui::add_param $IPINST -name "PULSE_11_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_11_OFFSET}
set PULSE_12_WIDTH [ipgui::add_param $IPINST -name "PULSE_12_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_12_WIDTH}
set PULSE_12_PERIOD [ipgui::add_param $IPINST -name "PULSE_12_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_12_PERIOD}
set PULSE_12_OFFSET [ipgui::add_param $IPINST -name "PULSE_12_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_12_OFFSET}
set PULSE_13_WIDTH [ipgui::add_param $IPINST -name "PULSE_13_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_13_WIDTH}
set PULSE_13_PERIOD [ipgui::add_param $IPINST -name "PULSE_13_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_13_PERIOD}
set PULSE_13_OFFSET [ipgui::add_param $IPINST -name "PULSE_13_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_13_OFFSET}
set PULSE_14_WIDTH [ipgui::add_param $IPINST -name "PULSE_14_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_14_WIDTH}
set PULSE_14_PERIOD [ipgui::add_param $IPINST -name "PULSE_14_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_14_PERIOD}
set PULSE_14_OFFSET [ipgui::add_param $IPINST -name "PULSE_14_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_14_OFFSET}
set PULSE_15_WIDTH [ipgui::add_param $IPINST -name "PULSE_15_WIDTH" -parent ${AXI_PWM_Generator}]
set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_15_WIDTH}
set PULSE_15_PERIOD [ipgui::add_param $IPINST -name "PULSE_15_PERIOD" -parent ${AXI_PWM_Generator}]
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_15_PERIOD}
set PULSE_15_OFFSET [ipgui::add_param $IPINST -name "PULSE_15_OFFSET" -parent ${AXI_PWM_Generator}]
set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_15_OFFSET}
}
proc update_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } {
# Procedure called to update ASYNC_CLK_EN when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } {
# Procedure called to validate ASYNC_CLK_EN
return true
}
proc update_PARAM_VALUE.EXT_ASYNC_SYNC { PARAM_VALUE.EXT_ASYNC_SYNC } {
# Procedure called to update EXT_ASYNC_SYNC when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.EXT_ASYNC_SYNC { PARAM_VALUE.EXT_ASYNC_SYNC } {
# Procedure called to validate EXT_ASYNC_SYNC
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.N_PWMS { PARAM_VALUE.N_PWMS } {
# Procedure called to update N_PWMS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.N_PWMS { PARAM_VALUE.N_PWMS } {
# Procedure called to validate N_PWMS
return true
}
proc update_PARAM_VALUE.PULSE_0_OFFSET { PARAM_VALUE.PULSE_0_OFFSET } {
# Procedure called to update PULSE_0_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_0_OFFSET { PARAM_VALUE.PULSE_0_OFFSET } {
# Procedure called to validate PULSE_0_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_0_PERIOD { PARAM_VALUE.PULSE_0_PERIOD } {
# Procedure called to update PULSE_0_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_0_PERIOD { PARAM_VALUE.PULSE_0_PERIOD } {
# Procedure called to validate PULSE_0_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_0_WIDTH { PARAM_VALUE.PULSE_0_WIDTH } {
# Procedure called to update PULSE_0_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_0_WIDTH { PARAM_VALUE.PULSE_0_WIDTH } {
# Procedure called to validate PULSE_0_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_10_OFFSET { PARAM_VALUE.PULSE_10_OFFSET } {
# Procedure called to update PULSE_10_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_10_OFFSET { PARAM_VALUE.PULSE_10_OFFSET } {
# Procedure called to validate PULSE_10_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_10_PERIOD { PARAM_VALUE.PULSE_10_PERIOD } {
# Procedure called to update PULSE_10_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_10_PERIOD { PARAM_VALUE.PULSE_10_PERIOD } {
# Procedure called to validate PULSE_10_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_10_WIDTH { PARAM_VALUE.PULSE_10_WIDTH } {
# Procedure called to update PULSE_10_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_10_WIDTH { PARAM_VALUE.PULSE_10_WIDTH } {
# Procedure called to validate PULSE_10_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_11_OFFSET { PARAM_VALUE.PULSE_11_OFFSET } {
# Procedure called to update PULSE_11_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_11_OFFSET { PARAM_VALUE.PULSE_11_OFFSET } {
# Procedure called to validate PULSE_11_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_11_PERIOD { PARAM_VALUE.PULSE_11_PERIOD } {
# Procedure called to update PULSE_11_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_11_PERIOD { PARAM_VALUE.PULSE_11_PERIOD } {
# Procedure called to validate PULSE_11_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_11_WIDTH { PARAM_VALUE.PULSE_11_WIDTH } {
# Procedure called to update PULSE_11_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_11_WIDTH { PARAM_VALUE.PULSE_11_WIDTH } {
# Procedure called to validate PULSE_11_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_12_OFFSET { PARAM_VALUE.PULSE_12_OFFSET } {
# Procedure called to update PULSE_12_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_12_OFFSET { PARAM_VALUE.PULSE_12_OFFSET } {
# Procedure called to validate PULSE_12_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_12_PERIOD { PARAM_VALUE.PULSE_12_PERIOD } {
# Procedure called to update PULSE_12_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_12_PERIOD { PARAM_VALUE.PULSE_12_PERIOD } {
# Procedure called to validate PULSE_12_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_12_WIDTH { PARAM_VALUE.PULSE_12_WIDTH } {
# Procedure called to update PULSE_12_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_12_WIDTH { PARAM_VALUE.PULSE_12_WIDTH } {
# Procedure called to validate PULSE_12_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_13_OFFSET { PARAM_VALUE.PULSE_13_OFFSET } {
# Procedure called to update PULSE_13_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_13_OFFSET { PARAM_VALUE.PULSE_13_OFFSET } {
# Procedure called to validate PULSE_13_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_13_PERIOD { PARAM_VALUE.PULSE_13_PERIOD } {
# Procedure called to update PULSE_13_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_13_PERIOD { PARAM_VALUE.PULSE_13_PERIOD } {
# Procedure called to validate PULSE_13_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_13_WIDTH { PARAM_VALUE.PULSE_13_WIDTH } {
# Procedure called to update PULSE_13_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_13_WIDTH { PARAM_VALUE.PULSE_13_WIDTH } {
# Procedure called to validate PULSE_13_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_14_OFFSET { PARAM_VALUE.PULSE_14_OFFSET } {
# Procedure called to update PULSE_14_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_14_OFFSET { PARAM_VALUE.PULSE_14_OFFSET } {
# Procedure called to validate PULSE_14_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_14_PERIOD { PARAM_VALUE.PULSE_14_PERIOD } {
# Procedure called to update PULSE_14_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_14_PERIOD { PARAM_VALUE.PULSE_14_PERIOD } {
# Procedure called to validate PULSE_14_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_14_WIDTH { PARAM_VALUE.PULSE_14_WIDTH } {
# Procedure called to update PULSE_14_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_14_WIDTH { PARAM_VALUE.PULSE_14_WIDTH } {
# Procedure called to validate PULSE_14_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_15_OFFSET { PARAM_VALUE.PULSE_15_OFFSET } {
# Procedure called to update PULSE_15_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_15_OFFSET { PARAM_VALUE.PULSE_15_OFFSET } {
# Procedure called to validate PULSE_15_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_15_PERIOD { PARAM_VALUE.PULSE_15_PERIOD } {
# Procedure called to update PULSE_15_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_15_PERIOD { PARAM_VALUE.PULSE_15_PERIOD } {
# Procedure called to validate PULSE_15_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_15_WIDTH { PARAM_VALUE.PULSE_15_WIDTH } {
# Procedure called to update PULSE_15_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_15_WIDTH { PARAM_VALUE.PULSE_15_WIDTH } {
# Procedure called to validate PULSE_15_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_1_OFFSET { PARAM_VALUE.PULSE_1_OFFSET } {
# Procedure called to update PULSE_1_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_1_OFFSET { PARAM_VALUE.PULSE_1_OFFSET } {
# Procedure called to validate PULSE_1_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_1_PERIOD { PARAM_VALUE.PULSE_1_PERIOD } {
# Procedure called to update PULSE_1_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_1_PERIOD { PARAM_VALUE.PULSE_1_PERIOD } {
# Procedure called to validate PULSE_1_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_1_WIDTH { PARAM_VALUE.PULSE_1_WIDTH } {
# Procedure called to update PULSE_1_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_1_WIDTH { PARAM_VALUE.PULSE_1_WIDTH } {
# Procedure called to validate PULSE_1_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_2_OFFSET { PARAM_VALUE.PULSE_2_OFFSET } {
# Procedure called to update PULSE_2_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_2_OFFSET { PARAM_VALUE.PULSE_2_OFFSET } {
# Procedure called to validate PULSE_2_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_2_PERIOD { PARAM_VALUE.PULSE_2_PERIOD } {
# Procedure called to update PULSE_2_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_2_PERIOD { PARAM_VALUE.PULSE_2_PERIOD } {
# Procedure called to validate PULSE_2_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_2_WIDTH { PARAM_VALUE.PULSE_2_WIDTH } {
# Procedure called to update PULSE_2_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_2_WIDTH { PARAM_VALUE.PULSE_2_WIDTH } {
# Procedure called to validate PULSE_2_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_3_OFFSET { PARAM_VALUE.PULSE_3_OFFSET } {
# Procedure called to update PULSE_3_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_3_OFFSET { PARAM_VALUE.PULSE_3_OFFSET } {
# Procedure called to validate PULSE_3_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_3_PERIOD { PARAM_VALUE.PULSE_3_PERIOD } {
# Procedure called to update PULSE_3_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_3_PERIOD { PARAM_VALUE.PULSE_3_PERIOD } {
# Procedure called to validate PULSE_3_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_3_WIDTH { PARAM_VALUE.PULSE_3_WIDTH } {
# Procedure called to update PULSE_3_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_3_WIDTH { PARAM_VALUE.PULSE_3_WIDTH } {
# Procedure called to validate PULSE_3_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_4_OFFSET { PARAM_VALUE.PULSE_4_OFFSET } {
# Procedure called to update PULSE_4_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_4_OFFSET { PARAM_VALUE.PULSE_4_OFFSET } {
# Procedure called to validate PULSE_4_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_4_PERIOD { PARAM_VALUE.PULSE_4_PERIOD } {
# Procedure called to update PULSE_4_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_4_PERIOD { PARAM_VALUE.PULSE_4_PERIOD } {
# Procedure called to validate PULSE_4_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_4_WIDTH { PARAM_VALUE.PULSE_4_WIDTH } {
# Procedure called to update PULSE_4_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_4_WIDTH { PARAM_VALUE.PULSE_4_WIDTH } {
# Procedure called to validate PULSE_4_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_5_OFFSET { PARAM_VALUE.PULSE_5_OFFSET } {
# Procedure called to update PULSE_5_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_5_OFFSET { PARAM_VALUE.PULSE_5_OFFSET } {
# Procedure called to validate PULSE_5_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_5_PERIOD { PARAM_VALUE.PULSE_5_PERIOD } {
# Procedure called to update PULSE_5_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_5_PERIOD { PARAM_VALUE.PULSE_5_PERIOD } {
# Procedure called to validate PULSE_5_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_5_WIDTH { PARAM_VALUE.PULSE_5_WIDTH } {
# Procedure called to update PULSE_5_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_5_WIDTH { PARAM_VALUE.PULSE_5_WIDTH } {
# Procedure called to validate PULSE_5_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_6_OFFSET { PARAM_VALUE.PULSE_6_OFFSET } {
# Procedure called to update PULSE_6_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_6_OFFSET { PARAM_VALUE.PULSE_6_OFFSET } {
# Procedure called to validate PULSE_6_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_6_PERIOD { PARAM_VALUE.PULSE_6_PERIOD } {
# Procedure called to update PULSE_6_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_6_PERIOD { PARAM_VALUE.PULSE_6_PERIOD } {
# Procedure called to validate PULSE_6_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_6_WIDTH { PARAM_VALUE.PULSE_6_WIDTH } {
# Procedure called to update PULSE_6_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_6_WIDTH { PARAM_VALUE.PULSE_6_WIDTH } {
# Procedure called to validate PULSE_6_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_7_OFFSET { PARAM_VALUE.PULSE_7_OFFSET } {
# Procedure called to update PULSE_7_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_7_OFFSET { PARAM_VALUE.PULSE_7_OFFSET } {
# Procedure called to validate PULSE_7_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_7_PERIOD { PARAM_VALUE.PULSE_7_PERIOD } {
# Procedure called to update PULSE_7_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_7_PERIOD { PARAM_VALUE.PULSE_7_PERIOD } {
# Procedure called to validate PULSE_7_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_7_WIDTH { PARAM_VALUE.PULSE_7_WIDTH } {
# Procedure called to update PULSE_7_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_7_WIDTH { PARAM_VALUE.PULSE_7_WIDTH } {
# Procedure called to validate PULSE_7_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_8_OFFSET { PARAM_VALUE.PULSE_8_OFFSET } {
# Procedure called to update PULSE_8_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_8_OFFSET { PARAM_VALUE.PULSE_8_OFFSET } {
# Procedure called to validate PULSE_8_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_8_PERIOD { PARAM_VALUE.PULSE_8_PERIOD } {
# Procedure called to update PULSE_8_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_8_PERIOD { PARAM_VALUE.PULSE_8_PERIOD } {
# Procedure called to validate PULSE_8_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_8_WIDTH { PARAM_VALUE.PULSE_8_WIDTH } {
# Procedure called to update PULSE_8_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_8_WIDTH { PARAM_VALUE.PULSE_8_WIDTH } {
# Procedure called to validate PULSE_8_WIDTH
return true
}
proc update_PARAM_VALUE.PULSE_9_OFFSET { PARAM_VALUE.PULSE_9_OFFSET } {
# Procedure called to update PULSE_9_OFFSET when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_9_OFFSET { PARAM_VALUE.PULSE_9_OFFSET } {
# Procedure called to validate PULSE_9_OFFSET
return true
}
proc update_PARAM_VALUE.PULSE_9_PERIOD { PARAM_VALUE.PULSE_9_PERIOD } {
# Procedure called to update PULSE_9_PERIOD when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_9_PERIOD { PARAM_VALUE.PULSE_9_PERIOD } {
# Procedure called to validate PULSE_9_PERIOD
return true
}
proc update_PARAM_VALUE.PULSE_9_WIDTH { PARAM_VALUE.PULSE_9_WIDTH } {
# Procedure called to update PULSE_9_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PULSE_9_WIDTH { PARAM_VALUE.PULSE_9_WIDTH } {
# Procedure called to validate PULSE_9_WIDTH
return true
}
proc update_PARAM_VALUE.PWM_EXT_SYNC { PARAM_VALUE.PWM_EXT_SYNC } {
# Procedure called to update PWM_EXT_SYNC when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PWM_EXT_SYNC { PARAM_VALUE.PWM_EXT_SYNC } {
# Procedure called to validate PWM_EXT_SYNC
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.ASYNC_CLK_EN { MODELPARAM_VALUE.ASYNC_CLK_EN PARAM_VALUE.ASYNC_CLK_EN } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_EN}] ${MODELPARAM_VALUE.ASYNC_CLK_EN}
}
proc update_MODELPARAM_VALUE.N_PWMS { MODELPARAM_VALUE.N_PWMS PARAM_VALUE.N_PWMS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.N_PWMS}] ${MODELPARAM_VALUE.N_PWMS}
}
proc update_MODELPARAM_VALUE.PWM_EXT_SYNC { MODELPARAM_VALUE.PWM_EXT_SYNC PARAM_VALUE.PWM_EXT_SYNC } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PWM_EXT_SYNC}] ${MODELPARAM_VALUE.PWM_EXT_SYNC}
}
proc update_MODELPARAM_VALUE.EXT_ASYNC_SYNC { MODELPARAM_VALUE.EXT_ASYNC_SYNC PARAM_VALUE.EXT_ASYNC_SYNC } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.EXT_ASYNC_SYNC}] ${MODELPARAM_VALUE.EXT_ASYNC_SYNC}
}
proc update_MODELPARAM_VALUE.PULSE_0_WIDTH { MODELPARAM_VALUE.PULSE_0_WIDTH PARAM_VALUE.PULSE_0_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_0_WIDTH}] ${MODELPARAM_VALUE.PULSE_0_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_1_WIDTH { MODELPARAM_VALUE.PULSE_1_WIDTH PARAM_VALUE.PULSE_1_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_1_WIDTH}] ${MODELPARAM_VALUE.PULSE_1_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_2_WIDTH { MODELPARAM_VALUE.PULSE_2_WIDTH PARAM_VALUE.PULSE_2_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_2_WIDTH}] ${MODELPARAM_VALUE.PULSE_2_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_3_WIDTH { MODELPARAM_VALUE.PULSE_3_WIDTH PARAM_VALUE.PULSE_3_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_3_WIDTH}] ${MODELPARAM_VALUE.PULSE_3_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_4_WIDTH { MODELPARAM_VALUE.PULSE_4_WIDTH PARAM_VALUE.PULSE_4_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_4_WIDTH}] ${MODELPARAM_VALUE.PULSE_4_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_5_WIDTH { MODELPARAM_VALUE.PULSE_5_WIDTH PARAM_VALUE.PULSE_5_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_5_WIDTH}] ${MODELPARAM_VALUE.PULSE_5_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_6_WIDTH { MODELPARAM_VALUE.PULSE_6_WIDTH PARAM_VALUE.PULSE_6_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_6_WIDTH}] ${MODELPARAM_VALUE.PULSE_6_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_7_WIDTH { MODELPARAM_VALUE.PULSE_7_WIDTH PARAM_VALUE.PULSE_7_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_7_WIDTH}] ${MODELPARAM_VALUE.PULSE_7_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_8_WIDTH { MODELPARAM_VALUE.PULSE_8_WIDTH PARAM_VALUE.PULSE_8_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_8_WIDTH}] ${MODELPARAM_VALUE.PULSE_8_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_9_WIDTH { MODELPARAM_VALUE.PULSE_9_WIDTH PARAM_VALUE.PULSE_9_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_9_WIDTH}] ${MODELPARAM_VALUE.PULSE_9_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_10_WIDTH { MODELPARAM_VALUE.PULSE_10_WIDTH PARAM_VALUE.PULSE_10_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_10_WIDTH}] ${MODELPARAM_VALUE.PULSE_10_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_11_WIDTH { MODELPARAM_VALUE.PULSE_11_WIDTH PARAM_VALUE.PULSE_11_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_11_WIDTH}] ${MODELPARAM_VALUE.PULSE_11_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_12_WIDTH { MODELPARAM_VALUE.PULSE_12_WIDTH PARAM_VALUE.PULSE_12_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_12_WIDTH}] ${MODELPARAM_VALUE.PULSE_12_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_13_WIDTH { MODELPARAM_VALUE.PULSE_13_WIDTH PARAM_VALUE.PULSE_13_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_13_WIDTH}] ${MODELPARAM_VALUE.PULSE_13_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_14_WIDTH { MODELPARAM_VALUE.PULSE_14_WIDTH PARAM_VALUE.PULSE_14_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_14_WIDTH}] ${MODELPARAM_VALUE.PULSE_14_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_15_WIDTH { MODELPARAM_VALUE.PULSE_15_WIDTH PARAM_VALUE.PULSE_15_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_15_WIDTH}] ${MODELPARAM_VALUE.PULSE_15_WIDTH}
}
proc update_MODELPARAM_VALUE.PULSE_0_PERIOD { MODELPARAM_VALUE.PULSE_0_PERIOD PARAM_VALUE.PULSE_0_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_0_PERIOD}] ${MODELPARAM_VALUE.PULSE_0_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_1_PERIOD { MODELPARAM_VALUE.PULSE_1_PERIOD PARAM_VALUE.PULSE_1_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_1_PERIOD}] ${MODELPARAM_VALUE.PULSE_1_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_2_PERIOD { MODELPARAM_VALUE.PULSE_2_PERIOD PARAM_VALUE.PULSE_2_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_2_PERIOD}] ${MODELPARAM_VALUE.PULSE_2_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_3_PERIOD { MODELPARAM_VALUE.PULSE_3_PERIOD PARAM_VALUE.PULSE_3_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_3_PERIOD}] ${MODELPARAM_VALUE.PULSE_3_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_4_PERIOD { MODELPARAM_VALUE.PULSE_4_PERIOD PARAM_VALUE.PULSE_4_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_4_PERIOD}] ${MODELPARAM_VALUE.PULSE_4_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_5_PERIOD { MODELPARAM_VALUE.PULSE_5_PERIOD PARAM_VALUE.PULSE_5_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_5_PERIOD}] ${MODELPARAM_VALUE.PULSE_5_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_6_PERIOD { MODELPARAM_VALUE.PULSE_6_PERIOD PARAM_VALUE.PULSE_6_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_6_PERIOD}] ${MODELPARAM_VALUE.PULSE_6_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_7_PERIOD { MODELPARAM_VALUE.PULSE_7_PERIOD PARAM_VALUE.PULSE_7_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_7_PERIOD}] ${MODELPARAM_VALUE.PULSE_7_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_8_PERIOD { MODELPARAM_VALUE.PULSE_8_PERIOD PARAM_VALUE.PULSE_8_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_8_PERIOD}] ${MODELPARAM_VALUE.PULSE_8_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_9_PERIOD { MODELPARAM_VALUE.PULSE_9_PERIOD PARAM_VALUE.PULSE_9_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_9_PERIOD}] ${MODELPARAM_VALUE.PULSE_9_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_10_PERIOD { MODELPARAM_VALUE.PULSE_10_PERIOD PARAM_VALUE.PULSE_10_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_10_PERIOD}] ${MODELPARAM_VALUE.PULSE_10_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_11_PERIOD { MODELPARAM_VALUE.PULSE_11_PERIOD PARAM_VALUE.PULSE_11_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_11_PERIOD}] ${MODELPARAM_VALUE.PULSE_11_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_12_PERIOD { MODELPARAM_VALUE.PULSE_12_PERIOD PARAM_VALUE.PULSE_12_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_12_PERIOD}] ${MODELPARAM_VALUE.PULSE_12_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_13_PERIOD { MODELPARAM_VALUE.PULSE_13_PERIOD PARAM_VALUE.PULSE_13_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_13_PERIOD}] ${MODELPARAM_VALUE.PULSE_13_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_14_PERIOD { MODELPARAM_VALUE.PULSE_14_PERIOD PARAM_VALUE.PULSE_14_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_14_PERIOD}] ${MODELPARAM_VALUE.PULSE_14_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_15_PERIOD { MODELPARAM_VALUE.PULSE_15_PERIOD PARAM_VALUE.PULSE_15_PERIOD } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_15_PERIOD}] ${MODELPARAM_VALUE.PULSE_15_PERIOD}
}
proc update_MODELPARAM_VALUE.PULSE_0_OFFSET { MODELPARAM_VALUE.PULSE_0_OFFSET PARAM_VALUE.PULSE_0_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_0_OFFSET}] ${MODELPARAM_VALUE.PULSE_0_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_1_OFFSET { MODELPARAM_VALUE.PULSE_1_OFFSET PARAM_VALUE.PULSE_1_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_1_OFFSET}] ${MODELPARAM_VALUE.PULSE_1_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_2_OFFSET { MODELPARAM_VALUE.PULSE_2_OFFSET PARAM_VALUE.PULSE_2_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_2_OFFSET}] ${MODELPARAM_VALUE.PULSE_2_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_3_OFFSET { MODELPARAM_VALUE.PULSE_3_OFFSET PARAM_VALUE.PULSE_3_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_3_OFFSET}] ${MODELPARAM_VALUE.PULSE_3_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_4_OFFSET { MODELPARAM_VALUE.PULSE_4_OFFSET PARAM_VALUE.PULSE_4_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_4_OFFSET}] ${MODELPARAM_VALUE.PULSE_4_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_5_OFFSET { MODELPARAM_VALUE.PULSE_5_OFFSET PARAM_VALUE.PULSE_5_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_5_OFFSET}] ${MODELPARAM_VALUE.PULSE_5_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_6_OFFSET { MODELPARAM_VALUE.PULSE_6_OFFSET PARAM_VALUE.PULSE_6_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_6_OFFSET}] ${MODELPARAM_VALUE.PULSE_6_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_7_OFFSET { MODELPARAM_VALUE.PULSE_7_OFFSET PARAM_VALUE.PULSE_7_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_7_OFFSET}] ${MODELPARAM_VALUE.PULSE_7_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_8_OFFSET { MODELPARAM_VALUE.PULSE_8_OFFSET PARAM_VALUE.PULSE_8_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_8_OFFSET}] ${MODELPARAM_VALUE.PULSE_8_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_9_OFFSET { MODELPARAM_VALUE.PULSE_9_OFFSET PARAM_VALUE.PULSE_9_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_9_OFFSET}] ${MODELPARAM_VALUE.PULSE_9_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_10_OFFSET { MODELPARAM_VALUE.PULSE_10_OFFSET PARAM_VALUE.PULSE_10_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_10_OFFSET}] ${MODELPARAM_VALUE.PULSE_10_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_11_OFFSET { MODELPARAM_VALUE.PULSE_11_OFFSET PARAM_VALUE.PULSE_11_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_11_OFFSET}] ${MODELPARAM_VALUE.PULSE_11_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_12_OFFSET { MODELPARAM_VALUE.PULSE_12_OFFSET PARAM_VALUE.PULSE_12_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_12_OFFSET}] ${MODELPARAM_VALUE.PULSE_12_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_13_OFFSET { MODELPARAM_VALUE.PULSE_13_OFFSET PARAM_VALUE.PULSE_13_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_13_OFFSET}] ${MODELPARAM_VALUE.PULSE_13_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_14_OFFSET { MODELPARAM_VALUE.PULSE_14_OFFSET PARAM_VALUE.PULSE_14_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_14_OFFSET}] ${MODELPARAM_VALUE.PULSE_14_OFFSET}
}
proc update_MODELPARAM_VALUE.PULSE_15_OFFSET { MODELPARAM_VALUE.PULSE_15_OFFSET PARAM_VALUE.PULSE_15_OFFSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PULSE_15_OFFSET}] ${MODELPARAM_VALUE.PULSE_15_OFFSET}
}