initial commit, add dds_par module
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_tdd_channel #(
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parameter DEFAULT_POLARITY = 0,
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parameter REGISTER_WIDTH = 32
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) (
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input logic clk,
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input logic resetn,
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input logic [REGISTER_WIDTH-1:0] tdd_counter,
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input axi_tdd_pkg::state_t tdd_cstate,
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input logic tdd_enable,
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input logic tdd_endof_frame,
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input logic ch_en,
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input logic asy_ch_pol,
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input logic [REGISTER_WIDTH-1:0] asy_t_high,
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input logic [REGISTER_WIDTH-1:0] asy_t_low,
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output logic out
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);
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// package import
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import axi_tdd_pkg::*;
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// internal registers
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logic ch_pol;
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logic [REGISTER_WIDTH-1:0] t_high;
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logic [REGISTER_WIDTH-1:0] t_low;
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logic tdd_ch_en;
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logic tdd_ch_set;
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logic tdd_ch_rst;
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// initial values
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initial begin
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tdd_ch_en = 1'b0;
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tdd_ch_set = 1'b0;
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tdd_ch_rst = 1'b0;
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out = 1'b0;
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end
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// Connect the enable signal to the enable flop lines
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(* direct_enable = "yes" *) logic enable;
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assign enable = tdd_enable;
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// Save the async register values only when the module is enabled
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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ch_pol <= DEFAULT_POLARITY;
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end else begin
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if (enable) begin
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ch_pol <= asy_ch_pol;
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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t_high <= '0;
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end else begin
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if (enable) begin
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t_high <= asy_t_high;
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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t_low <= '0;
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end else begin
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if (enable) begin
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t_low <= asy_t_low;
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end
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end
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end
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// TDD channel control signals
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_ch_en <= 1'b0;
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end else begin
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if (tdd_cstate == IDLE) begin
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tdd_ch_en <= 1'b0;
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end else begin
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if ((tdd_cstate == ARMED) || (tdd_endof_frame == 1'b1)) begin
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tdd_ch_en <= ch_en;
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end
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_ch_set <= 1'b0;
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end else begin
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if ((tdd_cstate == RUNNING) && (tdd_counter == t_high)) begin
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tdd_ch_set <= 1'b1;
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end else begin
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tdd_ch_set <= 1'b0;
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_ch_rst <= 1'b0;
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end else begin
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if (((tdd_cstate == RUNNING) && (tdd_counter == t_low)) || (tdd_endof_frame == 1'b1)) begin
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tdd_ch_rst <= 1'b1;
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end else begin
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tdd_ch_rst <= 1'b0;
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end
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end
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end
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// TDD channel output
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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out <= DEFAULT_POLARITY;
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end else begin
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if ((tdd_ch_en == 1'b0) || (tdd_ch_rst == 1'b1)) begin
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out <= ch_pol;
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end else begin
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if (tdd_ch_set == 1'b1) begin
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out <= ~ch_pol;
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end else begin
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out <= out;
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end
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end
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end
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end
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endmodule
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