initial commit, add dds_par module
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_tdd_counter #(
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parameter REGISTER_WIDTH = 32,
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parameter BURST_COUNT_WIDTH = 32
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) (
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input logic clk,
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input logic resetn,
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input logic tdd_enable,
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input logic tdd_sync_rst,
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input logic tdd_sync,
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input logic [BURST_COUNT_WIDTH-1:0] asy_tdd_burst_count,
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input logic [REGISTER_WIDTH-1:0] asy_tdd_startup_delay,
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input logic [REGISTER_WIDTH-1:0] asy_tdd_frame_length,
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output logic [REGISTER_WIDTH-1:0] tdd_counter,
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output axi_tdd_pkg::state_t tdd_cstate,
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output logic tdd_endof_frame
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);
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// package import
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import axi_tdd_pkg::*;
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// internal registers/wires
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logic [BURST_COUNT_WIDTH-1:0] tdd_burst_count;
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logic [REGISTER_WIDTH-1:0] tdd_startup_delay;
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logic [REGISTER_WIDTH-1:0] tdd_frame_length;
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logic [BURST_COUNT_WIDTH-1:0] tdd_burst_counter;
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logic tdd_delay_done;
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logic tdd_delay_skip;
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logic tdd_endof_burst;
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logic tdd_last_burst;
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state_t tdd_cstate_ns;
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// initial values
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initial begin
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tdd_burst_counter = '0;
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tdd_counter = '0;
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tdd_cstate = IDLE;
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tdd_cstate_ns = IDLE;
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tdd_delay_done = 1'b0;
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tdd_delay_skip = 1'b0;
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tdd_endof_frame = 1'b0;
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tdd_last_burst = 1'b0;
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end
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// Connect the enable signal to the enable flop lines
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(* direct_enable = "yes" *) logic enable;
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assign enable = tdd_enable;
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// Save the async register values only when the module is enabled
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_burst_count <= '0;
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end else begin
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if (enable) begin
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tdd_burst_count <= asy_tdd_burst_count;
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_startup_delay <= '0;
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end else begin
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if (enable) begin
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tdd_startup_delay <= asy_tdd_startup_delay;
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_frame_length <= '0;
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end else begin
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if (enable) begin
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tdd_frame_length <= asy_tdd_frame_length;
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end
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end
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end
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// TDD counter FSM
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_cstate <= IDLE;
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end else begin
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tdd_cstate <= tdd_cstate_ns;
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end
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end
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always @* begin
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tdd_cstate_ns = tdd_cstate;
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case (tdd_cstate)
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IDLE : begin
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if (tdd_enable == 1'b1) begin
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tdd_cstate_ns = ARMED;
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end
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end
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ARMED : begin
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if (tdd_enable == 1'b0) begin
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tdd_cstate_ns = IDLE;
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end else if (tdd_sync == 1'b1) begin
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tdd_cstate_ns = (tdd_delay_skip == 1'b1) ? RUNNING : WAITING;
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end
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end
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WAITING : begin
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if (tdd_delay_done == 1'b1) begin
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tdd_cstate_ns = RUNNING;
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end
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end
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RUNNING : begin
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if (tdd_endof_frame == 1'b1) begin
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tdd_cstate_ns = (tdd_endof_burst == 1'b1) ? (tdd_enable ? ARMED : IDLE) :
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(((tdd_burst_counter == 0) && !tdd_enable) ? IDLE : RUNNING);
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end
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end
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endcase
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end
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// TDD control signals
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_delay_done <= 1'b0;
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end else begin
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if (tdd_counter == (tdd_startup_delay - 1'b1)) begin
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tdd_delay_done <= 1'b1;
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end else begin
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tdd_delay_done <= 1'b0;
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_delay_skip <= 1'b0;
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end else begin
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if (tdd_startup_delay == 0) begin
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tdd_delay_skip <= 1'b1;
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end else begin
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tdd_delay_skip <= 1'b0;
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_endof_frame <= 1'b0;
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end else begin
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if (tdd_counter == (tdd_frame_length - 1'b1)) begin
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tdd_endof_frame <= 1'b1;
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end else begin
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tdd_endof_frame <= 1'b0;
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_last_burst <= 1'b0;
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end else begin
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tdd_last_burst <= (tdd_burst_counter == 1) ? 1'b1 : 1'b0;
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end
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end
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assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_endof_frame == 1'b1)) ? 1'b1 : 1'b0;
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// TDD free running counter
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_counter <= '0;
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end else begin
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if ((tdd_sync && tdd_sync_rst) == 1'b1) begin
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tdd_counter <= '0;
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end else begin
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if (tdd_cstate == WAITING) begin
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tdd_counter <= (tdd_delay_done == 1'b1) ? '0 : tdd_counter + 1'b1;
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end else begin
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if (tdd_cstate == RUNNING) begin
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tdd_counter <= (tdd_endof_frame == 1'b1) ? '0 : tdd_counter + 1'b1;
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end else begin
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tdd_counter <= '0;
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end
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end
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end
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end
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end
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// TDD burst counter
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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tdd_burst_counter <= '0;
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end else begin
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if (tdd_cstate == ARMED) begin
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tdd_burst_counter <= tdd_burst_count;
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end else begin
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if ((tdd_cstate == RUNNING) && (tdd_burst_counter != 0) && (tdd_endof_frame == 1'b1)) begin
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tdd_burst_counter <= tdd_burst_counter - 1'b1;
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end
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end
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end
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end
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endmodule
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