initial commit, add dds_par module
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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// Unpacker:
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// - unpack O_W number of data units from I_W number of data units
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// - data unit defined in bits by UNIT_W e.g 8 is a byte
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//
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// Constraints:
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// - O_W < I_W
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// - LATENCY 1
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// - no backpressure
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//
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// Data format:
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// idata [U(I_W-1) .... U(0)]
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// odata [U(O_W-1) .... U(0)]
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//
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// e.g
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// I_W = 6
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// O_W = 4
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// UNIT_W = 8
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//
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// idata : [B5,B4,B3,B2,B1,B0],[B11,B10,B9,B8,B7,B6]
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// odata : [B3,B2,B1,B0],[B7,B6,B5,B4],[B11,B10,B9,B8]
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//
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module ad_upack #(
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parameter I_W = 4,
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parameter O_W = 3,
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parameter UNIT_W = 8,
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parameter O_REG = 1
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) (
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input clk,
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input reset,
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input [I_W*UNIT_W-1:0] idata,
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input ivalid,
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output iready,
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output reg [O_W*UNIT_W-1:0] odata = 'h0,
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output reg ovalid = 'b0
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);
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// The Width of the shift reg is an integer multiple of output data width
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localparam SH_W = ((I_W/O_W) + ((I_W%O_W) > 0) + ((O_W % (I_W - ((I_W/O_W)*O_W) + ((I_W%O_W) == 0))) > 0))*O_W;
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// The Step of the algorithm is the greatest common divisor of I_W and O_W
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localparam STEP = gcd(I_W, O_W);
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localparam LATENCY = 1; // Minimum input latency from iready to ivalid
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integer i;
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reg [SH_W*UNIT_W-1:0] idata_sh;
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reg [SH_W*UNIT_W-1:0] idata_d = 'h0;
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reg [SH_W*UNIT_W-1:0] idata_d_nx;
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reg [SH_W-1:0] in_use = 'h0;
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reg [SH_W-1:0] inmask;
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wire [SH_W-1:0] out_mask = {O_W{1'b1}};
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wire [SH_W-1:0] in_use_nx;
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wire [SH_W-1:0] unit_valid;
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wire [O_W*UNIT_W-1:0] odata_s;
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wire ovalid_s;
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function [31:0] gcd;
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input [31:0] a;
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input [31:0] b;
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begin
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while (a != b) begin
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if (a > b) begin
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a = a-b;
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end else begin
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b = b-a;
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end
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end
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gcd = a;
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end
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endfunction
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assign unit_valid = (in_use | inmask);
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assign in_use_nx = unit_valid >> O_W;
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always @(posedge clk) begin
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if (reset) begin
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in_use <= 'h0;
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end else if (ovalid_s) begin
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in_use <= in_use_nx;
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end
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end
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always @(*) begin
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inmask = {I_W{ivalid}};
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for (i = STEP; i < O_W; i=i+STEP) begin
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if (in_use[i-1]) begin
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inmask = {I_W{ivalid}} << i;
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end
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end
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end
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always @(*) begin
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idata_d_nx = idata_d;
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if (ivalid) begin
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idata_d_nx = {{(SH_W-I_W)*UNIT_W{1'b0}},idata};
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for (i = STEP; i < O_W; i=i+STEP) begin
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if (in_use[i-1]) begin
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idata_d_nx = (idata << UNIT_W*i) | idata_d;
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end
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end
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end
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end
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always @(posedge clk) begin
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if (ovalid_s) begin
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idata_d <= idata_d_nx >> O_W*UNIT_W;
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end
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end
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assign iready = ~unit_valid[LATENCY*O_W + O_W -1];
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assign odata_s = idata_d_nx[O_W*UNIT_W-1:0];
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assign ovalid_s = unit_valid[O_W-1];
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generate
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if (O_REG) begin : o_reg
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always @(posedge clk) begin
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if (reset) begin
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ovalid <= 1'b0;
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end else begin
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ovalid <= ovalid_s;
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end
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end
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always @(posedge clk) begin
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odata <= odata_s;
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end
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end else begin
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always @(*) begin
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odata = odata_s;
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ovalid = ovalid_s;
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end
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end
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endgenerate
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endmodule
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