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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/common/tb/ad_mux_tb
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#!/bin/bash
SOURCE="ad_mux_tb.v"
SOURCE+=" ../ad_mux.v"
SOURCE+=" ../ad_mux_core.v"
cd `dirname $0`
source run_tb.sh
adi_library/common/tb/ad_mux_tb.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mux_tb;
parameter VCD_FILE = "ad_mux_tb.vcd";
parameter CH_W = 16; // Width of input channel
parameter CH_CNT = 64; // Number of input channels
parameter REQ_MUX_SZ = 8; // Size of mux which acts as a building block
parameter EN_REG = 1; // Enable register at output of each mux
localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
localparam NUM_STAGES = $clog2(CH_CNT) / $clog2(MUX_SZ) + |($clog2(CH_CNT) % $clog2(MUX_SZ));
localparam DW = CH_W*CH_CNT;
`include "tb_base.v"
reg [CH_W*CH_CNT-1:0] data_in = 'h0;
reg [$clog2(CH_CNT)-1:0] ch_sel = 'h0;
wire [CH_W-1:0] data_out;
ad_mux #(
.CH_W(CH_W),
.CH_CNT(CH_CNT),
.REQ_MUX_SZ(REQ_MUX_SZ),
.EN_REG(EN_REG)
) DUT (
.clk(clk),
.data_in(data_in),
.ch_sel(ch_sel),
.data_out(data_out));
wire [CH_W-1:0] ref_data;
generate
if (EN_REG) begin
integer ii;
reg [CH_W*CH_CNT-1:0] mux_pln [1:NUM_STAGES];
always @(posedge clk) begin
mux_pln[1] <= data_in >> ch_sel*CH_W;
for (ii=2; ii<=NUM_STAGES; ii=ii+1) begin
mux_pln[ii] <= mux_pln[ii-1];
end
end
assign ref_data = mux_pln[NUM_STAGES];
end else begin
assign ref_data = data_in >> ch_sel*CH_W;
end
endgenerate
integer i;
initial begin
for (i=0; i<CH_W*CH_CNT/8; i=i+1) begin
data_in[i*8+:8] = i[7:0];
end
for (i=0; i<CH_CNT; i=i+1) begin
@(posedge clk);
ch_sel <= ch_sel + 1;
end
end
wire mismatch;
assign mismatch = ref_data !== data_out;
always @(posedge clk) begin
if (mismatch) begin
failed <= 1'b1;
end
end
endmodule
adi_library/common/tb/ad_pack_tb
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#!/bin/bash
SOURCE="ad_pack_tb.v"
SOURCE+=" ../ad_pack.v"
cd `dirname $0`
source run_tb.sh
adi_library/common/tb/ad_pack_tb.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_pack_tb;
parameter VCD_FILE = "ad_pack_tb.vcd";
parameter I_W = 4; // Width of input channel
parameter O_W = 6; // Width of output channel
parameter UNIT_W = 8;
parameter VECT_W = 1024*8; // Multiple of 8
`include "tb_base.v"
reg [I_W*UNIT_W-1 : 0] idata;
wire [O_W*UNIT_W-1 : 0] odata;
reg ivalid = 'b0;
reg [VECT_W-1:0] input_vector;
reg [VECT_W-1:0] output_vector;
integer i=0;
integer j=0;
ad_pack #(
.I_W(I_W),
.O_W(O_W),
.UNIT_W(UNIT_W)
) DUT (
.clk(clk),
.reset(reset),
.idata(idata),
.ivalid(ivalid),
.odata(odata),
.ovalid(ovalid));
task test(input random_n);
begin
@(posedge clk);
i = 0;
j = 0;
while (i < (VECT_W/(I_W*UNIT_W) + (VECT_W%(I_W*UNIT_W)>0))) begin
@(posedge clk);
if ($urandom % 2 == 0 | random_n) begin
idata <= input_vector[i*(I_W*UNIT_W) +: (I_W*UNIT_W)];
ivalid <= 1'b1;
i = i + 1;
end else begin
idata <= 'bx;
ivalid <= 1'b0;
end
end
@(posedge clk);
idata <= 'bx;
ivalid <= 1'b0;
// Check output vector
repeat (20) @(posedge clk);
for (i=0; i<(VECT_W/(O_W*UNIT_W))*(O_W*UNIT_W)/8; i=i+1) begin
if (input_vector[i*8+:8] !== output_vector[i*8+:8]) begin
failed <= 1'b1;
$display("i=%d Expected=%x Found=%x",i,input_vector[i*8+:8],output_vector[i*8+:8]);
end
end
// Clear output vector
for (i=0; i<VECT_W/8; i=i+1) begin
output_vector[i*8+:8] = 8'bx;
end
end
endtask
initial begin
@(negedge reset);
// Test with incremental data
for (i=0; i<VECT_W/8; i=i+1) begin
input_vector[i*8+:8] = i[7:0];
end
test(1);
do_trigger_reset();
@(negedge reset);
test(0);
do_trigger_reset();
@(negedge reset);
// Test with randomized data
for (i=0; i<VECT_W/8; i=i+1) begin
input_vector[i*8+:8] = $urandom;
end
test(0);
end
always @(posedge clk) begin
if (ovalid) begin
if (j < VECT_W/(O_W*UNIT_W)) begin
output_vector[j*(O_W*UNIT_W) +: (O_W*UNIT_W)] = odata;
j = j + 1;
end
end
end
endmodule
adi_library/common/tb/ad_upack_tb
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#!/bin/bash
SOURCE="ad_upack_tb.v"
SOURCE+=" ../ad_upack.v"
cd `dirname $0`
source run_tb.sh
adi_library/common/tb/ad_upack_tb.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_upack_tb;
parameter VCD_FILE = "ad_upack_tb.vcd";
parameter I_W = 6; // Width of input channel
parameter O_W = 4; // Width of output channel
parameter UNIT_W = 8;
parameter VECT_W = 1024*8; // Multiple of 8
`include "tb_base.v"
reg [I_W*UNIT_W-1 : 0] idata;
wire [O_W*UNIT_W-1 : 0] odata;
reg ivalid = 'b0;
reg [VECT_W-1:0] input_vector;
reg [VECT_W-1:0] output_vector;
integer i=0;
integer j=0;
ad_upack #(
.I_W(I_W),
.O_W(O_W),
.UNIT_W(UNIT_W)
) DUT (
.clk(clk),
.reset(reset),
.idata(idata),
.iready(iready),
.ivalid(ivalid),
.odata(odata),
.ovalid(ovalid));
task test(input no_random);
begin
@(posedge clk);
i = 0;
j = 0;
while (i < VECT_W/(I_W*UNIT_W)) begin
@(posedge clk);
if (iready & (($urandom % 2 == 0) | no_random)) begin
idata <= input_vector[i*(I_W*UNIT_W) +: (I_W*UNIT_W)];
ivalid <= 1'b1;
i = i + 1;
end else begin
idata <= 'bx;
ivalid <= 1'b0;
end
end
@(posedge clk);
idata <= 'bx;
ivalid <= 1'b0;
// Check output vector
repeat (20) @(posedge clk);
for (i=0; i<(((VECT_W/(I_W*UNIT_W))*(I_W*UNIT_W))/(O_W*UNIT_W))*(O_W*UNIT_W)/8; i=i+1) begin
if (input_vector[i*8+:8] !== output_vector[i*8+:8]) begin
failed <= 1'b1;
$display("i=%d Expected=%x Found=%x",i,input_vector[i*8+:8],output_vector[i*8+:8]);
end
end
end
endtask
initial begin
@(negedge reset);
// Test with incremental data
for (i=0; i<VECT_W/8; i=i+1) begin
input_vector[i*8+:8] = i[7:0];
output_vector[i*8+:8] = 'bx;
end
test(1);
do_trigger_reset();
@(negedge reset);
// Test with incremental data random timing
for (i=0; i<VECT_W/8; i=i+1) begin
input_vector[i*8+:8] = i[7:0];
output_vector[i*8+:8] = 'bx;
end
test(0);
do_trigger_reset();
@(negedge reset);
// Test with randomized data random timing
for (i=0; i<VECT_W/8; i=i+1) begin
input_vector[i*8+:8] = $urandom;
end
test(0);
end
always @(posedge clk) begin
if (ovalid) begin
if (j < VECT_W/(O_W*UNIT_W)) begin
output_vector[j*(O_W*UNIT_W) +: (O_W*UNIT_W)] = odata;
j = j + 1;
end
end
end
endmodule
adi_library/common/tb/generate_xml.sh
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#!/bin/bash
##############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: BSD-1-Clause
##############################################################################
# Depending on simulator, search for errors or 'SUCCESS' keyword in specific log
if [[ "$SIMULATOR" == "modelsim" ]]; then
ERRS=`grep -i -e '# Error ' -e '# Fatal' -e '# Failed' -C 10 ${NAME}_modelsim.log`
SUCCESS=`grep 'SUCCESS' ${NAME}_${SIMULATOR}.log`
elif [[ "$SIMULATOR" == "xsim" ]]; then
ERRS=`grep -v ^# ${NAME}_xvlog.log | grep -w -i -e error -e fatal -e fatal_error -e failed -C 10`
ERRS=$ERRS`grep -v ^# ${NAME}_xelab.log | grep -w -i -e error -e fatal -e fatal_error -e failed -C 10`
ERRS=$ERRS`grep -v ^# ${NAME}_xsim.log | grep -w -i -e error -e fatal -e fatal_error -e failed -C 10`
SUCCESS=`grep 'SUCCESS' ${NAME}_xsim.log`
else
echo "XML file is generated only for 'modelsim' and 'xsim' simulators."
echo "Check that variable SIMULATOR is exported and is set to one of those."
fi
# If DURATION is not defined, try to extract it from log file. If it's not found, just use 0
if [[ -z ${DURATION+x} ]]; then
DURATION=$(grep -i 'elapsed' ${NAME}_${SIMULATOR}.log | cut -d ' ' -f '10')
if [[ -z "$DURATION" ]]; then DURATION="0";fi
fi
#Generate xml file
xmlFile="${NAME}.xml"
echo "<?xml version=\"1.0\" encoding=\"utf-8\"?>" > $xmlFile
echo -e "<testsuite>" >> $xmlFile
echo -e "\t<testcase name=\"${NAME}\" time=\"${DURATION}\" classname=\"component_tb\">" >> $xmlFile
if [[ "$ERRS" ]]; then
#replace < with &lt; and > with &gt; in ERRS to not broke created xml
ERRS=$(echo $ERRS | sed 's/</&lt;/g' | sed 's/>/&gt;/g')
echo -e "\t\t<failure>\n\"$ERRS\"\n\t\t</failure>" >> $xmlFile
elif [[ "$SUCCESS" ]]; then
echo -e "\t\t<passed/>" >> $xmlFile
else #There is no error or 'SUCCESS' keyword in log file - set result to 'Skipped'
echo -e "<skipped>" >> $xmlFile
echo -e "\tThe log file does not contain any errors or 'SUCCESS' keyword." >> $xmlFile
echo -e "\tLog file was not created properly or the testbench is not automated" >> $xmlFile
echo -e "</skipped>" >> $xmlFile
fi
echo -e "\t</testcase>" >> $xmlFile
echo "</testsuite>" >> $xmlFile
adi_library/common/tb/run_tb.sh
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##############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: BSD-1-Clause
##############################################################################
export NAME=`basename $0`
# MODE not defined or defined to something else than 'batch'
if [[ -z ${MODE+x} ]] || [[ ! "$MODE" =~ "batch" ]]; then MODE="gui";fi
MODE="-"${MODE##*-} #remove any eventual extra dashes
case "$SIMULATOR" in
modelsim)
# ModelSim flow
vlib work
vlog ${SOURCE} || exit 1
vsim ${NAME} -do "add log /* -r; run -a" $MODE -logfile ${NAME}_modelsim.log || exit 1
;;
xsim)
# XSim flow
xvlog -log ${NAME}_xvlog.log --sourcelibdir . ${SOURCE} || exit 1
xelab -log ${NAME}_xelab.log -debug all ${NAME} || exit 1
if [[ "$MODE" == "-gui" ]]; then
echo "log_wave -r *" > xsim_gui_cmd.tcl
echo "run all" >> xsim_gui_cmd.tcl
xsim work.${NAME} -gui -tclbatch xsim_gui_cmd.tcl -log ${NAME}_xsim.log
else
xsim work.${NAME} -R -log ${NAME}_xsim.log
fi
;;
xcelium)
# Xcelium flow
xmvlog -NOWARN NONPRT ${SOURCE} || exit 1
xmelab -access +rc ${NAME}
xmsim ${NAME} -gui || exit 1
;;
*)
#Icarus flow is the default
mkdir -p run
mkdir -p vcd
iverilog -o run/run_${NAME} -I.. ${SOURCE} $1 || exit 1
cd vcd
../run/run_${NAME}
;;
esac
adi_library/common/tb/tb_base.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
reg clk = 1'b0;
reg [3:0] reset_shift = 4'b1111;
reg trigger_reset = 1'b0;
wire reset;
reg failed = 1'b0;
initial
begin
$dumpfile (VCD_FILE);
$dumpvars;
`ifdef TIMEOUT
#`TIMEOUT
`else
#100000
`endif
if (failed == 1'b0)
$display("SUCCESS");
else
$display("FAILED");
$finish;
end
always @(*) #10 clk <= ~clk;
always @(posedge clk) begin
if (trigger_reset == 1'b1) begin
reset_shift <= 3'b111;
end else begin
reset_shift <= {reset_shift[2:0],1'b0};
end
end
assign reset = reset_shift[3];
task do_trigger_reset;
begin
@(posedge clk) trigger_reset <= 1'b1;
@(posedge clk) trigger_reset <= 1'b0;
end
endtask