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adi_library/data_offload/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := data_offload
GENERIC_DEPS += ../common/ad_axis_inf_rx.v
GENERIC_DEPS += ../common/ad_mem_asym.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += data_offload.v
GENERIC_DEPS += data_offload_fsm.v
GENERIC_DEPS += data_offload_regmap.v
XILINX_DEPS += data_offload_ip.tcl
XILINX_DEPS += data_offload_sv.ttcl
XILINX_DEPS += ../interfaces/if_do_ctrl.xml
XILINX_DEPS += ../interfaces/if_do_ctrl_rtl.xml
XILINX_LIB_DEPS += util_axis_fifo_asym
XILINX_LIB_DEPS += util_cdc
XILINX_INTERFACE_DEPS += interfaces
include ../scripts/library.mk
adi_library/data_offload/README.md
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# Data offload IP core
## Description, general use cases
Data offload module for high-speed converters:
**NOTE**: This IP will always have a storage unit (internal or external to the FPGA) and is
designed to handle high data rates. If your data paths will run in a lower data
rate, and your intention is just to transfer the data to another clock domain or
to adjust the bus width of the data path, you may want to check out the util_axis_fifo or
util_axis_fifo_asym IPs.
The initialization and data transfer looks as follows:
* in case of DAC, the DMA initialize the storage unit, after that the controller
will push the data to the DAC interface in one-shot or cyclic way
* in case of ADC, the DMA request a transfer, the controller will save the data into
the storage unit, after that will push it to the DMA
* BYPASS mode: simple streaming FIFO in case of clock rate or data width differences
between source and sink interfaces (data rate MUST match in order to work); the BYPASS
mode is used when an initially high rate path is downgraded to lower rates.
## Table of content
* [Block diagrams](README.md#block-diagram)
* [Parameters](README.md#parameters)
* [Interfaces](README.md#interfaces)
* [Register map](README.md#register-map)
* [Clock tree](README.md#clock-tree)
* [Data path](README.md#data-path)
* [Control path](README.md#control-path-offload-fsm)
## Generic arhitecture
The main role of our data paths, is to stream data from point A to point B
in a particular system. There are always a SOURCE and a DESTINATION
point, which can be a device (ADC or DAC), a DMA (for system memory) or any other
data processing IP.
In the context of Data Offload IP, we don't need to know who is the source and
who is the destination. Both interface is a AXI4 Stream interface, which can be
supported in both Xilinx's an Intel's architecture, and can be connected to any device
core or DMA.
The storage unit is connected to the Data Offload controller via two FIFO interface.
This way the same controller can be used for various storage solutions. (BRAM,
URAM, external memory etc.)
## Block diagram
![Generic Block Diagram](./docs/generic_bd.svg)
## Parameters
| NAME | TYPE | DEFAULT | DESCRIPTION |
|----------------------|:-----------:|:----------:|:---------------------------:|
|ID | integer | 0 | Instance ID number |
|MEM_TYPE | [ 0:0] | 0 | Define the used storage type: FPGA RAM - 0; external DDR - 1 |
|MEM_SIZE_LOG2 | integer | 10 | Log2 value of storage size, defines the width of transfer length control signals. |
|TX_OR_RXN_PATH | [ 0:0] | 1 | If set TX path enabled, otherwise RX |
|SRC_DATA_WIDTH | integer | 64 | The data width of the source interface |
|DST_DATA_WIDTH | integer | 124 | The data width of the destination interface |
|DST_CYCLIC_EN | [ 0:0] | 0 | Enables CYCLIC mode for destinations like DAC |
|AUTO_BRINGUP | [ 0:0] | 1 | If enabled the IP runs automatically after bootup |
|SYNC_EXT_ADD_INTERNAL_CDC | [ 0:0] | 1 | If enabled the external sync pin is synchronized to the internal clock domain with a CDC. |
|HAS_BYPASS | [ 0:0] | 1 | If set to zero the bypass FIFO is not implemented. |
## Interfaces
### AXI4 Lite Memory Mapped Slave (S_AXI4_LITE)
This interface is used to access the register map.
```verilog
// interface clock -- system clock -- 100 MHz
input s_axi_aclk
// interface resetn -- synchronous reset active low
input s_axi_aresetn
/* write address channel */
// validates the address on the bus
input s_axi_awvalid
// write address
input [15:0] s_axi_awaddr
// protection type -- not used in the core
input [ 2:0] s_axi_awprot
// write ready, indicates that the slave can accept the address
output s_axi_awready
/* write data channel */
// validate the data on the bus
input s_axi_wvalid
// write data
input [31:0] s_axi_wdata
// write strobe, indicates which byte lanes to update
input [ 3:0] s_axi_wstrb
// write ready, indicates that the slave can accept the data
output s_axi_wready
/* write response channel */
// validates the write response of the slave
output s_axi_bvalid
// write response, indicate the status of the transfer
output [ 1:0] s_axi_bresp
// response ready, indicates that the master can accept the data
input s_axi_bready
/* read address channel */
// validates the address on the bus
input s_axi_arvalid
// read address
input [15:0] s_axi_araddr
// protection type -- not used in the core
input [ 2:0] s_axi_arprot
// read ready, indicates that the slave can accept the address
output s_axi_arready
/* read data channel */
// validate the data on the bus
output s_axi_rvalid
// read response, indicate the status of the transfer
output [ 1:0] s_axi_rresp
// read data drivers by the slave
output [31:0] s_axi_rdata
// read ready, indicates that the master can accept the data
input s_axi_rready
```
### Supported data interfaces
**NOTE**: To simplify the design both the source and destination data interface is
an AXI4 streaming interface. A FIFO write (ADC) interface can be treated as AXI4
stream where only the master controls the data rate (s_axis_ready is always asserted),
and a FIFO read (DAC) interface can be treated as an AXI4 stream where only the slave
controls the data rate. (m_axis_valid is always asserted).
#### AXI4 Stream interface (S_AXIS | M_AXIS)
* The AXI Stream Slave (S_AXIS) interface is used to receive AXI stream from
the transmit DMA or ADC device.
* The AXI Stream Master (M_AXIS) interface is used to transmit AXI stream
to receive DMA or DAC device
```verilog
// NOTE: this reference is a master interface
// interface clock -- can be device/core clock or DMA clock
input m_axis_aclk
// interface resetn -- synchronous reset with the system clock
input m_axis_resetn
// indicates that the slave can accept a transfer in the current cycle (in case of an ADC core, this will control the stream)
input m_axis_ready
// indicates that the master is driving a valid transfer
output m_axis_valid
// primary payload
output [DATA_WIDTH-1:0] m_axis_data
// indicates the boundary of a packet
output m_axis_last
// byte qualifier, we need this so we can have different DMA and device data widths
output [(DATA_WIDTH/8)-1:0] m_axis_tkeep
```
**NOTE**: A packet will always be a full buffer. All the data beats going to be
full beats (all the bytes of the bus are valid), except the last one. **axis_last**
and **axis_tkeep** will be used to indicate a partial last beat. This information
should be transferred from the source domain to the sink domain, so we can read
back the data from memory correctly.
#### AXIS source and destination interface to the storage unit
This is blocking (back-pressure) interface for the storage unit,
with similar behavior of main AXIS data interfaces.
### Initialization request interface
Define a simple request interface to initialize the memory:
* The request will comes from the system and will put the data offload FSM
into a standby/ready state.
#### Synchronization modes
* **AUTOMATIC**
* ADC: The IP will start to fill up the buffer with samples as soon as possible.
* DAC: As the DMA will send a valid last, the FSM will start to send the
stored data to the device.
* **HARDWARE**
* ADC and DAC: An external signal will trigger the write or read into or from
the memory.
* **NOTE**: In case of DAC, if the DMA does not sent all the data into the
buffer, before a hardware sync event, the unsent data will be ignored. It's the
user/software responsibility to sync up these events accordingly.
* **SOFTWARE**
* The software write a RW1C register which will trigger the reads or writes
into or from the memory.
## Register Map
| WORD | BYTE | BITS | NAME | TYPE | CLOCK DOMAIN | DESCRIPTION |
|-------:|:--------:|:--------:|:---------------------:|:-----:|:------------:|:-----------------------:|
| 0x0000 | 0x0000 | | `VERSION` | RO | SYS | Version number |
| | | [31:16] | `MAJOR` | | | |
| | | [15: 8] | `MINOR` | | | |
| | | [ 7: 0] | `PATCH` | | | |
| 0x0001 | 0x0004 | | `PERIPHERAL_ID` | RO | SYS | Value of the IP configuration parameter |
| 0x0002 | 0x0008 | | `SCRATCH` | RW | SYS | Scratch register |
| 0x0003 | 0x000C | | `IDENTIFICATION` | RO | SYS | Peripheral identification. Default value: 0x44414F46 - ('D','A','O','F') |
| 0x0004 | 0x0010 | | `SYNTHESIS_CONFIG` | RO | SYS | Core configuration registers |
| | | [13: 8] | `MEM_SIZE_LOG2` | | | Log2 of memory size in bytes |
| | | [ 2: 2] | `HAS_BYPASS` | | | If not set the bypass logic is not implemented. |
| | | [ 1: 1] | `TX_OR_RXN_PATH` | | | RX Path => 0, TX => 1 |
| | | [ 0: 0] | `MEMORY_TYPE` | | | The used storage type (embedded => 0 or external => 1) |
| 0x0007 | 0x001C | | `TRANSFER_LENGTH` | RW | SRC | Transfer length |
| 0x0020 | 0x0080 | | `MEM_PHY_STATE` | RO | DDR | Status bits of the memory controller IP |
| | | [ 5: 5] | `UNDERFLOW` | RW1C | | Indicates that storage could not handle data rate during play. Available when core is in TX mode.|
| | | [ 4: 4] | `OVERFLOW` | RW1C | | Indicates that storage could not handle data rate during capture. Available when core is in RX mode. |
| | | [ 0: 0] | `CALIB_COMPLETE` | | | Indicates that the memory initialization and calibration have completed successfully |
| 0x0021 | 0x0084 | | `RESETN_OFFLOAD` | RW | DST/SRC | Reset all the internal address registers and state machines |
| | | [ 0: 0] | `RESETN` | | | |
| 0x0022 | 0x0088 | | `CONTROL` | RW | DST | A global control register |
| | | [ 1: 1] | `ONESHOT_EN` | | | By default the TX path runs on CYCLIC mode, set this bit to switch it to ONE-SHOT mode |
| | | [ 0: 0] | `OFFLOAD_BYPASS` | | | Bypass the offload storage, the data path consist just of a CDC FIFO |
| 0x0040 | 0x0100 | | `SYNC_TRIGGER` | RW1C | SRC | Synchronization setup for RX and TX path |
| | | [ 0: 0] | `SYNC_TRIGGER` | | | Trigger the data capture |
| 0x0041 | 0x0104 | | `SYNC_CONFIG` | RW | SRC | Synchronization setup |
| | | [ 1: 0] | `SYNC_CONFIG` | | | Auto - '0'; hardware - '1'; software - '2' |
| 0x0080 | 0x0200 | | `FSM_DBG` | RO | | Debug register for the offload FSM |
| | | [11: 8] | `FSM_STATE_READ` | | SRC | The current state of the read-offload state machine |
| | | [ 4: 0] | `FSM_STATE_WRITE` | | DST | The current state of the write-offload state machine |
## Clock tree
In general there are at least two different clock in the data offload module:
* DMA or system clock : on this clock will run all the front end interfaces
* Memory Controller user clock : user interface clock of the DDRx controller (**optional**)
* Device clock : the digital interface clock of the converter
![Clocks](./docs/clocks.svg)
A general frequency relationship of the above clocks are:
```
CLKdma <= CLKddr <= CLKconverter
```
The clock domain crossing should be handled by the [util_axis_fifo](https://github.com/analogdevicesinc/hdl/tree/master/library/util_axis_fifo) module.
* **TODO** : Make sure that we support both AXIS and FIFO
* **TODO** : Add support for asymmetric aspect ratio.
All the back end paths (device side) are time critical. The module must read or
write from or into the storage at the speed of the device.
```
DDR data rate >= Device data rate
DDR data rate >= ADC data rate + DAC data rate
```
## Data path
![Data path](./docs/datapath.svg)
* The data path should be designed to support any kind of difference between
the source, memory and sink data width.
* The data width adjustments will be made by the CDC_FIFO.
* In both path (ADC and DAC) the data stream at the front-end side is packatized,
meaning there is a valid TLAS/TKEEP in the stream. While in the back-end side
the stream is continuous. (no TLAST/TKEEP)
* The DAC path have to have a depacketizer to get rid of the last partial beat
from the stream.
* Because the ADC path already arrive in a packed form, and we always will
fill up the whole storage, we don't need to treat special use-cases.
### Used storage elements
| | ZC706 | ZCU102 | A10SOC |
|:----------------------|:------------------:|:-----------------:|:----------------:|
| FPGA | XC7Z045 FFG900 – 2 | XCZU9EG-2FFVB1156 | 10AS066N3F40E2SG |
| External Memory Type | DDR3 SODIMM | DDR4 | DDR4 HILO |
| External Memory Size | 1 GB | 512 MB | 2 GB |
| Embedded Memory Type | BRAM | BRAM | M20K |
| Embedded Memory Size | 19.1 Mb | 32.1 Mb | 41 Mb |
### Data width manipulation
* data width differences should be treated by the CDC FIFO
* the smallest granularity should be 8 bits. This constraints mainly will generate
additional logic just in the TX path, taking the fact that the data from the ADC
will come packed.
* the gearbox main role is to improve the DDR's bandwidth, strips the padding bits
of each samples, so the raw data could be stored into the memory.
### Xilinx's MIG vs. Intel's EMIF
* Incrementing burst support for 1 to 256 beats, the length of the burst should
be defined by the internal controller
* Concurrent read/write access, the external memory to be shared between an ADC
and DAC
* Dynamic burst length tuning: an FSM reads and writes dummy data until both
ADC's overflow and DAC's underflow lines are de-asserted. Pre-requisites : both
device's interface should be up and running.
* **TODO**: prefetch the next transfer if it's possible, by driving the address channels ahead (e.g. Overlapping read burst in case of AXI4)
* Optional gearbox to congest the samples in order to increase the maximum data rate.
* In general we packing all samples into 16 bits. This can add a significant
overhand to the maximum real data rate on the memory interface. The gearbox main
role is to pack and unpack the device's samples into the required data width. (in general 512 or 1024 bit)
Boards with FPGA side DDR3/4 SODIMMs/HILO: ZC706, ZCU102, A10SOC
| | ZC706 | ZCU102 | A10SOC |
|------------------------------|:---------:|:----------:|:----------:|
| Max data throughputs (MT/s) | 1600 | 2400 | 2133 |
| DDRx reference clocks | 200 MHz | 300 MHz | 133 MHz |
| DDRx Data bus width | 64 | 16 | 64 |
| Memory to FPGA clock ratio | 4:1 | 4:1 | 4:1 |
| UI type & burst length | AXI4-256 | AXI4-256 | Avalon Memory Map |
| UI data width | 512 | 128 | 512 |
### Internal cyclic buffer support for the TX path
![Data path with external storage](./docs/architecture_DDR.svg)
* On the front end side if the TX path, a special buffer will handle the data
width up/down conversions and run in cyclic mode if the length of the data set
is smaller than 4/8 AXI/Avalon burst. This way we can avoid to overload the memory
interface with small bursts.
* On the back end side, because the smallest granularity can be 8 bytes, we need
a dynamic 'depackatizer' or re-aligner, which will filter out the invalid data
bytes from the data stream. (this module will use the tlast and tkeep signal of
the AXI stream interface)
## Control path - Offload FSM
### RX control FSM for internal RAM mode
![RX_control FMS for internal RAM mode](./docs/rx_bram_fsm.svg)
### TX control FSM for internal RAM mode
![TX_control FMS for internal RAM mode](./docs/tx_bram_fsm.svg)
**TODO** FSMs for the external DDR mode
## References
### AMBA AXI
* [AMBA specification](http://infocenter.arm.com/help/topic/com.arm.doc.set.amba/index.html#specs)
* [UG761 AXI Reference Guide](https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf)
### Avalon
* [Avalon Interface Specification](https://www.altera.com/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf)
### Xilinx
* [Device Memory Interface Solutions](https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ds176_7Series_MIS.pdf)
* [Device Memory Interface Solutions User Guide](https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf)
* [Ultrascale Architecutre-Based FPGAs Memory IP (v1.4)](https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf)
* [Xilinx FIFO Generator](https://www.xilinx.com/products/intellectual-property/fifo_generator.html#documentation)
* [7 Series FPGAs Memory Resources](https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf)
* [Ultrascale Memory Resources](https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf)
### Intel
* [Intel Arria 10 Core Fabric and General Purpose I/Os Handbook](https://www.altera.com/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf)
* [Intel Arria 10 External Memory Interface IP User Guide](https://www.altera.com/en_US/pdfs/literature/ug/ug-20115.pdf)
* [Intel Arria 10 External Memory Interface IP Design Example](https://www.altera.com/en_US/pdfs/literature/ug/ug-20118.pdf)
* [Intel SCFIFO and DCFIFO](https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_fifo.pdf)
* [Intel Startix 10 High-Performance Design Handbook](https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/stratix-10/s10_hp_hb.pdf)
* [Intel Stratix 10 Embedded Memory User Guide](https://www.altera.com/en_US/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf)
### Supported FPGA boards
* [ZC706](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html)
* [ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html)
* [A10SOC](https://www.altera.com/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html)
adi_library/data_offload/component.xml
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns / 1ps
module data_offload #(
parameter ID = 0,
parameter MEM_TYPE = 0, // 1'b0 -FPGA RAM; 1'b1 - external memory
parameter MEM_SIZE_LOG2 = 10, // log2 of memory size in bytes
parameter TX_OR_RXN_PATH = 0, // if set IP is used in TX path, other wise in RX path
parameter SRC_DATA_WIDTH = 64,
parameter DST_DATA_WIDTH = 128,
parameter DST_CYCLIC_EN = 1'b0, // 1'b1 - CYCLIC mode enabled; 1'b0 - CYCLIC mode disabled
parameter AUTO_BRINGUP = 1,
parameter SYNC_EXT_ADD_INTERNAL_CDC = 1,
parameter HAS_BYPASS = 1
) (
// AXI4 Slave for configuration
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
// AXI4 stream slave for source stream (TX_DMA or ADC) -- Source interface
input s_axis_aclk,
input s_axis_aresetn,
output s_axis_ready,
input s_axis_valid,
input [SRC_DATA_WIDTH-1:0] s_axis_data,
input s_axis_last,
input [SRC_DATA_WIDTH/8-1:0] s_axis_tkeep,
// AXI4 stream master for destination stream (RX_DMA or DAC) -- Destination
// interface
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output m_axis_valid,
output [DST_DATA_WIDTH-1:0] m_axis_data,
output m_axis_last,
output [DST_DATA_WIDTH/8-1:0] m_axis_tkeep,
// initialization request interface
input init_req,
input sync_ext,
// AXIS - Memory UI to storage
// AXI stream master for source stream to storage (BRAM/URAM/DDR/HBM)
// runs on s_axis_aclk and s_axis_aresetn
input m_storage_axis_ready,
output m_storage_axis_valid,
output [SRC_DATA_WIDTH-1:0] m_storage_axis_data,
output m_storage_axis_last,
output [SRC_DATA_WIDTH/8-1:0] m_storage_axis_tkeep,
// AXI stream slave for destination stream from storage (BRAM/URAM/DDR/HBM)
// runs on m_axis_aclk and m_axis_aresetn
output s_storage_axis_ready,
input s_storage_axis_valid,
input [DST_DATA_WIDTH-1:0] s_storage_axis_data,
input s_storage_axis_last,
input [DST_DATA_WIDTH/8-1:0] s_storage_axis_tkeep,
// Control interface for storage for m_storage_axis interface
output wr_request_enable,
output wr_request_valid,
input wr_request_ready,
output [MEM_SIZE_LOG2-1:0] wr_request_length,
input [MEM_SIZE_LOG2-1:0] wr_response_measured_length,
input wr_response_eot,
input wr_overflow,
// Control interface for storage for s_storage_axis interface
output rd_request_enable,
output rd_request_valid,
input rd_request_ready,
output reg [MEM_SIZE_LOG2-1:0] rd_request_length,
input rd_response_eot,
input rd_underflow,
// Status and monitor
input ddr_calib_done
);
// local parameters -- to make the code more readable
localparam SRC_ADDR_WIDTH_BYPASS = (SRC_DATA_WIDTH > DST_DATA_WIDTH) ? 4 : 4 + $clog2(SRC_DATA_WIDTH/DST_DATA_WIDTH);
localparam DST_ADDR_WIDTH_BYPASS = (SRC_DATA_WIDTH <= DST_DATA_WIDTH) ? 4 + $clog2(DST_DATA_WIDTH/SRC_DATA_WIDTH) : 4;
localparam SRC_BEAT_BYTE = $clog2(SRC_DATA_WIDTH/8);
// NOTE: Clock domain prefixes
// src_* - AXI4 Stream Slave interface's clock domain
// dst_* - AXI4 Stream Master interface's clock domain
// internal signals
wire up_clk;
wire up_rstn;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire up_wack_s;
wire up_rack_s;
wire [31:0] up_rdata_s;
wire src_clk;
wire src_rstn;
wire dst_clk;
wire dst_rstn;
wire src_bypass_s;
wire dst_bypass_s;
wire oneshot_s;
wire [ 1:0] sync_config_s;
wire sync_int_s;
wire valid_bypass_s;
wire [DST_DATA_WIDTH-1:0] data_bypass_s;
wire ready_bypass_s;
wire [ 4:0] src_fsm_status_s;
wire [ 3:0] dst_fsm_status_s;
wire [MEM_SIZE_LOG2-1:0] src_transfer_length_s;
wire [MEM_SIZE_LOG2-1:0] rd_wr_response_measured_length;
wire rd_ml_valid;
wire rd_ready;
wire rd_ml_ready;
wire wr_ready;
assign src_clk = s_axis_aclk;
assign dst_clk = m_axis_aclk;
// internal registers
// Offload FSM and control
data_offload_fsm #(
.TX_OR_RXN_PATH (TX_OR_RXN_PATH),
.SYNC_EXT_ADD_INTERNAL_CDC (SYNC_EXT_ADD_INTERNAL_CDC)
) i_data_offload_fsm (
.up_clk (up_clk),
.wr_clk (src_clk),
.wr_resetn_in (src_rstn),
.wr_request_enable (wr_request_enable),
.wr_request_valid (wr_request_valid),
.wr_request_ready (wr_request_ready),
.wr_response_eot (wr_response_eot),
.wr_ready (wr_ready),
.rd_clk (dst_clk),
.rd_resetn_in (dst_rstn),
.rd_request_enable (rd_request_enable),
.rd_request_valid (rd_request_valid),
.rd_request_ready (rd_request_ready),
.rd_response_eot (rd_response_eot),
.rd_ready (rd_ready),
.rd_valid (s_storage_axis_valid),
.rd_ml_valid (rd_ml_valid),
.rd_ml_ready (rd_ml_ready),
.rd_oneshot (oneshot_s),
.wr_bypass (src_bypass_s),
.init_req (init_req),
.sync_config (sync_config_s),
.sync_external (sync_ext),
.sync_internal (sync_int_s),
.wr_fsm_state_out (src_fsm_status_s),
.rd_fsm_state_out (dst_fsm_status_s));
assign m_axis_valid = dst_bypass_s ? valid_bypass_s : (rd_ready & s_storage_axis_valid);
// For DAC paths set zero as IDLE data on the axis bus, avoid repeating last
// sample.
assign m_axis_data = TX_OR_RXN_PATH[0] & ~m_axis_valid ? {DST_DATA_WIDTH{1'b0}} :
(dst_bypass_s) ? data_bypass_s : s_storage_axis_data;
assign m_axis_last = (dst_bypass_s) ? 1'b0 : s_storage_axis_last;
assign m_axis_tkeep = (dst_bypass_s) ? {DST_DATA_WIDTH/8{1'b1}} : s_storage_axis_tkeep;
assign s_axis_ready = src_bypass_s ? ready_bypass_s : (wr_ready & m_storage_axis_ready);
assign m_storage_axis_valid = s_axis_valid & wr_ready;
assign m_storage_axis_data = s_axis_data;
assign m_storage_axis_last = s_axis_last;
assign m_storage_axis_tkeep = s_axis_tkeep;
assign s_storage_axis_ready = rd_ready & m_axis_ready;
// Bypass module instance -- the same FIFO, just a smaller depth
// NOTE: Generating an overflow is making sense just in BYPASS mode, and
// it's supported just with the FIFO interface
util_axis_fifo_asym #(
.S_DATA_WIDTH (SRC_DATA_WIDTH),
.S_ADDRESS_WIDTH (SRC_ADDR_WIDTH_BYPASS),
.M_DATA_WIDTH (DST_DATA_WIDTH),
.ASYNC_CLK (1)
) i_bypass_fifo (
.m_axis_aclk (m_axis_aclk),
.m_axis_aresetn (dst_rstn),
.m_axis_ready (m_axis_ready),
.m_axis_valid (valid_bypass_s),
.m_axis_data (data_bypass_s),
.m_axis_tlast (),
.m_axis_empty (),
.m_axis_almost_empty (),
.m_axis_tkeep (),
.m_axis_level (),
.s_axis_aclk (s_axis_aclk),
.s_axis_aresetn (src_rstn),
.s_axis_ready (ready_bypass_s),
.s_axis_valid (s_axis_valid & src_bypass_s),
.s_axis_data (s_axis_data),
.s_axis_tlast (),
.s_axis_full (),
.s_axis_almost_full (),
.s_axis_tkeep (),
.s_axis_room ());
// register map
data_offload_regmap #(
.ID (ID),
.MEM_TYPE (MEM_TYPE),
.MEM_SIZE_LOG2 (MEM_SIZE_LOG2),
.TX_OR_RXN_PATH (TX_OR_RXN_PATH),
.AUTO_BRINGUP (AUTO_BRINGUP),
.HAS_BYPASS (HAS_BYPASS)
) i_regmap (
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_rreq (up_rreq_s),
.up_rack (up_rack_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_wreq (up_wreq_s),
.up_wack (up_wack_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.src_clk (s_axis_aclk),
.dst_clk (m_axis_aclk),
.src_sw_resetn (src_rstn),
.dst_sw_resetn (dst_rstn),
.ddr_calib_done (ddr_calib_done),
.src_bypass (src_bypass_s),
.dst_bypass (dst_bypass_s),
.oneshot (oneshot_s),
.sync (sync_int_s),
.sync_config (sync_config_s),
.src_transfer_length (wr_request_length),
.dst_transfer_length (),
.src_fsm_status (src_fsm_status_s),
.dst_fsm_status (dst_fsm_status_s),
.src_overflow (wr_overflow),
.dst_underflow (rd_underflow));
// axi interface wrapper
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
up_axi #(
.AXI_ADDRESS_WIDTH (16)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// Measured length handshake CDC
util_axis_fifo #(
.DATA_WIDTH(MEM_SIZE_LOG2),
.ADDRESS_WIDTH(0),
.ASYNC_CLK(1)
) i_measured_length_cdc (
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn),
.s_axis_valid(wr_response_eot),
.s_axis_ready(),
.s_axis_full(),
.s_axis_data(wr_response_measured_length),
.s_axis_room(),
.s_axis_tkeep(),
.s_axis_tlast(),
.s_axis_almost_full(),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.m_axis_valid(rd_ml_valid),
.m_axis_ready(rd_ml_ready),
.m_axis_data(rd_wr_response_measured_length),
.m_axis_level(),
.m_axis_empty(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_almost_empty());
always @(posedge m_axis_aclk) begin
if (rd_ml_valid & rd_ml_ready)
rd_request_length <= rd_wr_response_measured_length;
end
endmodule
adi_library/data_offload/data_offload.xpr
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/data_offload/data_offload_constr.ttcl
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###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName [ttcl_add $ComponentName "_constr"] :>
<: setFileExtension ".xdc" :>
<: setFileProcessingOrder late :>
<: set mem_type [getBooleanValue "MEM_TYPE"] :>
<: set tx_enable [getBooleanValue "TX_OR_RXN_PATH"] :>
<: set internal_cdc [getBooleanValue "SYNC_EXT_ADD_INTERNAL_CDC"] :>
<: set has_bypass [getBooleanValue "HAS_BYPASS"] :>
## for all synchronization registers from util_cdc modules
set_property ASYNC_REG TRUE \
[get_cells -hier {*cdc_sync_stage1_reg*}] \
[get_cells -hier {*cdc_sync_stage2_reg*}]
## For RX in case of BRAMs
<: if { !$tx_enable } { :>
<: if { $internal_cdc } { :>
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_wr_sync/cdc_sync_stage1_reg[*]/D}]
<: } :>
<: } :>
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/cdc_hold_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_data_reg[*]}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/i_sync_out/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/i_sync_in/cdc_sync_stage1_reg[*]/D}]
## For TX in case of BRAMs
<: if { $tx_enable } { :>
<: if { $internal_cdc } { :>
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_rd_sync/cdc_sync_stage1_reg[*]/D}]
<: } :>
<: } :>
## For external DDRx memory
<: if { $mem_type } { :>
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*i_ddr_calib_done_sync/cdc_sync_stage1_reg[0]/D}]
<: } :>
## Common constraints
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*/i_dst_fsm_status/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*/i_dst_fsm_status/i_sync_out/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*/i_dst_fsm_status/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*/i_dst_fsm_status/i_sync_in/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*/i_dst_fsm_status/cdc_hold_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*/i_dst_fsm_status/out_data_reg[*]}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*/i_src_fsm_status/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*/i_src_fsm_status/i_sync_out/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*/i_src_fsm_status/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*/i_src_fsm_status/i_sync_in/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*/i_src_fsm_status/cdc_hold_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*/i_src_fsm_status/out_data_reg[*]}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*/i_wr_empty_sync/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*/i_wr_empty_sync/i_sync_out/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*/i_wr_empty_sync/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*/i_wr_empty_sync/i_sync_in/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_sync_xfer_control/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_sync_xfer_control/i_sync_out/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_sync_xfer_control/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_sync_xfer_control/i_sync_in/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_sync_xfer_control/cdc_hold_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_sync_xfer_control/out_data_reg[*]}]
<: if { $tx_enable } { :>
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*i_rd_init_req_sync/cdc_sync_stage1_reg[*]/D}]
<: } else { :>
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*i_wr_init_req_sync/cdc_sync_stage1_reg[*]/D}]
<: } :>
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*i_src_xfer_control/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*i_dst_xfer_control/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*i_dst_oneshot_sync/cdc_sync_stage1_reg[0]/D}]
# measured transfer length util_axis_fifo
set src_clk [get_clocks -of_objects [get_ports s_axis_aclk]]
set dest_clk [get_clocks -of_objects [get_ports m_axis_aclk]]
set_max_delay -quiet -datapath_only \
-from $src_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_measured_length_cdc/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
[get_property -min PERIOD $src_clk]
set_max_delay -quiet -datapath_only \
-from $dest_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_measured_length_cdc/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
[get_property -min PERIOD $dest_clk]
set_max_delay -quiet -datapath_only \
-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
-filter {NAME =~ *i_measured_length_cdc* && IS_SEQUENTIAL}] \
-to $dest_clk \
[get_property -min PERIOD $dest_clk]
## Constraints for the bypass module
<: if { $has_bypass } { :>
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*i_waddr_sync_gray/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-to [get_pins -hierarchical * -filter {NAME=~*i_raddr_sync_gray/cdc_sync_stage1_reg[*]/D}]
<: } :>
## Constraints for the overflow/underflow status
<: if { $tx_enable } { :>
set flow_cdc i_rd_underflow_sync
<: } else { :>
set flow_cdc i_wr_overflow_sync
<: } :>
set_false_path \
-from [get_pins -hierarchical * -filter NAME=~*/$flow_cdc/in_toggle_d1_reg/C] \
-to [get_pins -hierarchical * -filter NAME=~*/$flow_cdc/i_sync_out/cdc_sync_stage1_reg[*]/D]
set_false_path \
-from [get_pins -hierarchical * -filter NAME=~*/$flow_cdc/out_toggle_d1_reg/C] \
-to [get_pins -hierarchical * -filter NAME=~*/$flow_cdc/i_sync_in/cdc_sync_stage1_reg[*]/D]
adi_library/data_offload/data_offload_fsm.v
+321
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
/* This module controls the read and write access to the storage unit. It is
* used for both transmit and receive use cases
*/
module data_offload_fsm #(
parameter TX_OR_RXN_PATH = 0,
parameter SYNC_EXT_ADD_INTERNAL_CDC = 1
) (
input up_clk,
// Control interface for storage for m_storage_axis interface
output reg wr_request_enable = 1'b0,
output wr_request_valid,
input wr_request_ready,
input wr_response_eot,
// Control interface for storage for s_storage_axis interface
output reg rd_request_enable = 1'b0,
output rd_request_valid,
input rd_request_ready,
input rd_response_eot,
input rd_ml_valid,
output rd_ml_ready,
// Data path gating
output wr_ready,
output rd_ready,
input rd_valid,
// write control interface
input wr_clk,
input wr_resetn_in,
input wr_bypass,
// read control interface
input rd_clk,
input rd_resetn_in,
input rd_oneshot, // 0 - CYCLIC; 1 - ONE_SHOT;
// Synchronization interface - synchronous to the external DMA clock
input init_req,
input [ 1:0] sync_config,
input sync_external,
input sync_internal,
// FSM debug
output [ 4:0] wr_fsm_state_out,
output [ 3:0] rd_fsm_state_out
);
// FSM states
localparam WR_STATE_IDLE = 5'b00001;
localparam WR_STATE_PRE_WR = 5'b00010;
localparam WR_STATE_SYNC = 5'b00100;
localparam WR_STATE_WR = 5'b01000;
localparam WR_STATE_WAIT_RD = 5'b10000;
localparam WR_BIT_IDLE = 0;
localparam WR_BIT_PRE_WR = 1;
localparam WR_BIT_SYNC = 2;
localparam WR_BIT_WR = 3;
localparam RD_STATE_IDLE = 4'b0001;
localparam RD_STATE_PRE_RD = 4'b0010;
localparam RD_STATE_SYNC = 4'b0100;
localparam RD_STATE_RD = 4'b1000;
localparam RD_BIT_IDLE = 0;
localparam RD_BIT_PRE_RD = 1;
localparam RD_BIT_SYNC = 2;
localparam RD_BIT_RD = 3;
// Synchronization options
localparam AUTOMATIC = 2'b00;
localparam HARDWARE = 2'b01;
localparam SOFTWARE = 2'b10;
// internal registers
reg rd_cyclic_en = 1'b0;
// internal signals
wire wr_sync_external_s;
wire wr_init_req_s;
wire wr_rd_response_eot;
wire rd_sync_external_s;
wire rd_last_eot;
wire rd_init_req_s;
reg [4:0] wr_fsm_state = WR_STATE_IDLE;
reg [4:0] wr_fsm_next_state;
reg [3:0] rd_fsm_state = RD_STATE_IDLE;
reg [3:0] rd_fsm_next_state;
reg [1:0] rd_outstanding = 2'd0;
assign wr_fsm_state_out = wr_fsm_state;
assign rd_fsm_state_out = rd_fsm_state;
always @(*) begin
wr_fsm_next_state = wr_fsm_state;
case (wr_fsm_state)
WR_STATE_IDLE:
if (wr_init_req_s & ~wr_bypass) begin
wr_fsm_next_state = WR_STATE_PRE_WR;
end
WR_STATE_PRE_WR:
if (wr_request_ready) begin
wr_fsm_next_state = TX_OR_RXN_PATH ? WR_STATE_WR : WR_STATE_SYNC;
end
WR_STATE_SYNC:
case (sync_config)
AUTOMATIC:
wr_fsm_next_state = WR_STATE_WR;
HARDWARE:
if (wr_sync_external_s) begin
wr_fsm_next_state = WR_STATE_WR;
end
SOFTWARE:
if (sync_internal) begin
wr_fsm_next_state = WR_STATE_WR;
end
default:
wr_fsm_next_state = WR_STATE_WR;
endcase
WR_STATE_WR:
if (wr_response_eot) begin
wr_fsm_next_state = WR_STATE_WAIT_RD;
end
WR_STATE_WAIT_RD:
if (wr_rd_response_eot) begin
wr_fsm_next_state = WR_STATE_IDLE;
end
default:
wr_fsm_next_state = WR_STATE_IDLE;
endcase
end
always @(posedge wr_clk) begin
if (wr_resetn_in == 1'b0) begin
wr_fsm_state <= WR_STATE_IDLE;
end else begin
wr_fsm_state <= wr_fsm_next_state;
end
end
always @(*) begin
rd_fsm_next_state = rd_fsm_state;
case (rd_fsm_state)
RD_STATE_IDLE:
if (rd_ml_valid) begin
rd_fsm_next_state = RD_STATE_PRE_RD;
end
RD_STATE_PRE_RD:
if (rd_request_ready) begin
rd_fsm_next_state = TX_OR_RXN_PATH ? RD_STATE_SYNC : RD_STATE_RD;
end
RD_STATE_SYNC:
if (rd_valid) // Wait until storage is valid
case (sync_config)
AUTOMATIC:
rd_fsm_next_state = RD_STATE_RD;
HARDWARE:
if (rd_sync_external_s) begin
rd_fsm_next_state = RD_STATE_RD;
end
SOFTWARE:
if (sync_internal) begin
rd_fsm_next_state = RD_STATE_RD;
end
default:
rd_fsm_next_state = RD_STATE_RD;
endcase
RD_STATE_RD:
if (rd_last_eot) begin
rd_fsm_next_state = (rd_cyclic_en == 1'b0) ? RD_STATE_IDLE :
(TX_OR_RXN_PATH & (sync_config != AUTOMATIC)) ? RD_STATE_SYNC :
RD_STATE_RD;
end
default:
rd_fsm_next_state = RD_STATE_IDLE;
endcase
end
always @(posedge rd_clk) begin
if (rd_resetn_in == 1'b0) begin
rd_fsm_state <= RD_STATE_IDLE;
end else begin
rd_fsm_state <= rd_fsm_next_state;
end
end
always @(posedge rd_clk) begin
if (rd_resetn_in == 1'b0)
rd_outstanding <= 2'b0;
else if (rd_request_ready & rd_request_valid & ~rd_response_eot)
rd_outstanding <= rd_outstanding + 2'd1;
else if (~(rd_request_ready & rd_request_valid) & (rd_response_eot & rd_fsm_state[RD_BIT_RD]))
rd_outstanding <= rd_outstanding - 2'd1;
end
assign rd_last_eot = (rd_outstanding == 1) & (rd_response_eot & rd_fsm_state[RD_BIT_RD]) & !(rd_request_ready & rd_request_valid);
always @(posedge rd_clk) begin
if (rd_init_req_s) begin
rd_cyclic_en <= 1'b0;
end else if (rd_fsm_state[RD_BIT_PRE_RD]) begin
rd_cyclic_en <= ~rd_oneshot;
end
end
assign rd_ready = rd_fsm_state[RD_BIT_RD];
assign wr_ready = wr_fsm_state[WR_BIT_WR];
assign wr_request_valid = wr_fsm_state[WR_BIT_PRE_WR];
assign rd_request_valid = rd_fsm_state[RD_BIT_PRE_RD] | rd_cyclic_en;
always @(posedge rd_clk) begin
if (rd_resetn_in == 1'b0 || (~rd_init_req_s & ~TX_OR_RXN_PATH[0]))
rd_request_enable <= 1'b0;
else
rd_request_enable <= 1'b1;
end
always @(posedge wr_clk) begin
if (wr_resetn_in == 1'b0)
wr_request_enable <= 1'b0;
else
wr_request_enable <= 1'b1;
end
assign rd_ml_ready = rd_fsm_state[RD_BIT_IDLE];
// CDC circuits
sync_event #(
.NUM_OF_EVENTS (1),
.ASYNC_CLK (1)
) i_wr_empty_sync (
.in_clk (rd_clk),
.in_event (rd_last_eot && rd_fsm_state[RD_BIT_RD]),
.out_clk (wr_clk),
.out_event (wr_rd_response_eot));
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (TX_OR_RXN_PATH[0])
) i_rd_init_req_sync (
.in_bits (init_req),
.out_clk (rd_clk),
.out_resetn (1'b1),
.out_bits (rd_init_req_s));
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (~TX_OR_RXN_PATH[0])
) i_wr_init_req_sync (
.in_bits (init_req),
.out_clk (wr_clk),
.out_resetn (1'b1),
.out_bits (wr_init_req_s));
// When SYNC_EXT_ADD_INTERNAL_CDC is deasserted, one of these signals will end
// up being synchronized to the "wrong" clock domain. This shouldn't matter
// because the incorrectly synchronized signal is guarded by a synthesis constant.
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC)
) i_sync_wr_sync (
.in_bits ({ sync_external }),
.out_clk (wr_clk),
.out_resetn (1'b1),
.out_bits ({wr_sync_external_s}));
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC)
) i_sync_rd_sync (
.in_bits ({ sync_external }),
.out_clk (rd_clk),
.out_resetn (1'b1),
.out_bits ({ rd_sync_external_s }));
endmodule
adi_library/data_offload/data_offload_ip.tcl
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###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create data_offload
adi_ip_files data_offload [list \
"data_offload_sv.ttcl" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"data_offload_regmap.v" \
"data_offload_fsm.v" \
"data_offload.v" ]
## NOTE: To solve the issue AR# 70646 we need to call the following command
##set_property source_mgmt_mode DisplayOnly [current_project]
adi_ip_properties data_offload
adi_ip_ttcl data_offload "data_offload_constr.ttcl"
adi_ip_sim_ttcl data_offload "data_offload_sv.ttcl"
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo_asym:1.0 \
]
set_property display_name "ADI Data Offload Controller" [ipx::current_core]
set_property description "ADI Data Offload Controller" [ipx::current_core]
## Interface definitions
## destination interfaces (e.g. RX_DMA or DAC core)
adi_add_bus "m_axis" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[ list \
{"m_axis_ready" "TREADY"} \
{"m_axis_valid" "TVALID"} \
{"m_axis_data" "TDATA"} \
{"m_axis_last" "TLAST"} \
{"m_axis_tkeep" "TKEEP"} ]
## source interface (e.g. TX_DMA or ADC core)
adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[ list \
{"s_axis_ready" "TREADY"} \
{"s_axis_valid" "TVALID"} \
{"s_axis_data" "TDATA"} \
{"s_axis_last" "TLAST"} \
{"s_axis_tkeep" "TKEEP"} ]
adi_add_bus "wr_ctrl" "master" \
"analog.com:interface:if_do_ctrl_rtl:1.0" \
"analog.com:interface:if_do_ctrl:1.0" \
[list {"wr_request_enable" "request_enable"} \
{"wr_request_valid" "request_valid"} \
{"wr_request_ready" "request_ready"} \
{"wr_request_length" "request_length"} \
{"wr_response_measured_length" "response_measured_length"} \
{"wr_response_eot" "response_eot"} \
{"wr_overflow" "status_overflow"} \
]
adi_add_bus "rd_ctrl" "master" \
"analog.com:interface:if_do_ctrl_rtl:1.0" \
"analog.com:interface:if_do_ctrl:1.0" \
[list {"rd_request_enable" "request_enable"} \
{"rd_request_valid" "request_valid"} \
{"rd_request_ready" "request_ready"} \
{"rd_request_length" "request_length"} \
{"rd_response_eot" "response_eot"} \
{"rd_underflow" "status_underflow"} \
]
adi_add_bus "s_storage_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"s_storage_axis_ready" "TREADY"} \
{"s_storage_axis_valid" "TVALID"} \
{"s_storage_axis_data" "TDATA"} \
{"s_storage_axis_tkeep" "TKEEP"} \
{"s_storage_axis_last" "TLAST"}]
adi_add_bus "m_storage_axis" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"m_storage_axis_ready" "TREADY"} \
{"m_storage_axis_valid" "TVALID"} \
{"m_storage_axis_data" "TDATA"} \
{"m_storage_axis_tkeep" "TKEEP"} \
{"m_storage_axis_last" "TLAST"}]
adi_add_bus_clock "m_axis_aclk" "s_storage_axis:m_axis" "m_axis_aresetn"
adi_add_bus_clock "s_axis_aclk" "m_storage_axis:s_axis" "s_axis_aresetn"
set cc [ipx::current_core]
set_property -dict [list \
enablement_resolve_type dependent \
driver_value 0 \
enablement_dependency {MEM_TYPE == 1} \
] \
[ipx::get_ports ddr_calib_done -of_objects $cc]
set_property -dict [list \
driver_value 0 \
] \
[ipx::get_ports wr_overflow -of_objects $cc]
set_property -dict [list \
driver_value 0 \
] \
[ipx::get_ports rd_underflow -of_objects $cc]
## Parameter validations
## MEM_TPYE
set_property -dict [list \
"value_format" "long" \
"value_validation_type" "pairs" \
"value_validation_pairs" { \
"Internal memory" "0" \
"External memory" "1" \
} \
] \
[ipx::get_user_parameters MEM_TYPE -of_objects $cc]
set_property -dict [list \
"value_format" "long" \
] \
[ipx::get_hdl_parameters MEM_TYPE -of_objects $cc]
set_property -dict [list \
"value_validation_type" "pairs" \
"value_validation_pairs" { \
"RX path" "0" \
"TX path" "1" \
} \
] \
[ipx::get_user_parameters TX_OR_RXN_PATH -of_objects $cc]
set_property -dict [list \
"value_validation_type" "pairs" \
"value" "10" \
"value_validation_pairs" {\
"1kB" "10" \
"2kB" "11" \
"4kB" "12" \
"8kB" "13" \
"16kB" "14" \
"32kB" "15" \
"64kB" "16" \
"128kB" "17" \
"256kB" "18" \
"512kB" "19" \
"1MB" "20" \
"2MB" "21" \
"4MB" "22" \
"8MB" "23" \
"16MB" "24" \
"32MB" "25" \
"64MB" "26" \
"128MB" "27" \
"256MB" "28" \
"512MB" "29" \
"1GB" "30" \
"2GB" "31" \
"4GB" "32" \
"8GB" "33" \
"16GB" "34" \
} \
] \
[ipx::get_user_parameters MEM_SIZE_LOG2 -of_objects $cc]
## Boolean parameters
foreach {k v} { \
"HAS_BYPASS" "true" \
"DST_CYCLIC_EN" "true" \
"SYNC_EXT_ADD_INTERNAL_CDC" "true" \
} { \
set_property -dict [list \
"value_format" "bool" \
"value_format" "bool" \
"value" $v \
] \
[ipx::get_user_parameters $k -of_objects $cc]
set_property -dict [list \
"value_format" "bool" \
"value_format" "bool" \
"value" $v \
] \
[ipx::get_hdl_parameters $k -of_objects $cc]
}
### Customize IP Layout
## Remove the automatically generated GUI page
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
ipx::save_core [ipx::current_core]
## Create a new GUI page
ipgui::add_page -name {Data Offload} -component [ipx::current_core] -display_name {Data Offload}
set page0 [ipgui::get_pagespec -name "Data Offload" -component $cc]
## General Configurations
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
-parent $page0 -display_name "General Configuration" ]
ipgui::add_param -name "ID" -component $cc -parent $general_group
set_property -dict [list \
"display_name" "Core ID" \
] [ipgui::get_guiparamspec -name "ID" -component $cc]
ipgui::add_param -name "TX_OR_RXN_PATH" -component $cc -parent $general_group
set_property -dict [list \
"widget" "comboBox" \
"display_name" "Data path type" \
] [ipgui::get_guiparamspec -name "TX_OR_RXN_PATH" -component $cc]
ipgui::add_param -name "MEM_TYPE" -component $cc -parent $general_group
set_property -dict [list \
"widget" "comboBox" \
"display_name" "Storage Type" \
] [ipgui::get_guiparamspec -name "MEM_TYPE" -component $cc]
ipgui::add_param -name "MEM_SIZE_LOG2" -component $cc -parent $general_group
set_property -dict [list \
"display_name" "Storage Size" \
"tooltip" "Log2 value of Storage Size in bytes" \
] [ipgui::get_guiparamspec -name "MEM_SIZE_LOG2" -component $cc]
## Transmit and receive endpoints
set source_group [ipgui::add_group -name "Source Endpoint Configuration" -component $cc \
-parent $page0 -display_name "Source Endpoint Configuration" \
-layout "horizontal"]
set destination_group [ipgui::add_group -name "Destination Endpoint Configuration" -component $cc \
-parent $page0 -display_name "Destination Endpoint Configuration" \
-layout "horizontal"]
ipgui::add_param -name "SRC_DATA_WIDTH" -component $cc -parent $source_group
set_property -dict [list \
"display_name" "Source Interface data width" \
] [ipgui::get_guiparamspec -name "SRC_DATA_WIDTH" -component $cc]
ipgui::add_param -name "DST_DATA_WIDTH" -component $cc -parent $destination_group
set_property -dict [list \
"display_name" "Destination Interface data width" \
] [ipgui::get_guiparamspec -name "DST_DATA_WIDTH" -component $cc]
## Other features
set features_group [ipgui::add_group -name "Features" -component $cc \
-parent $page0 -display_name "Features" ]
ipgui::add_param -name "HAS_BYPASS" -component $cc -parent $features_group
set_property -dict [list \
"display_name" "Internal Bypass Data Path Enabled" \
] [ipgui::get_guiparamspec -name "HAS_BYPASS" -component $cc]
ipgui::add_param -name "DST_CYCLIC_EN" -component $cc -parent $features_group
set_property -dict [list \
"display_name" "Destination Cyclic Mode Enabled" \
] [ipgui::get_guiparamspec -name "DST_CYCLIC_EN" -component $cc]
set_property enablement_tcl_expr {$TX_OR_RXN_PATH == 1} [ipx::get_user_parameters DST_CYCLIC_EN -of_objects $cc]
ipgui::add_param -name "SYNC_EXT_ADD_INTERNAL_CDC" -component $cc -parent $features_group
set_property -dict [list \
"display_name" "Generate CDC Circuit for sync_ext" \
] [ipgui::get_guiparamspec -name "SYNC_EXT_ADD_INTERNAL_CDC" -component $cc]
## Create and save the XGUI file
ipx::create_xgui_files $cc
ipx::save_core [ipx::current_core]
adi_library/data_offload/data_offload_regmap.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module data_offload_regmap #(
parameter ID = 0,
parameter [ 0:0] MEM_TYPE = 1'b0,
parameter MEM_SIZE_LOG2 = 10,
parameter TX_OR_RXN_PATH = 0,
parameter AUTO_BRINGUP = 0,
parameter HAS_BYPASS = 1
) (
// microprocessor interface
input up_clk,
input up_rstn,
input up_rreq,
output reg up_rack,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
input up_wreq,
output reg up_wack,
input [13:0] up_waddr,
input [31:0] up_wdata,
// source clock domain
input src_clk,
// destination clock domain
input dst_clk,
// resets for all clock domains
output reg src_sw_resetn,
output reg dst_sw_resetn,
// status bit from the memory controller
input ddr_calib_done,
// bypass control
output src_bypass,
output dst_bypass,
output oneshot,
// synchronization
output sync,
output [ 1:0] sync_config,
output [MEM_SIZE_LOG2-1:0] src_transfer_length,
output [MEM_SIZE_LOG2-1:0] dst_transfer_length,
// FSM control and status
input [ 4:0] src_fsm_status,
input [ 3:0] dst_fsm_status,
input src_overflow,
input dst_underflow
);
// local parameters
localparam [31:0] CORE_VERSION = 32'h00010061; // 1.00.a
localparam [31:0] CORE_MAGIC = 32'h44414F46; // DAOF
localparam [33:0] MEM_SIZE = 1 << MEM_SIZE_LOG2;
// internal registers
reg [31:0] up_scratch = 'd0;
reg up_sw_resetn = 'd0;
reg up_bypass = 'd0;
reg up_sync = 'd0;
reg [ 1:0] up_sync_config = 'd0;
reg up_oneshot = 1'b0;
reg [MEM_SIZE_LOG2-1:0] up_transfer_length = 'd0;
reg up_src_overflow = 1'b0;
reg up_dst_underflow = 1'b0;
//internal signals
wire up_ddr_calib_done_s;
wire [ 4:0] up_wr_fsm_status_s;
wire [ 3:0] up_rd_fsm_status_s;
wire src_sw_resetn_s;
wire dst_sw_resetn_s;
wire [33:0] src_transfer_length_s;
wire up_src_overflow_set_s;
wire up_dst_underflow_set_s;
// write interface
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_wack <= up_wreq;
up_scratch <= 'd0;
up_sw_resetn <= AUTO_BRINGUP;
up_oneshot <= ~TX_OR_RXN_PATH;
up_bypass <= 'd0;
up_sync <= 'd0;
up_sync_config <= 'd0;
up_transfer_length <= {MEM_SIZE_LOG2{1'b1}};
up_src_overflow <= 1'b0;
up_dst_underflow <= 1'b0;
end else begin
up_wack <= up_wreq;
/* Scratch Register */
if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h02)) begin
up_scratch <= up_wdata;
end
/* Transfer Length Register */
if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h07)) begin
up_transfer_length <= {up_wdata[MEM_SIZE_LOG2-7:0], {6{1'b1}}};
end
/* Memory interface status register */
if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h20) && up_wdata[4]) begin
up_src_overflow <= 1'b0;
end else if (up_src_overflow_set_s) begin
up_src_overflow <= 1'b1;
end
if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h20) && up_wdata[5]) begin
up_dst_underflow <= 1'b0;
end else if (up_dst_underflow_set_s) begin
up_dst_underflow <= 1'b1;
end
/* Reset Offload Register */
if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h21)) begin
up_sw_resetn <= up_wdata[0];
end
/* Control Register */
if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h22)) begin
up_oneshot <= up_wdata[1];
up_bypass <= up_wdata[0] & HAS_BYPASS;
end
/* SYNC Offload Register - self cleared, one pulse signal */
if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h40)) begin
up_sync <= up_wdata[0];
end else begin
up_sync <= 1'b0;
end
/* SYNC RX Configuration Register */
if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h41)) begin
up_sync_config <= up_wdata[1:0];
end
end
end
//read interface for common registers
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rack <= 1'b0;
up_rdata <= 32'b0;
end else begin
up_rack <= up_rreq;
case(up_raddr)
/* Version Register */
14'h000: up_rdata <= {
CORE_VERSION[31:16], /* MAJOR */
CORE_VERSION[15: 8], /* MINOR */
CORE_VERSION[ 7: 0] /* PATCH */
};
/* Peripheral ID Register */
14'h001: up_rdata <= ID;
/* Peripheral ID Register */
14'h002: up_rdata <= up_scratch;
/* Identification Register */
14'h003: up_rdata <= CORE_MAGIC;
/* Configuration Register */
14'h004: up_rdata <= {
29'b0,
/* 2 */ HAS_BYPASS[0],
/* 1 */ TX_OR_RXN_PATH[0],
/* 0 */ MEM_TYPE[0]
};
/* Configuration Storage Unit Size LSB Register */
14'h005: up_rdata <= MEM_SIZE[31:0];
/* Configuration Storage Unit Size MSB Register */
14'h006: up_rdata <= {
30'b0,
/* 00-01 */ MEM_SIZE[33:32]
};
/* Configuration data transfer length */
14'h007: up_rdata <= {
{32-(MEM_SIZE_LOG2-6){1'b0}},
up_transfer_length[MEM_SIZE_LOG2-1:6]
};
/* 0x08-0x1f reserved for future use */
/* Memory Physical Interface Status */
14'h020: up_rdata <= {
26'b0,
up_dst_underflow,
up_src_overflow,
3'b0,
/* 0 */ up_ddr_calib_done_s
};
/* Reset Offload Register */
14'h021: up_rdata <= {
31'b0,
/* 0 */ up_sw_resetn
};
/* Control Register */
14'h022: up_rdata <= {
30'b0,
/* 1 */ up_oneshot,
/* 0 */ up_bypass
};
/* 0x24-0x3f reserved for future use */
/* SYNC Offload Register */
14'h040: up_rdata <= {
31'b0,
/* 0 */ up_sync
};
/* SYNC RX Configuration Register */
14'h041: up_rdata <= {
30'b0,
/* 00-01 */ up_sync_config
};
/* 0x42-0x7f reserved for future use */
/* FMS Debug Register */
14'h080: up_rdata <= {
20'b0,
/* 11-08 */ up_rd_fsm_status_s,
3'b0,
/* 04-00 */ up_wr_fsm_status_s
};
default: up_rdata <= 32'h00000000;
endcase
end
end /* read interface */
// Clock Domain Crossing Logic for reset, control and status signals
sync_data #(
.NUM_OF_BITS (4),
.ASYNC_CLK (1)
) i_dst_fsm_status (
.in_clk (dst_clk),
.in_data (dst_fsm_status),
.out_clk (up_clk),
.out_data (up_rd_fsm_status_s));
sync_data #(
.NUM_OF_BITS (5),
.ASYNC_CLK (1)
) i_src_fsm_status (
.in_clk (src_clk),
.in_data (src_fsm_status),
.out_clk (up_clk),
.out_data (up_wr_fsm_status_s));
generate
if (TX_OR_RXN_PATH) begin : sync_tx_path
sync_data #(
.NUM_OF_BITS (3),
.ASYNC_CLK (1)
) i_sync_xfer_control (
.in_clk (up_clk),
.in_data ({up_sync_config,
up_sync}),
.out_clk (dst_clk),
.out_data ({sync_config,
sync}));
end else begin : sync_rx_path
sync_data #(
.NUM_OF_BITS (3),
.ASYNC_CLK (1)
) i_sync_xfer_control (
.in_clk (up_clk),
.in_data ({up_sync_config,
up_sync}),
.out_clk (src_clk),
.out_data ({sync_config,
sync}));
end
endgenerate
sync_bits #(
.NUM_OF_BITS (2),
.ASYNC_CLK (1)
) i_src_xfer_control (
.in_bits ({ up_sw_resetn, up_bypass }),
.out_clk (src_clk),
.out_resetn (1'b1),
.out_bits ({ src_sw_resetn_s, src_bypass }));
sync_bits #(
.NUM_OF_BITS (2),
.ASYNC_CLK (1)
) i_dst_xfer_control (
.in_bits ({ up_sw_resetn, up_bypass }),
.out_clk (dst_clk),
.out_resetn (1'b1),
.out_bits ({ dst_sw_resetn_s, dst_bypass }));
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (1)
) i_ddr_calib_done_sync (
.in_bits (ddr_calib_done),
.out_clk (up_clk),
.out_resetn (1'b1),
.out_bits (up_ddr_calib_done_s));
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (1)
) i_dst_oneshot_sync (
.in_bits (up_oneshot),
.out_clk (dst_clk),
.out_resetn (1'b1),
.out_bits (oneshot));
sync_data #(
.NUM_OF_BITS (MEM_SIZE_LOG2),
.ASYNC_CLK (1)
) i_sync_src_transfer_length (
.in_clk (up_clk),
.in_data (up_transfer_length),
.out_clk (src_clk),
.out_data (src_transfer_length));
sync_data #(
.NUM_OF_BITS (MEM_SIZE_LOG2),
.ASYNC_CLK (1)
) i_sync_dst_transfer_length (
.in_clk (up_clk),
.in_data (up_transfer_length),
.out_clk (dst_clk),
.out_data (dst_transfer_length));
always @(posedge src_clk) begin
src_sw_resetn <= src_sw_resetn_s;
end
always @(posedge dst_clk) begin
dst_sw_resetn <= dst_sw_resetn_s;
end
generate if (TX_OR_RXN_PATH == 0) begin
sync_event #(
.NUM_OF_EVENTS (1),
.ASYNC_CLK (1)
) i_wr_overflow_sync (
.in_clk (src_clk),
.in_event (src_overflow),
.out_clk (up_clk),
.out_event (up_src_overflow_set_s));
assign up_dst_underflow_set_s = 1'b0;
end else begin
sync_event #(
.NUM_OF_EVENTS (1),
.ASYNC_CLK (1)
) i_rd_underflow_sync (
.in_clk (dst_clk),
.in_event (dst_underflow),
.out_clk (up_clk),
.out_event (up_dst_underflow_set_s));
assign up_src_overflow_set_s = 1'b0;
end
endgenerate
endmodule
adi_library/data_offload/data_offload_sv.ttcl
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###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
# SPDX short identifier: ADIBSD
###############################################################################
<: :>
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./sim/" :>
<: setFileName ${ComponentName}_pkg :>
<: setFileExtension ".sv" :>
<: set id [get_property MODELPARAM_VALUE.ID] :>
<: set mem_type [get_property MODELPARAM_VALUE.MEM_TYPE] :>
<: set mem_size_log2 [get_property MODELPARAM_VALUE.MEM_SIZE_LOG2] :>
<: set tx_or_rxn_path [get_property MODELPARAM_VALUE.TX_OR_RXN_PATH] :>
<: set src_data_width [get_property MODELPARAM_VALUE.src_data_width] :>
<: set dst_data_width [get_property MODELPARAM_VALUE.dst_data_width] :>
<: set dst_cyclic_en [get_property MODELPARAM_VALUE.dst_cyclic_en] :>
// boolean to intiger
<: proc b2i {b} { if {$b==true} {return 1} else {return 0}} :>
// C hex to verilog hex
<: proc h2vh {a} { return [string replace $a 0 1 "'h"]} :>
///////////////////////////////////////////////////////////////////////////
//NOTE: This file has been automatically generated by Vivado.
///////////////////////////////////////////////////////////////////////////
package <=: ComponentName :>_pkg;
///////////////////////////////////////////////////////////////////////////
// These parameters are named after the component for use in your verification
// environment.
///////////////////////////////////////////////////////////////////////////
parameter <=: ComponentName :>_ID = <=: $id :>;
parameter <=: ComponentName :>_MEM_TYPE = <=: $mem_type :>;
parameter <=: ComponentName :>_MEM_SIZE_LOG2 = <=: $mem_size_log2 :>;
parameter <=: ComponentName :>_TX_OR_RXN_PATH = <=: b2i $tx_or_rxn_path :>;
parameter <=: ComponentName :>_SRC_DATA_WIDTH = <=: b2i $src_data_width :>;
parameter <=: ComponentName :>_DST_DATA_WIDTH = <=: b2i $dst_data_width :>;
parameter <=: ComponentName :>_DST_CYCLIC_EN = <=: b2i $dst_cyclic_en :>;
//////////////////////////////////////////////////////////////////////////
endpackage : <=: ComponentName :>_pkg
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<svg
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adi_library/data_offload/gui/data_offload_v1_0.gtcl
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# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_DST_CYCLIC_EN_ENABLEMENT {TX_OR_RXN_PATH } {expr $TX_OR_RXN_PATH == 1}
adi_library/data_offload/xgui/data_offload_v1_0.tcl
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# Loading additional proc with user specified bodies to compute parameter values.
source [file join [file dirname [file dirname [info script]]] gui/data_offload_v1_0.gtcl]
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Data_Offload [ipgui::add_page $IPINST -name "Data Offload"]
#Adding Group
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Data_Offload}]
ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}
ipgui::add_param $IPINST -name "TX_OR_RXN_PATH" -parent ${General_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "MEM_TYPE" -parent ${General_Configuration} -widget comboBox
set MEM_SIZE_LOG2 [ipgui::add_param $IPINST -name "MEM_SIZE_LOG2" -parent ${General_Configuration} -widget comboBox]
set_property tooltip {Log2 value of Storage Size in bytes} ${MEM_SIZE_LOG2}
#Adding Group
set Source_Endpoint_Configuration [ipgui::add_group $IPINST -name "Source Endpoint Configuration" -parent ${Data_Offload} -layout horizontal]
ipgui::add_param $IPINST -name "SRC_DATA_WIDTH" -parent ${Source_Endpoint_Configuration}
#Adding Group
set Destination_Endpoint_Configuration [ipgui::add_group $IPINST -name "Destination Endpoint Configuration" -parent ${Data_Offload} -layout horizontal]
ipgui::add_param $IPINST -name "DST_DATA_WIDTH" -parent ${Destination_Endpoint_Configuration}
#Adding Group
set Features [ipgui::add_group $IPINST -name "Features" -parent ${Data_Offload}]
ipgui::add_param $IPINST -name "HAS_BYPASS" -parent ${Features}
ipgui::add_param $IPINST -name "DST_CYCLIC_EN" -parent ${Features}
ipgui::add_param $IPINST -name "SYNC_EXT_ADD_INTERNAL_CDC" -parent ${Features}
}
proc update_PARAM_VALUE.DST_CYCLIC_EN { PARAM_VALUE.DST_CYCLIC_EN PARAM_VALUE.TX_OR_RXN_PATH } {
# Procedure called to update DST_CYCLIC_EN when any of the dependent parameters in the arguments change
set DST_CYCLIC_EN ${PARAM_VALUE.DST_CYCLIC_EN}
set TX_OR_RXN_PATH ${PARAM_VALUE.TX_OR_RXN_PATH}
set values(TX_OR_RXN_PATH) [get_property value $TX_OR_RXN_PATH]
if { [gen_USERPARAMETER_DST_CYCLIC_EN_ENABLEMENT $values(TX_OR_RXN_PATH)] } {
set_property enabled true $DST_CYCLIC_EN
} else {
set_property enabled false $DST_CYCLIC_EN
}
}
proc validate_PARAM_VALUE.DST_CYCLIC_EN { PARAM_VALUE.DST_CYCLIC_EN } {
# Procedure called to validate DST_CYCLIC_EN
return true
}
proc update_PARAM_VALUE.AUTO_BRINGUP { PARAM_VALUE.AUTO_BRINGUP } {
# Procedure called to update AUTO_BRINGUP when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.AUTO_BRINGUP { PARAM_VALUE.AUTO_BRINGUP } {
# Procedure called to validate AUTO_BRINGUP
return true
}
proc update_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } {
# Procedure called to update DST_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } {
# Procedure called to validate DST_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.HAS_BYPASS { PARAM_VALUE.HAS_BYPASS } {
# Procedure called to update HAS_BYPASS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.HAS_BYPASS { PARAM_VALUE.HAS_BYPASS } {
# Procedure called to validate HAS_BYPASS
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.MEM_SIZE_LOG2 { PARAM_VALUE.MEM_SIZE_LOG2 } {
# Procedure called to update MEM_SIZE_LOG2 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.MEM_SIZE_LOG2 { PARAM_VALUE.MEM_SIZE_LOG2 } {
# Procedure called to validate MEM_SIZE_LOG2
return true
}
proc update_PARAM_VALUE.MEM_TYPE { PARAM_VALUE.MEM_TYPE } {
# Procedure called to update MEM_TYPE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.MEM_TYPE { PARAM_VALUE.MEM_TYPE } {
# Procedure called to validate MEM_TYPE
return true
}
proc update_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } {
# Procedure called to update SRC_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } {
# Procedure called to validate SRC_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC { PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC } {
# Procedure called to update SYNC_EXT_ADD_INTERNAL_CDC when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC { PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC } {
# Procedure called to validate SYNC_EXT_ADD_INTERNAL_CDC
return true
}
proc update_PARAM_VALUE.TX_OR_RXN_PATH { PARAM_VALUE.TX_OR_RXN_PATH } {
# Procedure called to update TX_OR_RXN_PATH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TX_OR_RXN_PATH { PARAM_VALUE.TX_OR_RXN_PATH } {
# Procedure called to validate TX_OR_RXN_PATH
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.MEM_TYPE { MODELPARAM_VALUE.MEM_TYPE PARAM_VALUE.MEM_TYPE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.MEM_TYPE}] ${MODELPARAM_VALUE.MEM_TYPE}
}
proc update_MODELPARAM_VALUE.MEM_SIZE_LOG2 { MODELPARAM_VALUE.MEM_SIZE_LOG2 PARAM_VALUE.MEM_SIZE_LOG2 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.MEM_SIZE_LOG2}] ${MODELPARAM_VALUE.MEM_SIZE_LOG2}
}
proc update_MODELPARAM_VALUE.TX_OR_RXN_PATH { MODELPARAM_VALUE.TX_OR_RXN_PATH PARAM_VALUE.TX_OR_RXN_PATH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_OR_RXN_PATH}] ${MODELPARAM_VALUE.TX_OR_RXN_PATH}
}
proc update_MODELPARAM_VALUE.SRC_DATA_WIDTH { MODELPARAM_VALUE.SRC_DATA_WIDTH PARAM_VALUE.SRC_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SRC_DATA_WIDTH}] ${MODELPARAM_VALUE.SRC_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.DST_DATA_WIDTH { MODELPARAM_VALUE.DST_DATA_WIDTH PARAM_VALUE.DST_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DST_DATA_WIDTH}] ${MODELPARAM_VALUE.DST_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.DST_CYCLIC_EN { MODELPARAM_VALUE.DST_CYCLIC_EN PARAM_VALUE.DST_CYCLIC_EN } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DST_CYCLIC_EN}] ${MODELPARAM_VALUE.DST_CYCLIC_EN}
}
proc update_MODELPARAM_VALUE.AUTO_BRINGUP { MODELPARAM_VALUE.AUTO_BRINGUP PARAM_VALUE.AUTO_BRINGUP } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.AUTO_BRINGUP}] ${MODELPARAM_VALUE.AUTO_BRINGUP}
}
proc update_MODELPARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC { MODELPARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC}] ${MODELPARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC}
}
proc update_MODELPARAM_VALUE.HAS_BYPASS { MODELPARAM_VALUE.HAS_BYPASS PARAM_VALUE.HAS_BYPASS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.HAS_BYPASS}] ${MODELPARAM_VALUE.HAS_BYPASS}
}