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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/intel/avl_dacfifo/.timestamp_intel
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adi_library/intel/avl_dacfifo/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := avl_dacfifo
INTEL_DEPS += ../../common/ad_b2g.v
INTEL_DEPS += ../../common/ad_g2b.v
INTEL_DEPS += ../../common/ad_mem.v
INTEL_DEPS += ../../common/util_delay.v
INTEL_DEPS += avl_dacfifo.v
INTEL_DEPS += avl_dacfifo_constr.sdc
INTEL_DEPS += avl_dacfifo_hw.tcl
INTEL_DEPS += avl_dacfifo_rd.v
INTEL_DEPS += avl_dacfifo_wr.v
INTEL_DEPS += util_dacfifo_bypass.v
include ../../scripts/library.mk
adi_library/intel/avl_dacfifo/avl_dacfifo.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module avl_dacfifo #(
parameter DAC_DATA_WIDTH = 64,
parameter DAC_MEM_ADDRESS_WIDTH = 8,
parameter DMA_DATA_WIDTH = 64,
parameter DMA_MEM_ADDRESS_WIDTH = 10,
parameter AVL_DATA_WIDTH = 512,
parameter AVL_ADDRESS_WIDTH = 25,
parameter AVL_BURST_LENGTH = 127,
parameter AVL_BASE_ADDRESS = 32'h00000000,
parameter AVL_ADDRESS_LIMIT = 32'h1fffffff
) (
// dma interface
input dma_clk,
input dma_rst,
input dma_valid,
input [(DMA_DATA_WIDTH-1):0] dma_data,
output reg dma_ready,
input dma_xfer_req,
input dma_xfer_last,
// dac interface
input dac_clk,
input dac_rst,
input dac_valid,
output reg [(DAC_DATA_WIDTH-1):0] dac_data,
output reg dac_dunf,
output reg dac_xfer_out,
input bypass,
// avalon interface
input avl_clk,
input avl_reset,
output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address,
output reg [ 6:0] avl_burstcount,
output reg [ 63:0] avl_byteenable,
output avl_read,
input [(AVL_DATA_WIDTH-1):0] avl_readdata,
input avl_readdata_valid,
input avl_ready,
output avl_write,
output [(AVL_DATA_WIDTH-1):0] avl_writedata
);
localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0;
// internal register
reg dma_bypass_m1 = 1'b0;
reg dma_bypass = 1'b0;
reg dac_bypass_m1 = 1'b0;
reg dac_bypass = 1'b0;
reg dac_xfer_out_m1 = 1'b0;
reg dac_xfer_out_bypass = 1'b0;
// internal signals
wire dma_ready_wr_s;
wire dma_ready_bypass_s;
wire avl_read_s;
wire avl_write_s;
wire [ 24:0] avl_wr_address_s;
wire [ 24:0] avl_rd_address_s;
wire [ 24:0] avl_last_address_s;
wire [ 6:0] avl_last_burstcount_s;
wire [ 7:0] dma_last_beats_s;
wire [ 6:0] avl_wr_burstcount_s;
wire [ 6:0] avl_rd_burstcount_s;
wire [ 63:0] avl_wr_byteenable_s;
wire [ 63:0] avl_rd_byteenable_s;
wire avl_xfer_wren_s;
wire avl_xfer_out_s;
wire avl_xfer_in_s;
wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s;
wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s;
wire dac_xfer_fifo_out_s;
wire dac_dunf_fifo_s;
wire dac_dunf_bypass_s;
avl_dacfifo_wr #(
.AVL_DATA_WIDTH (AVL_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.AVL_DDR_BASE_ADDRESS (AVL_BASE_ADDRESS),
.DMA_MEM_ADDRESS_WIDTH(DMA_MEM_ADDRESS_WIDTH),
.AVL_BURST_LENGTH (AVL_BURST_LENGTH)
) i_wr (
.dma_clk (dma_clk),
.dma_data (dma_data),
.dma_ready (dma_ready),
.dma_ready_out (dma_ready_wr_s),
.dma_valid (dma_valid),
.dma_xfer_req (dma_xfer_req),
.dma_xfer_last (dma_xfer_last),
.dma_last_beats (dma_last_beats_s),
.avl_last_address (avl_last_address_s),
.avl_last_burstcount (avl_last_burstcount_s),
.avl_clk (avl_clk),
.avl_reset (avl_reset),
.avl_address (avl_wr_address_s),
.avl_burstcount (avl_wr_burstcount_s),
.avl_byteenable (avl_wr_byteenable_s),
.avl_waitrequest (~avl_ready),
.avl_write (avl_write),
.avl_data (avl_writedata),
.avl_xfer_req_out (avl_xfer_out_s),
.avl_xfer_req_in (avl_xfer_in_s));
avl_dacfifo_rd #(
.AVL_DATA_WIDTH(AVL_DATA_WIDTH),
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
.AVL_DDR_BASE_ADDRESS(AVL_BASE_ADDRESS),
.AVL_DDR_ADDRESS_LIMIT(AVL_ADDRESS_LIMIT),
.DAC_MEM_ADDRESS_WIDTH(DAC_MEM_ADDRESS_WIDTH),
.AVL_BURST_LENGTH (AVL_BURST_LENGTH)
) i_rd (
.dac_clk(dac_clk),
.dac_reset(dac_rst),
.dac_valid(dac_valid),
.dac_data(dac_data_fifo_s),
.dac_xfer_req(dac_xfer_fifo_out_s),
.dac_dunf(dac_dunf_fifo_s),
.avl_clk(avl_clk),
.avl_reset(avl_reset),
.avl_address(avl_rd_address_s),
.avl_burstcount(avl_rd_burstcount_s),
.avl_byteenable(avl_rd_byteenable_s),
.avl_waitrequest(~avl_ready),
.avl_readdatavalid(avl_readdata_valid),
.avl_read(avl_read),
.avl_data(avl_readdata),
.avl_last_address(avl_last_address_s),
.avl_last_burstcount(avl_last_burstcount_s),
.dma_last_beats(dma_last_beats_s),
.avl_xfer_req_in(avl_xfer_out_s),
.avl_xfer_req_out(avl_xfer_in_s));
// avalon address multiplexer and output registers
assign avl_xfer_wren_s = ~avl_xfer_in_s;
always @(posedge avl_clk) begin
if (avl_reset == 1'b1) begin
avl_address <= 0;
avl_burstcount <= 0;
avl_byteenable <= 0;
end else if (avl_ready) begin
avl_address <= (avl_xfer_wren_s == 1'b1) ? avl_wr_address_s : avl_rd_address_s;
avl_burstcount <= (avl_xfer_wren_s == 1'b1) ? avl_wr_burstcount_s : avl_rd_burstcount_s;
avl_byteenable <= (avl_xfer_wren_s == 1'b1) ? avl_wr_byteenable_s : avl_rd_byteenable_s;
end
end
// bypass logic -- supported if DAC_DATA_WIDTH == DMA_DATA_WIDTH
generate
if (FIFO_BYPASS) begin
util_dacfifo_bypass #(
.DAC_DATA_WIDTH (DAC_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH)
) i_dacfifo_bypass (
.dma_clk(dma_clk),
.dma_data(dma_data),
.dma_ready(dma_ready),
.dma_ready_out(dma_ready_bypass_s),
.dma_valid(dma_valid),
.dma_xfer_req(dma_xfer_req),
.dac_clk(dac_clk),
.dac_rst(dac_rst),
.dac_valid(dac_valid),
.dac_data(dac_data_bypass_s),
.dac_dunf(dac_dunf_bypass_s));
always @(posedge dma_clk) begin
dma_bypass_m1 <= bypass;
dma_bypass <= dma_bypass_m1;
end
always @(posedge dac_clk) begin
dac_bypass_m1 <= bypass;
dac_bypass <= dac_bypass_m1;
dac_xfer_out_m1 <= dma_xfer_req;
dac_xfer_out_bypass <= dac_xfer_out_m1;
end
// mux for the dma_ready
always @(posedge dma_clk) begin
dma_ready <= (dma_bypass) ? dma_ready_bypass_s : dma_ready_wr_s;
end
// mux for dac data
always @(posedge dac_clk) begin
if (dac_valid) begin
dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s;
end
dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s;
dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s;
end
end else begin /* if (~FIFO_BYPASS) */
always @(posedge dma_clk) begin
dma_ready <= dma_ready_wr_s;
end
always @(posedge dac_clk) begin
if (dac_valid) begin
dac_data <= dac_data_fifo_s;
end
dac_xfer_out <= dac_xfer_fifo_out_s;
dac_dunf <= dac_dunf_fifo_s;
end
end
endgenerate
endmodule
adi_library/intel/avl_dacfifo/avl_dacfifo_constr.sdc
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###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# CDC paths
set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|dac_mem_raddr_g*] \
-to [get_registers *avl_dacfifo_rd:i_rd|avl_mem_raddr_m1*]
set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_mem_waddr_g*] \
-to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_waddr_m1*]
set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_xfer_req_out*] \
-to [get_registers *avl_dacfifo_rd:i_rd|dac_avl_xfer_req_m1*]
set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_mem_laddr_toggle*] \
-to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_laddr_toggle_m[0]]
set_false_path -to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_laddr*]
set_false_path -to [get_registers *avl_dacfifo_rd:i_rd|dac_dma_last_beats_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_xfer_req_lp*] \
-to [get_registers *avl_dacfifo_wr:i_wr|dma_xfer_req_lp_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_xfer_req_out*] \
-to [get_registers *avl_dacfifo_wr:i_wr|dma_avl_xfer_req_out_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_mem_raddr_g*] \
-to [get_registers *avl_dacfifo_wr:i_wr|dma_mem_raddr_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_xfer_req*] \
-to [get_registers *avl_dacfifo_wr:i_wr|avl_dma_xfer_req_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_mem_waddr_g*] \
-to [get_registers *avl_dacfifo_wr:i_wr|avl_mem_waddr_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_last_beats*] \
-to [get_registers *avl_dacfifo_wr:i_wr|avl_dma_last_beats_m1*]
set_false_path -from [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dac_mem_raddr_g*] \
-to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dma_mem_raddr_m1*]
set_false_path -from [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dma_mem_waddr_g*] \
-to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dac_mem_waddr_m1*]
set_false_path -to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dac_xfer_out_m1*]
set_false_path -to [get_registers *avl_dacfifo:*avl_dma_xfer_req_m1*]
set_false_path -to [get_registers *avl_dacfifo:*dac_xfer_out_m1*]
set_false_path -to [get_registers *avl_dacfifo:*bypass_m1*]
set_false_path -to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dma_rst_m1*]
adi_library/intel/avl_dacfifo/avl_dacfifo_hw.tcl
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###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
package require qsys 14.0
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create avl_dacfifo {Avalon DDR DAC Fifo} p_avl_dacfifo_elab
ad_ip_files avl_dacfifo [list\
$ad_hdl_dir/library/common/util_delay.v \
$ad_hdl_dir/library/common/ad_b2g.v \
$ad_hdl_dir/library/common/ad_g2b.v \
$ad_hdl_dir/library/common/ad_mem.v \
util_dacfifo_bypass.v \
avl_dacfifo_wr.v \
avl_dacfifo_rd.v \
avl_dacfifo.v \
avl_dacfifo_constr.sdc]
# parameters
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter DAC_DATA_WIDTH INTEGER 64
ad_ip_parameter DAC_MEM_ADDRESS_WIDTH INTEGER 8
ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
ad_ip_parameter DMA_MEM_ADDRESS_WIDTH INTEGER 8
ad_ip_parameter AVL_DATA_WIDTH INTEGER 512
ad_ip_parameter AVL_ADDRESS_WIDTH INTEGER 25
ad_ip_parameter AVL_BURST_LENGTH INTEGER 127
ad_ip_parameter AVL_BASE_ADDRESS INTEGER 0
ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x800000
# interfaces
ad_interface clock dma_clk input 1 clk
ad_interface reset dma_rst input 1 if_dma_clk
ad_interface signal dma_xfer_req input 1 xfer_req
add_interface s_axis axi4stream end
set_interface_property s_axis associatedClock if_dma_clk
set_interface_property s_axis associatedReset if_dma_rst
add_interface_port s_axis dma_valid tvalid Input 1
add_interface_port s_axis dma_xfer_last tlast Input 1
add_interface_port s_axis dma_ready tready Output 1
add_interface_port s_axis dma_data tdata Input DMA_DATA_WIDTH
ad_interface clock dac_clk input 1 clk
ad_interface reset dac_rst input 1 if_dac_clk
ad_interface signal dac_valid input 1 valid
ad_interface signal dac_data output DAC_DATA_WIDTH data
ad_interface signal dac_dunf output 1 unf
ad_interface signal dac_xfer_out output 1 xfer_out
ad_interface signal bypass input 1 bypass
add_interface avl_clock clock end
add_interface_port avl_clock avl_clk clk input 1
add_interface avl_reset reset end
set_interface_property avl_reset associatedclock avl_clock
add_interface_port avl_reset avl_reset reset input 1
add_interface amm_ddr avalon master
add_interface_port amm_ddr avl_address address output 25
add_interface_port amm_ddr avl_burstcount burstcount output 7
add_interface_port amm_ddr avl_byteenable byteenable output 64
add_interface_port amm_ddr avl_read read output 1
add_interface_port amm_ddr avl_readdata readdata input 512
add_interface_port amm_ddr avl_readdata_valid readdatavalid input 1
add_interface_port amm_ddr avl_ready waitrequest_n input 1
add_interface_port amm_ddr avl_write write output 1
add_interface_port amm_ddr avl_writedata writedata output 512
set_interface_property amm_ddr associatedClock avl_clock
set_interface_property amm_ddr associatedReset avl_reset
set_interface_property amm_ddr addressUnits WORDS
# elaborate
proc p_avl_dacfifo_elab {} {
# read parameters
set m_device_family [get_parameter_value "DEVICE_FAMILY"]
set m_dma_data_width [get_parameter_value "DMA_DATA_WIDTH"]
set m_dma_mem_addr_width [get_parameter_value "DMA_MEM_ADDRESS_WIDTH"]
set m_avl_data_width [get_parameter_value "AVL_DATA_WIDTH"]
set m_avl_addr_width [get_parameter_value "AVL_ADDRESS_WIDTH"]
set m_dac_data_width [get_parameter_value "DAC_DATA_WIDTH"]
set m_dac_mem_addr_width [get_parameter_value "DAC_MEM_ADDRESS_WIDTH"]
set m_dac_mem_addr_width_bypass 10
if {$m_dma_data_width > $m_dac_data_width} {
set m_dma_to_dac_ratio [expr $m_dma_data_width/$m_dac_data_width]
if {$m_dma_to_dac_ratio eq 2} {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 1]
} elseif {$m_dma_to_dac_ratio eq 4} {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 2]
} else {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 3]
}
} else {
set m_dma_to_dac_ratio [expr $m_dac_data_width/$m_dma_data_width]
if {$m_dma_to_dac_ratio eq 1} {
set m_dma_mem_addr_width_bypass $m_dac_mem_addr_width_bypass
} elseif {$m_dma_to_dac_ratio eq 2} {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 1]
} elseif {$m_dma_to_dac_ratio eq 4} {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 2]
} else {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 3]
}
}
# intel memory for WRITE side
add_hdl_instance ad_mem_asym_wr intel_mem_asym 1.0
set_instance_parameter_value ad_mem_asym_wr DEVICE_FAMILY $m_device_family
set_instance_parameter_value ad_mem_asym_wr A_ADDRESS_WIDTH $m_dma_mem_addr_width
set_instance_parameter_value ad_mem_asym_wr A_DATA_WIDTH $m_dma_data_width
set_instance_parameter_value ad_mem_asym_wr B_DATA_WIDTH $m_avl_data_width
# intel memory for READ side
add_hdl_instance ad_mem_asym_rd intel_mem_asym 1.0
set_instance_parameter_value ad_mem_asym_rd DEVICE_FAMILY $m_device_family
set_instance_parameter_value ad_mem_asym_rd A_ADDRESS_WIDTH 0
set_instance_parameter_value ad_mem_asym_rd A_DATA_WIDTH $m_avl_data_width
set_instance_parameter_value ad_mem_asym_rd B_ADDRESS_WIDTH $m_dac_mem_addr_width
set_instance_parameter_value ad_mem_asym_rd B_DATA_WIDTH $m_dac_data_width
# intel memory for bypass logic
add_hdl_instance ad_mem_asym_bypass intel_mem_asym 1.0
set_instance_parameter_value ad_mem_asym_bypass DEVICE_FAMILY $m_device_family
set_instance_parameter_value ad_mem_asym_bypass A_ADDRESS_WIDTH $m_dma_mem_addr_width_bypass
set_instance_parameter_value ad_mem_asym_bypass A_DATA_WIDTH $m_dma_data_width
set_instance_parameter_value ad_mem_asym_bypass B_ADDRESS_WIDTH $m_dac_mem_addr_width_bypass
set_instance_parameter_value ad_mem_asym_bypass B_DATA_WIDTH $m_dac_data_width
}
adi_library/intel/avl_dacfifo/avl_dacfifo_rd.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module avl_dacfifo_rd #(
parameter AVL_DATA_WIDTH = 512,
parameter DAC_DATA_WIDTH = 64,
parameter AVL_BURST_LENGTH = 127,
parameter AVL_DDR_BASE_ADDRESS = 0,
parameter AVL_DDR_ADDRESS_LIMIT = 33554432,
parameter DAC_MEM_ADDRESS_WIDTH = 8
) (
input dac_clk,
input dac_reset,
input dac_valid,
output reg [(DAC_DATA_WIDTH-1):0] dac_data,
output reg dac_xfer_req,
output reg dac_dunf,
input avl_clk,
input avl_reset,
output reg [24:0] avl_address,
output reg [ 6:0] avl_burstcount,
output [63:0] avl_byteenable,
input avl_waitrequest,
input avl_readdatavalid,
output reg avl_read,
input [AVL_DATA_WIDTH-1:0] avl_data,
input [24:0] avl_last_address,
input [ 6:0] avl_last_burstcount,
input [ 7:0] dma_last_beats,
input avl_xfer_req_in,
output reg avl_xfer_req_out
);
// Max supported MEM_RATIO is 16
localparam MEM_RATIO = AVL_DATA_WIDTH/DAC_DATA_WIDTH;
localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH :
(MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) :
(MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) :
(MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH - 3) :
(MEM_RATIO == 16) ? (DAC_MEM_ADDRESS_WIDTH - 4) :
(DAC_MEM_ADDRESS_WIDTH - 5);
localparam AVL_MEM_THRESHOLD_LO = AVL_BURST_LENGTH;
localparam AVL_MEM_THRESHOLD_HI = {(AVL_MEM_ADDRESS_WIDTH){1'b1}} - AVL_BURST_LENGTH;
localparam DAC_MEM_THRESHOLD = 2 * (AVL_BURST_LENGTH * MEM_RATIO);
localparam MEM_WIDTH_DIFF = (MEM_RATIO > 16) ? 5 :
(MEM_RATIO > 8) ? 4 :
(MEM_RATIO > 4) ? 3 :
(MEM_RATIO > 2) ? 2 :
(MEM_RATIO > 1) ? 1 : 1;
// FSM state definition
localparam IDLE = 5'b00001;
localparam XFER_STAGING = 5'b00010;
localparam XFER_FULL_BURST = 5'b00100;
localparam XFER_PARTIAL_BURST = 5'b01000;
localparam XFER_END = 5'b10000;
// internal register
reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_laddr;
reg avl_mem_laddr_toggle;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_g;
reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr;
reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_m1;
reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_m2;
reg avl_mem_request_data;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_addr_diff;
reg [ 4:0] avl_read_state;
reg [ 7:0] avl_burstcounter;
reg avl_inread;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_m1;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_m2;
reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_laddr;
reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_raddr;
reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_raddr_g;
reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_addr_diff;
reg [ 7:0] dac_mem_laddr_waddr;
reg [ 7:0] dac_mem_laddr_raddr;
reg dac_mem_laddr_valid;
reg dac_avl_xfer_req;
reg dac_avl_xfer_req_m1;
reg dac_avl_xfer_req_m2;
reg [ 7:0] dac_dma_last_beats_m1;
reg [ 7:0] dac_dma_last_beats_m2;
reg [ 7:0] dac_dma_last_beats;
reg [ 3:0] dac_mem_laddr_toggle_m;
reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_laddr_b;
reg dac_mem_renable;
reg dac_mem_valid;
reg dac_xfer_req_d;
// internal signals
wire avl_fifo_reset_s;
wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_s;
wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_addr_diff_s;
wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_b2g_s;
wire [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_g2b_s;
wire [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_laddr_s;
wire avl_read_int_s;
wire avl_end_of_burst_s;
wire dac_fifo_reset_s;
wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_addr_diff_s;
wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_s;
wire [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_g2b_s;
wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_raddr_b2g_s;
wire [DAC_DATA_WIDTH-1:0] dac_mem_data_s;
wire dac_mem_laddr_wea_s;
wire dac_mem_laddr_rea_s;
wire dac_mem_laddr_unf_s;
wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_laddr_s;
wire dac_mem_dunf_s;
// An asymmetric memory to transfer data from Avalon interface to DAC
// interface
ad_mem_asym_rd i_mem_asym (
.mem_i_wrclock_clk (avl_clk),
.mem_i_wren_wren (avl_readdatavalid),
.mem_i_wraddress_wraddress (avl_mem_waddr),
.mem_i_datain_datain (avl_data),
.mem_i_rdclock_clk (dac_clk),
.mem_i_rdaddress_rdaddress (dac_mem_raddr),
.mem_o_dataout_dataout (dac_mem_data_s));
// the fifo reset is the dma_xfer_req
assign avl_fifo_reset_s = avl_reset || ~avl_xfer_req_out;
assign dac_fifo_reset_s = dac_reset || ~dac_avl_xfer_req;
// loop back the avl_xfer_req to the WRITE module -- this way we can make
// sure, that in case of a new DMA transfer, the last avalon read burst is
// finished, so the upcomming avalon writes will not block the interface
always @(posedge avl_clk) begin
if (avl_reset == 1'b1) begin
avl_xfer_req_out <= 1'b0;
end else begin
if ((avl_read_state == IDLE) ||
(avl_read_state == XFER_STAGING) ||
(avl_read_state == XFER_END)) begin
avl_xfer_req_out <= avl_xfer_req_in;
end
end
end
// FSM to generate the necessary Avalon Write transactions
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_read_state <= IDLE;
avl_burstcount <= AVL_BURST_LENGTH;
end else begin
case (avl_read_state)
IDLE : begin
if (avl_xfer_req_in == 1'b1) begin
avl_read_state <= XFER_STAGING;
end else begin
avl_read_state <= IDLE;
end
end
XFER_STAGING : begin
if (avl_xfer_req_in == 1'b1) begin
if (avl_mem_request_data == 1'b1) begin
if (avl_address + AVL_BURST_LENGTH <= avl_last_address) begin
avl_read_state <= XFER_FULL_BURST;
avl_burstcount <= AVL_BURST_LENGTH;
end else begin
avl_read_state <= XFER_PARTIAL_BURST;
avl_burstcount <= avl_last_burstcount;
end
end
end else begin
avl_read_state <= IDLE;
end
end
// Avalon transaction with full burst length
XFER_FULL_BURST : begin
if (avl_burstcounter < avl_burstcount) begin
avl_read_state <= XFER_FULL_BURST;
end else begin
avl_read_state <= XFER_STAGING;
end
end
// Avalon transaction with the remaining data, burst length is less than
// the maximum supported burst length
XFER_PARTIAL_BURST : begin
if (avl_burstcounter < avl_burstcount) begin
avl_read_state <= XFER_PARTIAL_BURST;
end else begin
avl_read_state <= XFER_END;
end
end
XFER_END : begin
avl_read_state <= IDLE;
end
default : begin
avl_read_state <= IDLE;
end
endcase
end
end
// FSM outputs
assign avl_read_int_s = ((avl_read_state == XFER_FULL_BURST) ||
(avl_read_state == XFER_PARTIAL_BURST)) ? 1 : 0;
assign avl_end_of_burst_s = (avl_burstcount == avl_burstcounter) ? 1 : 0;
// Avalon address generation and read control signaling
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_address <= AVL_DDR_BASE_ADDRESS;
end else begin
if (avl_end_of_burst_s == 1'b1) begin
avl_address <= (avl_address < avl_last_address) ? avl_address + avl_burstcount : AVL_DDR_BASE_ADDRESS;
end
end
end
always @(posedge avl_clk) begin
if (avl_reset == 1'b1) begin
avl_read <= 1'b0;
avl_inread <= 1'b0;
end else begin
if (avl_read == 1'b0) begin
if ((avl_waitrequest == 1'b0) && (avl_read_int_s == 1'b1) && (avl_inread == 1'b0)) begin
avl_read <= 1'b1;
avl_inread <= 1'b1;
end
end else if ((avl_read == 1'b1) && (avl_waitrequest == 1'b0)) begin
avl_read <= 1'b0;
end
if (avl_end_of_burst_s == 1'b1) begin
avl_inread <= 1'b0;
end
end
end
// Avalon burstcounter
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_burstcounter <= 8'b0;
end else begin
if ((avl_read_int_s == 1'b1) && (avl_readdatavalid == 1'b1)) begin
avl_burstcounter <= (avl_burstcounter < avl_burstcount) ? avl_burstcounter + 1'b1 : 1'b0;
end else if (avl_end_of_burst_s == 1'b1) begin
avl_burstcounter <= 8'b0;
end
end
end
assign avl_byteenable = {64{1'b1}};
// write data from Avalon interface into the async FIFO
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_mem_waddr <= 'b0;
avl_mem_waddr_g <= 'b0;
avl_mem_laddr <= 'b0;
avl_mem_laddr_toggle <= 1'b0;
end else begin
if (avl_readdatavalid == 1'b1) begin
avl_mem_waddr <= avl_mem_waddr + 1'b1;
end
if (avl_read_state == XFER_END) begin
avl_mem_laddr <= avl_mem_waddr - 1'b1;
avl_mem_laddr_toggle <= ~avl_mem_laddr_toggle;
end
avl_mem_waddr_g <= avl_mem_waddr_b2g_s;
end
end
ad_b2g #(
.DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH)
) i_avl_mem_wr_addr_b2g (
.din (avl_mem_waddr),
.dout (avl_mem_waddr_b2g_s));
// control the FIFO to prevent overflow, underflow is monitored
assign avl_mem_raddr_s = (MEM_RATIO == 1) ? avl_mem_raddr :
(MEM_RATIO == 2) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):1] :
(MEM_RATIO == 4) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):2] :
(MEM_RATIO == 8) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):3] :
(MEM_RATIO == 16) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):4] :
avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):5];
assign avl_mem_laddr_s = (MEM_RATIO == 1) ? avl_mem_laddr :
(MEM_RATIO == 2) ? {avl_mem_laddr, 1'b0} :
(MEM_RATIO == 4) ? {avl_mem_laddr, 2'b0} :
(MEM_RATIO == 8) ? {avl_mem_laddr, 3'b0} :
(MEM_RATIO == 16) ? {avl_mem_laddr, 4'b0} :
{avl_mem_laddr, 5'b0};
assign avl_mem_addr_diff_s = {1'b1, avl_mem_waddr} - avl_mem_raddr_s;
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_mem_addr_diff <= 'd0;
avl_mem_raddr <= 'd0;
avl_mem_raddr_m1 <= 'd0;
avl_mem_raddr_m2 <= 'd0;
avl_mem_request_data <= 'd0;
end else begin
avl_mem_raddr_m1 <= dac_mem_raddr_g;
avl_mem_raddr_m2 <= avl_mem_raddr_m1;
avl_mem_raddr <= avl_mem_raddr_g2b_s;
avl_mem_addr_diff <= avl_mem_addr_diff_s[AVL_MEM_ADDRESS_WIDTH-1:0];
if (avl_xfer_req_out == 1'b0) begin
avl_mem_request_data <= 1'b0;
end else if (avl_mem_addr_diff >= AVL_MEM_THRESHOLD_HI) begin
avl_mem_request_data <= 1'b0;
end else if (avl_mem_addr_diff <= AVL_MEM_THRESHOLD_LO) begin
avl_mem_request_data <= 1'b1;
end
end
end
ad_g2b #(
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
) i_avl_mem_rd_addr_g2b (
.din (avl_mem_raddr_m2),
.dout (avl_mem_raddr_g2b_s));
// Push data from the async FIFO to the DAC
// Data flow is controlled by the DAC, no back-pressure. If FIFO is not
// ready, data will be dropped
assign dac_mem_waddr_s = (MEM_RATIO == 1) ? dac_mem_waddr :
(MEM_RATIO == 2) ? {dac_mem_waddr, 1'b0} :
(MEM_RATIO == 4) ? {dac_mem_waddr, 2'b0} :
(MEM_RATIO == 8) ? {dac_mem_waddr, 3'b0} :
(MEM_RATIO == 16) ? {dac_mem_waddr, 4'b0} :
{dac_mem_waddr, 5'b0};
assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr_s} - dac_mem_raddr;
always @(posedge dac_clk) begin
if (dac_fifo_reset_s == 1'b1) begin
dac_mem_waddr_m2 <= 0;
dac_mem_waddr_m1 <= 0;
dac_mem_waddr <= 0;
dac_mem_laddr <= 0;
dac_mem_laddr_toggle_m <= 4'b0;
end else begin
dac_mem_waddr_m1 <= avl_mem_waddr_g;
dac_mem_waddr_m2 <= dac_mem_waddr_m1;
dac_mem_waddr <= dac_mem_waddr_g2b_s;
dac_mem_laddr_toggle_m <= {dac_mem_laddr_toggle_m[2:0], avl_mem_laddr_toggle};
dac_mem_laddr <= (dac_mem_laddr_toggle_m[2] ^ dac_mem_laddr_toggle_m[1]) ?
avl_mem_laddr_s :
dac_mem_laddr;
end
end
// A buffer for storing the dac_mem_laddr (the address of the last avalon
// beat inside the CDC fifo)
// If the stored data sequence is smaller, it can happen that multiple
// dac_mem_laddr values exist in the same time. This buffers stores this
// values and make sure that they are feeded to the read logic in order.
assign dac_mem_laddr_wea_s = dac_mem_laddr_toggle_m[3] ^ dac_mem_laddr_toggle_m[2];
assign dac_mem_laddr_rea_s = ((dac_mem_raddr == dac_mem_laddr_b) &&
(dac_mem_laddr_unf_s == 1'b0)) ? 1'b1 :1'b0;
always @(posedge dac_clk) begin
if (dac_fifo_reset_s == 1'b1) begin
dac_mem_laddr_waddr <= 0;
dac_mem_laddr_raddr <= 0;
end else begin
dac_mem_laddr_waddr <= (dac_mem_laddr_wea_s == 1'b1) ? dac_mem_laddr_waddr + 1 : dac_mem_laddr_waddr;
dac_mem_laddr_raddr <= (dac_mem_laddr_rea_s == 1'b1) ? dac_mem_laddr_raddr + 1 : dac_mem_laddr_raddr;
end
end
assign dac_mem_laddr_unf_s = (dac_mem_laddr_waddr == dac_mem_laddr_raddr) ? 1'b1 : 1'b0;
always @(posedge dac_clk) begin
if (dac_fifo_reset_s == 1'b1) begin
dac_mem_laddr_valid <= 1'b0;
end else begin
if (dac_mem_laddr_wea_s == 1'b1)
dac_mem_laddr_valid <= 1'b1;
end
end
ad_mem #(
.DATA_WIDTH (DAC_MEM_ADDRESS_WIDTH),
.ADDRESS_WIDTH (8)
) i_mem (
.clka (dac_clk),
.wea (dac_mem_laddr_wea_s),
.addra (dac_mem_laddr_waddr),
.dina (dac_mem_laddr),
.clkb (dac_clk),
.reb (1'b1),
.addrb (dac_mem_laddr_raddr),
.doutb (dac_mem_laddr_s));
ad_g2b #(
.DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH)
) i_dac_mem_wr_addr_g2b (
.din (dac_mem_waddr_m2),
.dout (dac_mem_waddr_g2b_s));
always @(posedge dac_clk) begin
if (dac_reset == 1'b1) begin
dac_avl_xfer_req_m2 <= 0;
dac_avl_xfer_req_m1 <= 0;
dac_avl_xfer_req <= 0;
end else begin
dac_avl_xfer_req_m1 <= avl_xfer_req_out;
dac_avl_xfer_req_m2 <= dac_avl_xfer_req_m1;
dac_avl_xfer_req <= dac_avl_xfer_req_m2;
end
end
always @(posedge dac_clk) begin
if (dac_reset == 1'b1) begin
dac_dma_last_beats_m2 <= 0;
dac_dma_last_beats_m1 <= 0;
dac_dma_last_beats <= 0;
end else begin
dac_dma_last_beats_m1 <= dma_last_beats;
dac_dma_last_beats_m2 <= dac_dma_last_beats_m1;
dac_dma_last_beats <= dac_dma_last_beats_m2;
end
end
always @(posedge dac_clk) begin
if (dac_fifo_reset_s == 1'b1) begin
dac_mem_renable <= 1'b0;
dac_mem_valid <= 1'b0;
end else begin
if (dac_mem_dunf_s == 1'b1) begin
dac_mem_renable <= 1'b0;
end else if (dac_mem_addr_diff >= DAC_MEM_THRESHOLD) begin
dac_mem_renable <= 1'b1;
end
dac_mem_valid <= (dac_mem_renable) ? dac_valid : 1'b0;
end
end
assign dac_mem_dunf_s = (dac_mem_addr_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0] == {DAC_MEM_ADDRESS_WIDTH{1'b0}}) ? 1'b1 : 1'b0;
always @(posedge dac_clk) begin
if (dac_fifo_reset_s == 1'b1) begin
dac_mem_raddr <= 0;
dac_mem_raddr_g <= 0;
dac_mem_addr_diff <= 0;
dac_mem_laddr_b <= 0;
end else begin
dac_mem_laddr_b <= (!dac_mem_laddr_unf_s) ? dac_mem_laddr_s : dac_mem_laddr_b;
dac_mem_addr_diff <= dac_mem_addr_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0];
if (dac_mem_valid) begin
if ((dac_dma_last_beats != {MEM_WIDTH_DIFF{1'b1}}) &&
(dac_mem_raddr == (dac_mem_laddr_b + dac_dma_last_beats)) &&
(dac_mem_laddr_valid == 1'b1)) begin
dac_mem_raddr <= dac_mem_raddr + (MEM_RATIO - dac_dma_last_beats);
end else begin
dac_mem_raddr <= dac_mem_raddr + 1'b1;
end
end
dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
end
end
ad_b2g #(
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
) i_dac_mem_rd_addr_b2g (
.din (dac_mem_raddr),
.dout (dac_mem_raddr_b2g_s));
always @(posedge dac_clk) begin
if (dac_fifo_reset_s == 1'b1) begin
dac_xfer_req <= 1'b0;
dac_xfer_req_d <= 1'b0;
dac_data <= {DAC_DATA_WIDTH{1'b0}};
end else begin
dac_xfer_req_d <= dac_mem_renable;
dac_xfer_req <= dac_xfer_req_d;
dac_data <= (dac_xfer_req_d == 1'b1) ? dac_mem_data_s : {DAC_DATA_WIDTH{1'b0}};
end
end
always @(posedge dac_clk) begin
if (dac_fifo_reset_s == 1'b1) begin
dac_dunf <= 1'b0;
end else begin
dac_dunf <= (dac_mem_addr_diff == 0) ? 1'b1 : 1'b0;
end
end
endmodule
adi_library/intel/avl_dacfifo/avl_dacfifo_wr.v
+520
View File
@@ -0,0 +1,520 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module avl_dacfifo_wr #(
parameter AVL_DATA_WIDTH = 512,
parameter DMA_DATA_WIDTH = 64,
parameter AVL_BURST_LENGTH = 128,
parameter AVL_DDR_BASE_ADDRESS = 0,
parameter AVL_DDR_ADDRESS_LIMIT = 33554432,
parameter DMA_MEM_ADDRESS_WIDTH = 10
) (
input dma_clk,
input [DMA_DATA_WIDTH-1:0] dma_data,
input dma_ready,
output reg dma_ready_out,
input dma_valid,
input dma_xfer_req,
input dma_xfer_last,
output reg [ 7:0] dma_last_beats,
input avl_clk,
input avl_reset,
output reg [24:0] avl_address,
output reg [ 6:0] avl_burstcount,
output [63:0] avl_byteenable,
input avl_waitrequest,
output reg avl_write,
output reg [AVL_DATA_WIDTH-1:0] avl_data,
output reg [24:0] avl_last_address,
output reg [ 6:0] avl_last_burstcount,
output reg avl_xfer_req_out,
input avl_xfer_req_in
);
localparam MEM_RATIO = AVL_DATA_WIDTH/DMA_DATA_WIDTH; // Max supported MEM_RATIO is 16
localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH :
(MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) :
(MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) :
(MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) :
(MEM_RATIO == 16) ? (DMA_MEM_ADDRESS_WIDTH - 4) :
(DMA_MEM_ADDRESS_WIDTH - 5);
localparam MEM_WIDTH_DIFF = (MEM_RATIO > 16) ? 5 :
(MEM_RATIO > 8) ? 4 :
(MEM_RATIO > 4) ? 3 :
(MEM_RATIO > 2) ? 2 :
(MEM_RATIO > 1) ? 1 : 1;
localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - AVL_BURST_LENGTH;
// FSM state definition
localparam IDLE = 5'b00001;
localparam XFER_STAGING = 5'b00010;
localparam XFER_FULL_BURST = 5'b00100;
localparam XFER_PARTIAL_BURST = 5'b01000;
localparam XFER_END = 5'b10000;
wire dma_reset;
wire dma_fifo_reset_s;
wire dma_mem_wea_s;
wire [DMA_MEM_ADDRESS_WIDTH :0] dma_mem_addr_diff_s;
wire [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr_s;
wire [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_waddr_b2g_s;
wire [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr_g2b_s;
wire avl_fifo_reset_s;
wire avl_write_int_s;
wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_b2g_s;
wire [DMA_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_m2_g2b_s;
wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_addr_diff_s;
wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_waddr_s;
wire [AVL_DATA_WIDTH-1:0] avl_data_s;
wire avl_xfer_req_lp_s;
reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_waddr;
reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_waddr_g;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr_m1;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr_m2;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr;
reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_addr_diff;
reg dma_xfer_req_d;
reg dma_xfer_req_lp_m1;
reg dma_xfer_req_lp_m2;
reg dma_xfer_req_lp;
reg dma_avl_xfer_req_out_m1;
reg dma_avl_xfer_req_out_m2;
reg dma_avl_xfer_req_out;
reg [ 4:0] avl_write_state;
reg avl_write_d;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_g;
reg [DMA_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr;
reg [DMA_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_m1;
reg [DMA_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_m2;
reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_addr_diff;
reg avl_dma_xfer_req;
reg avl_dma_xfer_req_m1;
reg avl_dma_xfer_req_m2;
reg [ 7:0] avl_dma_last_beats;
reg [ 7:0] avl_dma_last_beats_m1;
reg [ 7:0] avl_dma_last_beats_m2;
reg [ 3:0] avl_xfer_pburst_offset;
reg [ 7:0] avl_burst_counter;
reg avl_last_burst;
reg avl_init_burst;
reg avl_endof_burst;
reg [ 1:0] avl_mem_rvalid;
reg avl_xfer_req_lp;
// An asymmetric memory to transfer data from DMAC interface to Avalon Memory Map
// interface
ad_mem_asym_wr i_mem_asym (
.mem_i_wrclock_clk (dma_clk),
.mem_i_wren_wren (dma_mem_wea_s),
.mem_i_wraddress_wraddress (dma_mem_waddr),
.mem_i_datain_datain (dma_data),
.mem_i_rdclock_clk (avl_clk),
.mem_i_rdaddress_rdaddress (avl_mem_raddr),
.mem_o_dataout_dataout (avl_data_s));
// the fifo reset is the dma_xfer_req
assign dma_reset = ~dma_xfer_req_d & dma_xfer_req;
assign dma_fifo_reset_s = (~dma_xfer_req_lp & dma_xfer_req_lp_m2);
assign avl_fifo_reset_s = (avl_reset == 1'b1) ||
(avl_dma_xfer_req_m2 & ~avl_dma_xfer_req);
always @(posedge dma_clk) begin
dma_xfer_req_d <= dma_xfer_req;
end
always @(posedge dma_clk) begin
if (dma_reset) begin
dma_xfer_req_lp_m1 <= 1'b0;
dma_xfer_req_lp_m2 <= 1'b0;
dma_xfer_req_lp <= 1'b0;
dma_avl_xfer_req_out_m1 <= 1'b0;
dma_avl_xfer_req_out_m2 <= 1'b0;
dma_avl_xfer_req_out <= 1'b0;
end else begin
dma_xfer_req_lp_m1 <= avl_xfer_req_lp;
dma_xfer_req_lp_m2 <= dma_xfer_req_lp_m1;
dma_xfer_req_lp <= dma_xfer_req_lp_m2;
dma_avl_xfer_req_out_m1 <= avl_xfer_req_out;
dma_avl_xfer_req_out_m2 <= dma_avl_xfer_req_out_m1;
dma_avl_xfer_req_out <= dma_avl_xfer_req_out_m2;
end
end
// write address generation
assign dma_mem_wea_s = dma_ready & dma_valid;
always @(posedge dma_clk) begin
if ((dma_fifo_reset_s == 1'b1) || (dma_avl_xfer_req_out == 1'b1)) begin
dma_mem_waddr <= 0;
dma_mem_waddr_g <= 0;
end else begin
if (dma_mem_wea_s == 1'b1) begin
dma_mem_waddr <= dma_mem_waddr + 1'b1;
end
end
dma_mem_waddr_g <= dma_mem_waddr_b2g_s;
end
always @(posedge dma_clk) begin
if (dma_fifo_reset_s == 1'b1) begin
dma_last_beats <= 0;
end else begin
if ((dma_xfer_last == 1'b1) && (dma_mem_wea_s == 1'b1)) begin
dma_last_beats <= dma_mem_waddr[MEM_WIDTH_DIFF-1:0];
end
end
end
ad_b2g #(
.DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH)
) i_dma_mem_waddr_b2g (
.din (dma_mem_waddr),
.dout (dma_mem_waddr_b2g_s));
// The memory module request data until reaches the high threshold.
assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
assign dma_mem_raddr_s = (MEM_RATIO == 1) ? {dma_mem_raddr, {0{1'b0}}} :
(MEM_RATIO == 2) ? {dma_mem_raddr, {1{1'b0}}} :
(MEM_RATIO == 4) ? {dma_mem_raddr, {2{1'b0}}} :
(MEM_RATIO == 8) ? {dma_mem_raddr, {3{1'b0}}} :
(MEM_RATIO == 16) ? {dma_mem_raddr, {4{1'b0}}} :
{dma_mem_raddr, {5{1'b0}}};
always @(posedge dma_clk) begin
if (dma_fifo_reset_s == 1'b1) begin
dma_mem_addr_diff <= 'b0;
dma_mem_raddr_m1 <= 'b0;
dma_mem_raddr_m2 <= 'b0;
dma_mem_raddr <= 'b0;
dma_ready_out <= 1'b0;
end else begin
dma_mem_raddr_m1 <= avl_mem_raddr_g;
dma_mem_raddr_m2 <= dma_mem_raddr_m1;
dma_mem_raddr <= dma_mem_raddr_g2b_s;
dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0];
if (dma_xfer_req_lp == 1'b1) begin
dma_ready_out <= (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) ? 1'b0 : 1'b1;
end else begin
dma_ready_out <= 1'b0;
end
end
end
ad_g2b #(
.DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH)
) i_dma_mem_rd_address_g2b (
.din (dma_mem_raddr_m2),
.dout (dma_mem_raddr_g2b_s));
always @(posedge avl_clk) begin
if (avl_reset == 1'b1) begin
avl_dma_xfer_req_m1 <= 'b0;
avl_dma_xfer_req_m2 <= 'b0;
avl_dma_xfer_req <= 'b0;
end else begin
avl_dma_xfer_req_m1 <= dma_xfer_req;
avl_dma_xfer_req_m2 <= avl_dma_xfer_req_m1;
avl_dma_xfer_req <= avl_dma_xfer_req_m2;
end
end
assign avl_xfer_req_lp_s = avl_dma_xfer_req & ~avl_xfer_req_in;
always @(posedge avl_clk) begin
if (avl_reset == 1'b1) begin
avl_xfer_req_lp <= 1'b0;
end else begin
avl_xfer_req_lp <= avl_xfer_req_lp_s;
end
end
// FSM to generate the necessary Avalon Write transactions
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_write_state <= IDLE;
avl_last_burst <= 1'b0;
avl_init_burst <= 1'b0;
avl_endof_burst <= 1'b0;
end else begin
case (avl_write_state)
IDLE : begin
if (avl_dma_xfer_req == 1'b1) begin
avl_write_state <= XFER_STAGING;
end else begin
avl_write_state <= IDLE;
end
end
XFER_STAGING : begin
avl_endof_burst <= 1'b0;
if (avl_xfer_req_lp == 1'b1) begin
// there are enough data for one transaction
if (avl_mem_addr_diff >= AVL_BURST_LENGTH) begin
avl_write_state <= XFER_FULL_BURST;
avl_init_burst <= 1'b1;
end else begin
avl_write_state <= XFER_STAGING;
end
end else if ((avl_dma_xfer_req == 1'b0) && (avl_xfer_pburst_offset == 4'b0)) begin // DMA transfer was finished
if (avl_mem_addr_diff >= AVL_BURST_LENGTH) begin
avl_write_state <= XFER_FULL_BURST;
avl_init_burst <= 1'b1;
end else if ((avl_mem_addr_diff > 0) ||
(avl_dma_last_beats[MEM_WIDTH_DIFF-1:0] != {MEM_WIDTH_DIFF{1'b1}})) begin
avl_write_state <= XFER_PARTIAL_BURST;
avl_last_burst <= 1'b1;
end else begin
avl_write_state <= XFER_END;
end
end else begin
avl_write_state <= XFER_STAGING;
end
end
// Avalon transaction with full burst length
XFER_FULL_BURST : begin
avl_init_burst <= 1'b0;
if ((avl_burst_counter < avl_burstcount) || ((avl_waitrequest) || (avl_write))) begin
avl_write_state <= XFER_FULL_BURST;
end else begin
avl_write_state <= XFER_STAGING;
avl_endof_burst <= 1'b1;
end
end
// Avalon transaction with the remaining data, burst length is less than
// the maximum supported burst length
XFER_PARTIAL_BURST : begin
avl_last_burst <= 1'b0;
if ((avl_burst_counter < avl_burstcount) || ((avl_waitrequest) || (avl_write))) begin
avl_write_state <= XFER_PARTIAL_BURST;
end else begin
avl_write_state <= XFER_END;
end
end
XFER_END : begin
avl_write_state <= IDLE;
end
default : begin
avl_write_state <= IDLE;
end
endcase
end
end
// FSM outputs
assign avl_write_int_s = ((avl_write_state == XFER_FULL_BURST) ||
(avl_write_state == XFER_PARTIAL_BURST)) ? 1'b1 : 1'b0;
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_mem_waddr_m1 <= 'b0;
avl_mem_waddr_m2 <= 'b0;
avl_mem_waddr <= 'b0;
avl_xfer_pburst_offset <= 4'b1111;
end else begin
avl_mem_waddr_m1 <= dma_mem_waddr_g;
avl_mem_waddr_m2 <= avl_mem_waddr_m1;
avl_mem_waddr <= avl_mem_waddr_m2_g2b_s;
if ((avl_dma_xfer_req == 0) && (avl_xfer_pburst_offset > 0)) begin
avl_xfer_pburst_offset <= avl_xfer_pburst_offset - 4'b1;
end
end
end
ad_g2b #(
.DATA_WIDTH (DMA_MEM_ADDRESS_WIDTH)
) i_avl_mem_waddr_g2b (
.din (avl_mem_waddr_m2),
.dout (avl_mem_waddr_m2_g2b_s));
// ASYNC MEM read control
assign avl_mem_waddr_s = (MEM_RATIO == 1) ? {avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):0]} :
(MEM_RATIO == 2) ? {avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):1]} :
(MEM_RATIO == 4) ? {avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):2]} :
(MEM_RATIO == 8) ? {avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):3]} :
{avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):4]};
assign avl_mem_addr_diff_s = {1'b1, avl_mem_waddr_s} - avl_mem_raddr;
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_mem_addr_diff <= 'b0;
end else begin
avl_mem_addr_diff <= avl_mem_addr_diff_s[(AVL_MEM_ADDRESS_WIDTH-1):0];
end
end
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_mem_rvalid <= 2'b0;
avl_mem_raddr <= 'b0;
avl_mem_raddr_g <= 'b0;
end else begin
if (~avl_waitrequest && avl_write) begin
avl_mem_rvalid[0] <= 1'b1;
avl_mem_rvalid[1] <= avl_mem_rvalid[0];
end else begin
avl_mem_rvalid <= {avl_mem_rvalid[0], 1'b0};
end
if (~avl_waitrequest && avl_write) begin
avl_mem_raddr <= avl_mem_raddr + 1'b1;
end
if (avl_write_state == XFER_END) begin
avl_mem_raddr <= 'b0;
end
avl_mem_raddr_g <= avl_mem_raddr_b2g_s;
end
end
ad_b2g #(
.DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH)
) i_avl_mem_rd_address_b2g (
.din (avl_mem_raddr),
.dout (avl_mem_raddr_b2g_s));
// Avalon write address
always @(posedge avl_clk) begin
if (avl_fifo_reset_s == 1'b1) begin
avl_address <= AVL_DDR_BASE_ADDRESS;
end else begin
if (avl_endof_burst == 1'b1) begin
avl_address <= (avl_address < AVL_DDR_ADDRESS_LIMIT) ? avl_address + AVL_BURST_LENGTH : AVL_DDR_BASE_ADDRESS;
end
end
end
// Avalon write
always @(posedge avl_clk) begin
if ((avl_fifo_reset_s == 1'b1) || (avl_write_state == XFER_END)) begin
avl_write <= 1'b0;
avl_write_d <= 1'b0;
avl_data <= 'b0;
end else begin
if (~avl_waitrequest) begin
avl_write_d <= (avl_init_burst || avl_last_burst) ||
(avl_write_int_s & avl_mem_rvalid[1]);
avl_write <= avl_write_d;
avl_data <= avl_data_s;
end
end
end
// Avalon burstcount & counter
always @(posedge avl_clk) begin
if (avl_reset) begin
avl_burstcount <= 'b1;
avl_burst_counter <= 'b0;
end else begin
if (avl_last_burst) begin
if (avl_dma_last_beats[MEM_WIDTH_DIFF-1:0] != {MEM_WIDTH_DIFF{1'b1}}) begin
avl_burstcount <= avl_mem_addr_diff + 1;
end else begin
avl_burstcount <= avl_mem_addr_diff;
end
end else if (avl_write_state != XFER_PARTIAL_BURST) begin
avl_burstcount <= AVL_BURST_LENGTH;
end
if (avl_write_state == XFER_STAGING) begin
avl_burst_counter <= 'b0;
end else if (avl_write_d && ~avl_waitrequest) begin
avl_burst_counter <= avl_burst_counter + 1'b1;
end
end
end
// generate avl_byteenable signal
always @(posedge avl_clk) begin
if (avl_reset == 1'b1) begin
avl_dma_last_beats_m1 <= 8'b0;
avl_dma_last_beats_m2 <= 8'b0;
avl_dma_last_beats <= 8'b0;
end else begin
avl_dma_last_beats_m1 <= dma_last_beats;
avl_dma_last_beats_m2 <= avl_dma_last_beats_m1;
avl_dma_last_beats <= avl_dma_last_beats_m2;
end
end
assign avl_byteenable = {64{1'b1}};
// save the last address and byteenable
always @(posedge avl_clk) begin
if (avl_reset == 1'b1) begin
avl_last_address <= 0;
avl_last_burstcount <= 'b0;
end else begin
if (avl_write && ~avl_waitrequest) begin
avl_last_address <= avl_address;
avl_last_burstcount <= avl_burstcount;
end
end
end
// avl_xfer_req generation for synchronize the access of the external
// memory
always @(posedge avl_clk) begin
if (avl_reset == 1'b1) begin
avl_xfer_req_out <= 1'b0;
end else begin
if (avl_write_state == XFER_END) begin
avl_xfer_req_out <= 1'b1;
end else if (avl_write_state == XFER_STAGING) begin
avl_xfer_req_out <= 1'b0;
end
end
end
endmodule
adi_library/intel/avl_dacfifo/util_dacfifo_bypass.v
+275
View File
@@ -0,0 +1,275 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_dacfifo_bypass #(
parameter DAC_DATA_WIDTH = 64,
parameter DMA_DATA_WIDTH = 64
) (
// DMA FIFO interface
input dma_clk,
input [(DMA_DATA_WIDTH-1):0] dma_data,
input dma_ready,
output reg dma_ready_out,
input dma_valid,
// request and synchronization
input dma_xfer_req,
// dac fifo interface
input dac_clk,
input dac_rst,
input dac_valid,
output reg [(DAC_DATA_WIDTH-1):0] dac_data,
output reg dac_dunf
);
// supported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH :
DAC_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DAC_ADDRESS_WIDTH = 10;
localparam DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :
(MEM_RATIO == 2) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 1) : (DAC_ADDRESS_WIDTH + 1)) :
(MEM_RATIO == 4) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH + 2)) :
((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 3) : (DAC_ADDRESS_WIDTH + 3));
localparam DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4;
localparam DAC_BUF_THRESHOLD_LO = 4;
reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0;
reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0;
reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0;
reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0;
reg dac_mem_rea = 1'b0;
reg dac_mem_rea_d = 1'b0;
reg dma_rst_m1 = 1'b0;
reg dma_rst = 1'b0;
reg [DMA_ADDRESS_WIDTH-1:0] dma_mem_addr_diff = 1'b0;
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 1'b0;
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 1'b0;
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr = 1'b0;
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 1'b0;
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 1'b0;
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr = 1'b0;
reg dac_xfer_out = 1'b0;
reg dac_xfer_out_m1 = 1'b0;
// internal signals
wire [(DAC_ADDRESS_WIDTH):0] dac_mem_addr_diff_s;
wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_raddr_s;
wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_s;
wire dma_mem_wea_s;
wire dac_mem_rea_s;
wire [(DAC_DATA_WIDTH-1):0] dac_mem_rdata_s;
wire [DMA_ADDRESS_WIDTH:0] dma_address_diff_s;
wire dac_mem_empty_s;
wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s;
wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s;
wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;
wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
// An asymmetric memory to transfer data from DMAC interface to DAC interface
ad_mem_asym_bypass i_mem_asym (
.mem_i_wrclock_clk (dma_clk),
.mem_i_wren_wren (dma_mem_wea_s),
.mem_i_wraddress_wraddress (dma_mem_waddr),
.mem_i_datain_datain (dma_data),
.mem_i_rdclock_clk (dac_clk),
.mem_i_rdaddress_rdaddress (dac_mem_raddr),
.mem_o_dataout_dataout (dac_mem_rdata_s));
// dma reset is brought from dac domain
always @(posedge dma_clk) begin
dma_rst_m1 <= dac_rst;
dma_rst <= dma_rst_m1;
end
// Write address generation for the asymmetric memory
assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_mem_waddr <= 'h0;
dma_mem_waddr_g <= 'h0;
end else begin
if (dma_mem_wea_s == 1'b1) begin
dma_mem_waddr <= dma_mem_waddr + 1'b1;
end
dma_mem_waddr_g <= dma_mem_waddr_b2g_s;
end
end
ad_b2g #(
.DATA_WIDTH (DMA_ADDRESS_WIDTH)
) i_dma_mem_waddr_b2g (
.din (dma_mem_waddr),
.dout (dma_mem_waddr_b2g_s));
// The memory module request data until reaches the high threshold.
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_mem_addr_diff <= 'b0;
dma_mem_raddr_m1 <= 'b0;
dma_mem_raddr_m2 <= 'b0;
dma_mem_raddr <= 'b0;
dma_ready_out <= 1'b0;
end else begin
dma_mem_raddr_m1 <= dac_mem_raddr_g;
dma_mem_raddr_m2 <= dma_mem_raddr_m1;
dma_mem_raddr <= dma_mem_raddr_m2_g2b_s;
dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0];
if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
dma_ready_out <= 1'b0;
end else begin
dma_ready_out <= 1'b1;
end
end
end
ad_g2b #(
.DATA_WIDTH (DAC_ADDRESS_WIDTH)
) i_dma_mem_raddr_g2b (
.din (dma_mem_raddr_m2),
.dout (dma_mem_raddr_m2_g2b_s));
// relative address offset on dma domain
assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
((MEM_RATIO == 1) ? (dma_mem_raddr) :
(MEM_RATIO == 2) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):1]) :
(MEM_RATIO == 4) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):2]) : (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):3])) :
((MEM_RATIO == 1) ? (dma_mem_raddr) :
(MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) :
(MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0}));
// relative address offset on dac domain
assign dac_address_diff_s = {1'b1, dac_mem_waddr_s} - dac_mem_raddr;
assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ?
((MEM_RATIO == 1) ? (dac_mem_waddr) :
(MEM_RATIO == 2) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):1]) :
(MEM_RATIO == 4) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):2]) : (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):3])) :
((MEM_RATIO == 1) ? (dac_mem_waddr) :
(MEM_RATIO == 2) ? ({dac_mem_waddr, 1'b0}) :
(MEM_RATIO == 4) ? ({dac_mem_waddr, 2'b0}) : ({dac_mem_waddr, 3'b0}));
// Read address generation for the asymmetric memory
assign dac_mem_empty_s = (dac_mem_waddr_s == dac_mem_raddr) ? 1'b1 : 1'b0;
assign dac_mem_rea_s = dac_valid & !dac_mem_empty_s;
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_mem_raddr <= 'h0;
dac_mem_raddr_g <= 'h0;
end else begin
if (dac_mem_rea_s == 1'b1) begin
dac_mem_raddr <= dac_mem_raddr + 1'b1;
end
dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
end
end
// compensate the read latency of the memory
always @(posedge dac_clk) begin
dac_mem_rea_d <= dac_mem_rea_s;
dac_mem_rea <= dac_mem_rea_d;
end
ad_b2g #(
.DATA_WIDTH (DAC_ADDRESS_WIDTH)
) i_dac_mem_raddr_b2g (
.din (dac_mem_raddr),
.dout (dac_mem_raddr_b2g_s));
// transfer the write address into the DAC's clock domain
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_mem_waddr_m1 <= 'b0;
dac_mem_waddr_m2 <= 'b0;
dac_mem_waddr <= 'b0;
end else begin
dac_mem_waddr_m1 <= dma_mem_waddr_g;
dac_mem_waddr_m2 <= dac_mem_waddr_m1;
dac_mem_waddr <= dac_mem_waddr_m2_g2b_s;
end
end
ad_g2b #(
.DATA_WIDTH (DMA_ADDRESS_WIDTH)
) i_dac_mem_waddr_g2b (
.din (dac_mem_waddr_m2),
.dout (dac_mem_waddr_m2_g2b_s));
// define underflow
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_xfer_out_m1 <= 1'b0;
dac_xfer_out <= 1'b0;
dac_dunf <= 1'b0;
end else begin
dac_xfer_out_m1 <= dma_xfer_req;
dac_xfer_out <= dac_xfer_out_m1;
if (dac_valid == 1'b1) begin
dac_dunf <= dac_mem_empty_s;
end
end
end
// DAC data output logic - make sure that the data output is zero between
// transfers
always @(posedge dac_clk) begin
if (dac_dunf == 1'b1) begin
dac_data <= 0;
end else begin
dac_data <= dac_mem_rdata_s;
end
end
endmodule