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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
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adi_library/intel/axi_adxcvr/.timestamp_intel
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adi_library/intel/axi_adxcvr/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_adxcvr
INTEL_DEPS += ../../common/up_axi.v
INTEL_DEPS += axi_adxcvr.v
INTEL_DEPS += axi_adxcvr_hw.tcl
INTEL_DEPS += axi_adxcvr_up.v
include ../../scripts/library.mk
adi_library/intel/axi_adxcvr/axi_adxcvr.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_adxcvr #(
// parameters
parameter integer ID = 0,
parameter [ 7:0] FPGA_TECHNOLOGY = 0,
parameter [ 7:0] FPGA_FAMILY = 0,
parameter [ 7:0] SPEED_GRADE = 0,
parameter [ 7:0] DEV_PACKAGE = 0,
parameter [15:0] FPGA_VOLTAGE = 0,
parameter integer XCVR_TYPE = 0,
parameter integer TX_OR_RX_N = 0,
parameter integer NUM_OF_LANES = 4
) (
// xcvr, lane-pll and ref-pll are shared
output up_rst,
input up_pll_locked,
input [(NUM_OF_LANES-1):0] up_ready,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [11:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [11:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
// internal signals
wire up_rstn;
wire up_clk;
wire up_wreq;
wire [ 9:0] up_waddr;
wire [31:0] up_wdata;
wire up_wack;
wire up_rreq;
wire [ 9:0] up_raddr;
wire [31:0] up_rdata;
wire up_rack;
// clk & rst
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// instantiations
axi_adxcvr_up #(
.ID (ID),
.XCVR_TYPE (XCVR_TYPE),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.FPGA_VOLTAGE (FPGA_VOLTAGE),
.TX_OR_RX_N (TX_OR_RX_N),
.NUM_OF_LANES (NUM_OF_LANES)
) i_up (
.up_rst (up_rst),
.up_pll_locked (up_pll_locked),
.up_ready (up_ready),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
up_axi #(
.AXI_ADDRESS_WIDTH (12)
) i_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
adi_library/intel/axi_adxcvr/axi_adxcvr_hw.tcl
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###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
package require qsys 14.0
package require quartus::device
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
set_module_property NAME axi_adxcvr
set_module_property DESCRIPTION "AXI ADXCVR Core"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_adxcvr
set_module_property ELABORATION_CALLBACK p_axi_adxcvr
set_module_property VALIDATION_CALLBACK info_param_validate
# files
ad_ip_files axi_adxcvr [list \
$ad_hdl_dir/library/common/up_axi.v \
axi_adxcvr_up.v \
axi_adxcvr.v \
]
# parameters
add_parameter ID INTEGER 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter TX_OR_RX_N INTEGER 0
set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
set_parameter_property TX_OR_RX_N UNITS None
set_parameter_property TX_OR_RX_N HDL_PARAMETER true
add_parameter NUM_OF_LANES INTEGER 4
set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER true
adi_add_auto_fpga_spec_params
adi_add_device_spec_param XCVR_TYPE
adi_add_device_spec_param FPGA_VOLTAGE
set_parameter_property FPGA_VOLTAGE DISPLAY_UNITS mV
set_parameter_property FPGA_VOLTAGE_MANUAL DISPLAY_UNITS mV
adi_add_indep_spec_params_overwrite XCVR_TYPE
adi_add_indep_spec_params_overwrite FPGA_VOLTAGE
# axi4 slave interface
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
# xcvr interface
ad_interface reset up_rst output 1 s_axi_clock
set_interface_property if_up_rst associatedResetSinks s_axi_reset
add_interface core_pll_locked conduit end
add_interface_port core_pll_locked up_pll_locked pll_locked Input 1
# name changes
proc p_axi_adxcvr {} {
set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N]
set m_num_of_lanes [get_parameter_value NUM_OF_LANES]
if {$m_tx_or_rx_n == 1} {
add_interface ready conduit end
add_interface_port ready up_ready tx_ready input $m_num_of_lanes
}
if {$m_tx_or_rx_n == 0} {
add_interface ready conduit end
add_interface_port ready up_ready rx_ready input $m_num_of_lanes
}
}
adi_library/intel/axi_adxcvr/axi_adxcvr_up.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adxcvr_up #(
// parameters
parameter integer ID = 0,
parameter [ 7:0] FPGA_TECHNOLOGY = 0,
parameter [ 7:0] FPGA_FAMILY = 0,
parameter [ 7:0] SPEED_GRADE = 0,
parameter [ 7:0] DEV_PACKAGE = 0,
parameter [15:0] FPGA_VOLTAGE = 0,
parameter integer XCVR_TYPE = 0,
parameter integer TX_OR_RX_N = 0,
parameter integer NUM_OF_LANES = 4
) (
// xcvr, lane-pll and ref-pll are shared
output up_rst,
input up_pll_locked,
input [(NUM_OF_LANES-1):0] up_ready,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 9:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [ 9:0] up_raddr,
output [31:0] up_rdata,
output up_rack
);
// parameters
localparam [31:0] VERSION = 32'h00110161;
// internal registers
reg up_wreq_d = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg [ 3:0] up_rst_cnt = 'd8;
reg up_status_int = 'd0;
reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0;
// internal signals
wire up_ready_s;
wire [31:0] up_status_32_s;
wire [31:0] up_rparam_s;
// defaults
assign up_wack = up_wreq_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wreq_d <= 'd0;
up_scratch <= 'd0;
end else begin
up_wreq_d <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin
up_scratch <= up_wdata;
end
end
end
// reset-controller
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_resetn <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin
up_resetn <= up_wdata[0];
end
end
end
assign up_rst = up_rst_cnt[3];
assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0;
assign up_status_32_s[NUM_OF_LANES] = up_pll_locked;
assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rst_cnt <= 4'h8;
up_status_int <= 1'b0;
end else begin
if (up_resetn == 1'b0) begin
up_rst_cnt <= 4'h8;
end else if (up_rst_cnt[3] == 1'b1) begin
up_rst_cnt <= up_rst_cnt + 1'b1;
end
if (up_resetn == 1'b0) begin
up_status_int <= 1'b0;
end else if (up_ready_s == 1'b1) begin
up_status_int <= 1'b1;
end
end
end
// Specific to Intel
assign up_rparam_s[31:28] = 8'd0;
assign up_rparam_s[27:24] = XCVR_TYPE[3:0];
// Specific to Xilinx
assign up_rparam_s[23:16] = 8'd0;
// generic
assign up_rparam_s[15: 9] = 7'd0;
assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1;
assign up_rparam_s[ 7: 0] = NUM_OF_LANES[7:0];
// read interface
assign up_rack = up_rreq_d;
assign up_rdata = up_rdata_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rreq_d <= 'd0;
up_rdata_d <= 'd0;
end else begin
up_rreq_d <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr)
10'h000: up_rdata_d <= VERSION;
10'h001: up_rdata_d <= ID;
10'h002: up_rdata_d <= up_scratch;
10'h004: up_rdata_d <= {31'd0, up_resetn};
10'h005: up_rdata_d <= {31'd0, up_status_int};
10'h006: up_rdata_d <= up_status_32_s;
10'h007: up_rdata_d <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
10'h009: up_rdata_d <= up_rparam_s;
10'h050: up_rdata_d <= {16'd0, FPGA_VOLTAGE}; // mV
default: up_rdata_d <= 32'd0;
endcase
end else begin
up_rdata_d <= 32'd0;
end
end
end
endmodule