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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
commit 315a673005
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adi_library/intel/jesd204_phy/.timestamp_intel
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adi_library/intel/jesd204_phy/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := jesd204_phy
INTEL_DEPS += jesd204_phy_glue.v
INTEL_DEPS += jesd204_phy_glue_hw.tcl
INTEL_DEPS += jesd204_phy_hw.tcl
INTEL_LIB_DEPS += jesd204/jesd204_soft_pcs_rx
INTEL_LIB_DEPS += jesd204/jesd204_soft_pcs_tx
include ../../scripts/library.mk
adi_library/intel/jesd204_phy/jesd204_phy_glue.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module jesd204_phy_glue #(
parameter WIDTH = 20,
parameter CONST_WIDTH = 1,
parameter NUM_OF_LANES = 1,
parameter LANE_INVERT = 0
) (
input [WIDTH-1:0] in,
output [WIDTH-1:0] out,
output [CONST_WIDTH-1:0] const_out,
output [NUM_OF_LANES-1:0] polinv
);
/* There really should be a standard component in Qsys that allows to do this */
assign out = in;
assign const_out = {CONST_WIDTH{1'b0}};
assign polinv = LANE_INVERT[NUM_OF_LANES-1:0];
endmodule
adi_library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
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###############################################################################
## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
package require qsys 14.0
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_ip_intel.tcl
#
# For whatever strange reason all the interface of the native PHY become
# conduits when it is instantiated in a compose callback. This glue logic module
# converts the interfaces to their proper type.
#
ad_ip_create jesd204_phy_glue {Native PHY to JESD204 glue logic} \
jesd204_phy_glue_elab
set_module_property INTERNAL true
# files
ad_ip_files jesd204_phy_glue [list \
jesd204_phy_glue.v \
]
# parameters
ad_ip_parameter DEVICE STRING "" false
ad_ip_parameter TX_OR_RX_N BOOLEAN false false
ad_ip_parameter SOFT_PCS BOOLEAN false false
ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false
ad_ip_parameter NUM_OF_LANES POSITIVE 4 true
ad_ip_parameter LANE_INVERT INTEGER 0 true
ad_ip_parameter WIDTH NATURAL 20 true { \
DERIVED true \
}
ad_ip_parameter CONST_WIDTH NATURAL 1 true { \
DERIVED true \
}
proc glue_add_if {num name type dir {bcast false}} {
if {$bcast} {
add_interface ${name} $type $dir
} else {
for {set i 0} {$i < $num} {incr i} {
add_interface ${name}_${i} $type $dir
}
}
add_interface phy_${name} conduit end
}
proc glue_add_if_port {num ifname port role dir width {bcast false}} {
variable sig_offset
set phy_width [expr $num * $width]
if {$dir == "Input"} {
set sig "in"
set phy_dir "Output"
set phy_sig "out"
} else {
set sig "out"
set phy_dir "Input"
set phy_sig "in"
}
if {$bcast} {
add_interface_port ${ifname} ${port} $role $dir $width
set_port_property ${port} fragment_list \
[format "%s(%d:%d)" $sig [expr $sig_offset + $width - 1] $sig_offset]
} else {
for {set i 0} {$i < $num} {incr i} {
set base [expr $sig_offset + $width * $i]
add_interface_port ${ifname}_${i} ${port}_${i} $role $dir $width
set_port_property ${port}_${i} fragment_list \
[format "%s(%d:%d)" $sig [expr $base + $width - 1] $base]
}
}
add_interface_port phy_${ifname} phy_${port} $role $phy_dir $phy_width
if {$bcast} {
set _frag [format "%s(%d:%d)" $phy_sig [expr $sig_offset + $width - 1] $sig_offset]
set sig_offset [expr $sig_offset + $width]
set frag "${_frag}"
for {set i 1} {$i < $num} {incr i} {
set frag [concat ${frag} ${_frag}]
}
} else {
set frag [format "%s(%d:%d)" $phy_sig [expr $sig_offset + $phy_width - 1] $sig_offset]
set sig_offset [expr $sig_offset + $phy_width]
}
set_port_property phy_${port} fragment_list $frag
}
proc glue_add_tx_serial_clk {num_of_lanes} {
variable sig_offset
# The serial clock is special. The first 6 transceivers use the x1 connection
# since they are in the same bank as the PLL. The others have to use the xN
# connection through the CGB.
if {$num_of_lanes > 6} {
set clk0_width 6
set clk1_width [expr $num_of_lanes - 6]
} else {
set clk0_width $num_of_lanes
set clk1_width 0
}
add_interface tx_serial_clk_x1 hssi_serial_clock sink
add_interface_port tx_serial_clk_x1 tx_serial_clk_x1 clk Input 1
set_port_property tx_serial_clk_x1 fragment_list \
[format "in(%d:%d)" $sig_offset $sig_offset]
add_interface phy_tx_serial_clk0 conduit end
add_interface_port phy_tx_serial_clk0 phy_tx_serial_clk0 clk Output $num_of_lanes
set _frag [format "out(%d:%d)" $sig_offset $sig_offset]
set sig_offset [expr $sig_offset + 1]
set frag "${_frag}"
for {set i 1} {$i < $clk0_width} {incr i} {
set frag [concat ${_frag} ${frag}]
}
if {$num_of_lanes > 6} {
add_interface tx_serial_clk_xN hssi_serial_clock sink
add_interface_port tx_serial_clk_xN tx_serial_clk_xN clk Input 1
set_port_property tx_serial_clk_xN fragment_list \
[format "in(%d:%d)" $sig_offset $sig_offset]
set _frag [format "out(%d:%d)" $sig_offset $sig_offset]
set sig_offset [expr $sig_offset + 1]
for {set i 0} {$i < $clk1_width} {incr i} {
set frag [concat ${_frag} ${frag}]
}
}
set_port_property phy_tx_serial_clk0 fragment_list $frag
}
proc glue_add_if_port_conduit {num ifname port phy_port dir width} {
variable sig_offset
set phy_width [expr $num * $width]
if {$dir == "Input"} {
set sig "in"
set phy_dir "Output"
set phy_sig "out"
} else {
set sig "out"
set phy_dir "Input"
set phy_sig "in"
}
for {set i 0} {$i < $num} {incr i} {
set base [expr $sig_offset + $width * $i]
add_interface_port ${ifname}_${i} ${ifname}_${port}_${i} $port $dir $width
set_port_property ${ifname}_${port}_${i} fragment_list \
[format "%s(%d:%d)" $sig [expr $base + $width - 1] $base]
}
add_interface phy_${phy_port} conduit end
add_interface_port phy_${phy_port} phy_${phy_port} $phy_port $phy_dir $phy_width
set_port_property phy_${phy_port} fragment_list \
[format "%s(%d:%d)" $phy_sig [expr $sig_offset + $phy_width - 1] $sig_offset]
set sig_offset [expr $sig_offset + $phy_width]
}
proc glue_add_const_conduit {port width} {
variable const_offset
set ifname phy_${port}
add_interface $ifname conduit end
add_interface_port $ifname $ifname $port Output $width
set_port_property $ifname fragment_list [format "const_out(%d:%d)" \
[expr $const_offset + $width - 1] $const_offset]
set const_offset [expr $const_offset + $width]
}
proc jesd204_phy_glue_elab {} {
variable sig_offset
variable const_offset
set device [get_parameter DEVICE]
set soft_pcs [get_parameter SOFT_PCS]
set num_of_lanes [get_parameter NUM_OF_LANES]
set bonding_clocks_en [get_parameter BONDING_CLOCKS_EN]
set sig_offset 0
set const_offset 0
if {[string equal $device "Arria 10"]} {
set reconfig_avmm_address_width 10
set unused_width_per_lane 88
} elseif {[string equal $device "Stratix 10"]} {
set reconfig_avmm_address_width 11
set unused_width_per_lane 40
} else {
send_message error "Only Arria 10 and Stratix 10 are supported."
}
glue_add_if $num_of_lanes reconfig_clk clock sink true
glue_add_if_port $num_of_lanes reconfig_clk reconfig_clk clk Input 1 true
glue_add_if $num_of_lanes reconfig_reset reset sink true
glue_add_if_port $num_of_lanes reconfig_reset reconfig_reset reset Input 1 true
glue_add_if $num_of_lanes reconfig_avmm avalon sink
for {set i 0} {$i < $num_of_lanes} {incr i} {
set_interface_property reconfig_avmm_${i} associatedClock reconfig_clk
set_interface_property reconfig_avmm_${i} associatedReset reconfig_reset
}
glue_add_if_port $num_of_lanes reconfig_avmm reconfig_address address Input $reconfig_avmm_address_width
glue_add_if_port $num_of_lanes reconfig_avmm reconfig_read read Input 1
glue_add_if_port $num_of_lanes reconfig_avmm reconfig_readdata readdata Output 32
glue_add_if_port $num_of_lanes reconfig_avmm reconfig_waitrequest waitrequest Output 1
glue_add_if_port $num_of_lanes reconfig_avmm reconfig_write write Input 1
glue_add_if_port $num_of_lanes reconfig_avmm reconfig_writedata writedata Input 32
if {[get_parameter TX_OR_RX_N]} {
glue_add_if $num_of_lanes tx_clkout clock source
glue_add_if_port $num_of_lanes tx_clkout tx_clkout clk Output 1
glue_add_if $num_of_lanes tx_coreclkin clock sink true
glue_add_if_port $num_of_lanes tx_coreclkin tx_coreclkin clk Input 1 true
if {$bonding_clocks_en && $num_of_lanes > 6} {
glue_add_if $num_of_lanes tx_bonding_clocks hssi_bonded_clock sink true
glue_add_if_port $num_of_lanes tx_bonding_clocks tx_bonding_clocks clk Input 6 true
} else {
glue_add_tx_serial_clk $num_of_lanes
}
if {$soft_pcs} {
set unused_width [expr $num_of_lanes * $unused_width_per_lane]
glue_add_const_conduit tx_enh_data_valid $num_of_lanes
for {set i 0} {$i < $num_of_lanes} {incr i} {
add_interface tx_raw_data_${i} conduit start
}
glue_add_if_port_conduit $num_of_lanes tx_raw_data raw_data tx_parallel_data Input 40
} else {
set unused_width [expr $num_of_lanes * 92]
for {set i 0} {$i < $num_of_lanes} {incr i} {
add_interface tx_phy_${i} conduit start
}
glue_add_if_port_conduit $num_of_lanes tx_phy char tx_parallel_data Input 32
glue_add_if_port_conduit $num_of_lanes tx_phy charisk tx_datak Input 4
}
glue_add_const_conduit unused_tx_parallel_data $unused_width
add_interface phy_tx_polinv conduit end
add_interface_port phy_tx_polinv polinv tx_polinv Output $num_of_lanes
set_port_property polinv TERMINATION $soft_pcs
} else {
glue_add_if 1 rx_cdr_refclk0 clock sink true
glue_add_if_port 1 rx_cdr_refclk0 rx_cdr_refclk0 clk Input 1 true
glue_add_if $num_of_lanes rx_coreclkin clock sink true
glue_add_if_port $num_of_lanes rx_coreclkin rx_coreclkin clk Input 1 true
glue_add_if $num_of_lanes rx_clkout clock source
glue_add_if_port $num_of_lanes rx_clkout rx_clkout clk Output 1
if {$soft_pcs} {
for {set i 0} {$i < $num_of_lanes} {incr i} {
add_interface rx_raw_data_${i} conduit start
}
glue_add_if_port_conduit $num_of_lanes rx_raw_data raw_data rx_parallel_data Output 40
} else {
for {set i 0} {$i < $num_of_lanes} {incr i} {
add_interface rx_phy_${i} conduit start
}
glue_add_if_port_conduit $num_of_lanes rx_phy char rx_parallel_data Output 32
glue_add_if_port_conduit $num_of_lanes rx_phy charisk rx_datak Output 4
glue_add_if_port_conduit $num_of_lanes rx_phy disperr rx_disperr Output 4
glue_add_if_port_conduit $num_of_lanes rx_phy notintable rx_errdetect Output 4
glue_add_if_port_conduit $num_of_lanes rx_phy patternalign_en rx_std_wa_patternalign Input 1
}
add_interface const_out conduit end
add_interface_port const_out const_out const_out Output 1
set_port_property const_out TERMINATION true
set const_offset 1
add_interface phy_rx_polinv conduit end
add_interface_port phy_rx_polinv polinv rx_polinv Output $num_of_lanes
set_port_property polinv TERMINATION $soft_pcs
}
set_interface_property reconfig_reset associatedClock reconfig_clk
set_interface_property reconfig_reset synchronousEdges DEASSERT
set_parameter_value WIDTH $sig_offset
set_parameter_value CONST_WIDTH $const_offset
}
adi_library/intel/jesd204_phy/jesd204_phy_hw.tcl
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###############################################################################
## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
package require qsys 14.0
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
#
# Instantiates the Arria 10 native PHY and configures it for JESD204 operation.
# The datapath width is configured for 4 octets per beat.
#
# Optionally a soft-logic PCS is instantiated, this can be used if the lane rate
# is too high for the hard-logic PCS.
#
ad_ip_create jesd204_phy "ADI JESD204 PHY"
set_module_property COMPOSITION_CALLBACK jesd204_phy_composition_callback
set_module_property INTERNAL false
# parameters
ad_ip_parameter DEVICE STRING "Stratix 10" false
ad_ip_parameter ID NATURAL 0 false
ad_ip_parameter SOFT_PCS BOOLEAN false false
ad_ip_parameter TX_OR_RX_N BOOLEAN false false
ad_ip_parameter LANE_RATE FLOAT 10000 false
ad_ip_parameter REFCLK_FREQUENCY FLOAT 500.0 false
ad_ip_parameter NUM_OF_LANES POSITIVE 4 false
ad_ip_parameter REGISTER_INPUTS INTEGER 0 false
ad_ip_parameter LANE_INVERT INTEGER 0 false
ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false
proc jesd204_phy_composition_callback {} {
set device [get_parameter_value "DEVICE"]
set soft_pcs [get_parameter_value "SOFT_PCS"]
set tx [get_parameter_value "TX_OR_RX_N"]
set lane_rate [get_parameter_value "LANE_RATE"]
set refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
set id [get_parameter_value "ID"]
set num_of_lanes [get_parameter_value "NUM_OF_LANES"]
set register_inputs [get_parameter_value "REGISTER_INPUTS"]
set lane_invert [get_parameter_value "LANE_INVERT"]
set bonding_clocks_en [get_parameter_value "BONDING_CLOCKS_EN"]
set link_clk_frequency [expr $lane_rate / 40]
if {[string equal $device "Arria 10"]} {
set device_type 1
} elseif {[string equal $device "Stratix 10"]} {
set device_type 2
} else {
set device_type 0
}
add_instance link_clock clock_source
set_instance_parameter_value link_clock {clockFrequency} [expr $link_clk_frequency*1000000]
add_interface link_clk clock sink
set_interface_property link_clk EXPORT_OF link_clock.clk_in
add_interface link_reset reset sink
set_interface_property link_reset EXPORT_OF link_clock.clk_in_reset
## Arria10
if {$device_type == 1} {
add_instance native_phy altera_xcvr_native_a10
set_instance_parameter_value native_phy {enh_txfifo_mode} "Phase compensation"
set_instance_parameter_value native_phy {enh_rxfifo_mode} "Phase compensation"
set_instance_property native_phy SUPPRESS_ALL_WARNINGS true
set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true
## Stratix 10
} elseif {$device_type == 2} {
add_instance native_phy altera_xcvr_native_s10_htile
set_instance_parameter_value native_phy {tx_fifo_mode} "Phase compensation"
set_instance_parameter_value native_phy {rx_fifo_mode} "Phase compensation"
## Unsupported device
} else {
send_message error "Only Arria 10 and Stratix 10 are supported."
}
if {$soft_pcs} {
set_instance_parameter_value native_phy {protocol_mode} "basic_enh"
} else {
set_instance_parameter_value native_phy {protocol_mode} "basic_std"
set_instance_parameter_value native_phy {std_pcs_pma_width} 20
if {$tx} {
set_instance_parameter_value native_phy {std_tx_byte_ser_mode} "Serialize x2"
set_instance_parameter_value native_phy {std_tx_8b10b_enable} 1
set_instance_parameter_value native_phy {std_tx_polinv_enable} 1
set_instance_parameter_value native_phy {enable_port_tx_polinv} 1
} else {
set_instance_parameter_value native_phy {std_rx_byte_deser_mode} "Deserialize x2"
set_instance_parameter_value native_phy {std_rx_8b10b_enable} 1
set_instance_parameter_value native_phy {std_rx_word_aligner_mode} "manual (PLD controlled)"
set_instance_parameter_value native_phy {std_rx_word_aligner_pattern_len} 20
set_instance_parameter_value native_phy {std_rx_word_aligner_pattern} 0xA0D7C
set_instance_parameter_value native_phy {enable_port_rx_std_wa_patternalign} 1
set_instance_parameter_value native_phy {std_rx_polinv_enable} 1
set_instance_parameter_value native_phy {enable_port_rx_polinv} 1
}
}
if {$tx} {
set_instance_parameter_value native_phy {duplex_mode} "tx"
if {$bonding_clocks_en && $num_of_lanes > 6} {
set_instance_parameter_value native_phy {bonded_mode} "pma_only"
} else {
set_instance_parameter_value native_phy {bonded_mode} "not_bonded"
}
set_instance_parameter_value native_phy {enable_port_tx_pma_elecidle} 0
} else {
set_instance_parameter_value native_phy {duplex_mode} "rx"
set_instance_parameter_value native_phy {set_cdr_refclk_freq} $refclk_frequency
set_instance_parameter_value native_phy {enable_port_rx_is_lockedtodata} 1
set_instance_parameter_value native_phy {enable_port_rx_is_lockedtoref} 0
set_instance_parameter_value native_phy {enable_ports_rx_manual_cdr_mode} 0
}
set_instance_parameter_value native_phy {channels} $num_of_lanes
set_instance_parameter_value native_phy {set_data_rate} $lane_rate
set_instance_parameter_value native_phy {enable_simple_interface} 1
set_instance_parameter_value native_phy {enh_pcs_pma_width} 40
set_instance_parameter_value native_phy {enh_pld_pcs_width} 40
set_instance_parameter_value native_phy {rcfg_enable} 1
set_instance_parameter_value native_phy {rcfg_shared} 0
set_instance_parameter_value native_phy {rcfg_jtag_enable} 0
set_instance_parameter_value native_phy {rcfg_sv_file_enable} 0
set_instance_parameter_value native_phy {rcfg_h_file_enable} 0
set_instance_parameter_value native_phy {rcfg_mif_file_enable} 0
set_instance_parameter_value native_phy {set_user_identifier} $id
set_instance_parameter_value native_phy {set_capability_reg_enable} 1
set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1
set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0
add_instance phy_glue jesd204_phy_glue
set_instance_parameter_value phy_glue DEVICE $device
set_instance_parameter_value phy_glue TX_OR_RX_N $tx
set_instance_parameter_value phy_glue SOFT_PCS $soft_pcs
set_instance_parameter_value phy_glue NUM_OF_LANES $num_of_lanes
set_instance_parameter_value phy_glue LANE_INVERT $lane_invert
set_instance_parameter_value phy_glue BONDING_CLOCKS_EN $bonding_clocks_en
add_interface reconfig_clk clock sink
set_interface_property reconfig_clk EXPORT_OF phy_glue.reconfig_clk
add_interface reconfig_reset reset sink
set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset
if {$tx} {
if {$bonding_clocks_en && $num_of_lanes > 6} {
add_interface bonding_clocks hssi_bonded_clock end
set_interface_property bonding_clocks EXPORT_OF phy_glue.tx_bonding_clocks
add_connection phy_glue.phy_tx_bonding_clocks native_phy.tx_bonding_clocks
} else {
add_interface serial_clk_x1 hssi_serial_clock end
set_interface_property serial_clk_x1 EXPORT_OF phy_glue.tx_serial_clk_x1
if {$num_of_lanes > 6} {
add_interface serial_clk_xN hssi_serial_clock end
set_interface_property serial_clk_xN EXPORT_OF phy_glue.tx_serial_clk_xN
}
add_connection phy_glue.phy_tx_serial_clk0 native_phy.tx_serial_clk0
}
add_connection link_clock.clk phy_glue.tx_coreclkin
if { $soft_pcs == true && $device_type == 1 } {
add_connection phy_glue.phy_tx_enh_data_valid native_phy.tx_enh_data_valid
}
foreach x {reconfig_clk reconfig_reset reconfig_avmm tx_coreclkin \
tx_clkout tx_parallel_data unused_tx_parallel_data} {
add_connection phy_glue.phy_${x} native_phy.${x}
}
foreach x {serial_data analogreset digitalreset cal_busy} {
add_interface ${x} conduit end
set_interface_property ${x} EXPORT_OF native_phy.tx_${x}
}
if {$soft_pcs == false} {
add_connection phy_glue.phy_tx_datak native_phy.tx_datak
add_connection phy_glue.phy_tx_polinv native_phy.tx_polinv
}
## Startix 10
if {$device_type == 2} {
foreach x {analogreset_stat digitalreset_stat} {
add_interface ${x} conduit end
set_interface_property ${x} EXPORT_OF native_phy.tx_${x}
}
}
} else {
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF phy_glue.rx_cdr_refclk0
add_connection link_clock.clk phy_glue.rx_coreclkin
foreach x {serial_data analogreset digitalreset cal_busy is_lockedtodata} {
add_interface ${x} conduit end
set_interface_property ${x} EXPORT_OF native_phy.rx_${x}
}
foreach x {reconfig_clk reconfig_reset reconfig_avmm rx_coreclkin \
rx_clkout rx_parallel_data rx_cdr_refclk0} {
add_connection phy_glue.phy_${x} native_phy.${x}
}
if {$soft_pcs == false} {
foreach x {rx_datak rx_disperr rx_errdetect rx_std_wa_patternalign} {
add_connection phy_glue.phy_${x} native_phy.${x}
}
add_connection phy_glue.phy_rx_polinv native_phy.rx_polinv
}
## Startix 10
if {$device_type == 2} {
foreach x {analogreset_stat digitalreset_stat} {
add_interface ${x} conduit end
set_interface_property ${x} EXPORT_OF native_phy.rx_${x}
}
}
}
for {set i 0} {$i < $num_of_lanes} {incr i} {
add_interface reconfig_avmm_${i} avalon slave
set_interface_property reconfig_avmm_${i} EXPORT_OF phy_glue.reconfig_avmm_${i}
add_interface phy_${i} conduit start
if {$tx} {
if {$soft_pcs} {
add_instance soft_pcs_${i} jesd204_soft_pcs_tx
set_instance_parameter_value soft_pcs_${i} INVERT_OUTPUTS \
[expr ($lane_invert >> $i) & 1]
add_connection link_clock.clk soft_pcs_${i}.clock
add_connection link_clock.clk_reset soft_pcs_${i}.reset
add_connection soft_pcs_${i}.tx_raw_data phy_glue.tx_raw_data_${i}
set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.tx_phy
} else {
set_interface_property phy_${i} EXPORT_OF phy_glue.tx_phy_${i}
}
} else {
if {$soft_pcs} {
add_instance soft_pcs_${i} jesd204_soft_pcs_rx
set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs
set_instance_parameter_value soft_pcs_${i} INVERT_INPUTS \
[expr ($lane_invert >> $i) & 1]
add_connection link_clock.clk soft_pcs_${i}.clock
add_connection link_clock.clk_reset soft_pcs_${i}.reset
add_connection phy_glue.rx_raw_data_${i} soft_pcs_${i}.rx_raw_data
set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.rx_phy
} else {
set_interface_property phy_${i} EXPORT_OF phy_glue.rx_phy_${i}
}
}
}
}