initial commit, add dds_par module

2024-01-15 09:36:08 +08:00
commit 315a673005
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+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
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+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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+// including negligence, or under any other theory of
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+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
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+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef if_do_ctrl_v1_0
+`define if_do_ctrl_v1_0
+
+package parameter_structs;
+
+  typedef struct packed {
+      bit    portEnabled;
+      integer    portWidth;
+  }portConfig;
+
+  typedef struct packed {
+    // <typeName> <LogicalName> = {<enablement>, <width>}
+    portConfig request_length;
+    portConfig response_measured_length;
+  }if_do_ctrl_v1_0_port_configuration;
+
+  parameter if_do_ctrl_v1_0_port_configuration if_do_ctrl_v1_0_default_port_configuration = '{request_length:'{1, -1}, response_measured_length:'{1, -1}};
+
+endpackage
+
+interface if_do_ctrl_v1_0 #(parameter_structs::if_do_ctrl_v1_0_port_configuration port_configuration)();
+  logic request_enable;                                                                                  // 
+  logic request_valid;                                                                                   // 
+  logic request_ready;                                                                                   // 
+  logic [port_configuration.request_length.portWidth-1:0] request_length;                                // 
+  logic [port_configuration.response_measured_length.portWidth-1:0] response_measured_length;            // 
+  logic response_eot;                                                                                    // 
+  logic status_underflow;                                                                                // 
+  logic status_overflow;                                                                                 // 
+
+  modport MASTER (
+    input request_ready, response_eot, status_underflow, status_overflow, 
+    output request_enable, request_valid, request_length, response_measured_length
+    );
+
+  modport SLAVE (
+    input request_enable, request_valid, request_length, response_measured_length, 
+    output request_ready, response_eot, status_underflow, status_overflow
+    );
+
+  modport MONITOR (
+    input request_enable, request_valid, request_ready, request_length, response_measured_length, response_eot, status_underflow, status_overflow
+    );
+
+endinterface // if_do_ctrl_v1_0
+
+`endif