initial commit, add dds_par module

adi_library/interfaces/if_gt_qpll_v1_0.sv

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+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
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+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef if_gt_qpll_v1_0
+`define if_gt_qpll_v1_0
+
+interface if_gt_qpll_v1_0();
+  logic qpll_rst;                                        // 
+  logic qpll_ref_clk;                                    // 
+
+  modport MASTER (
+    output qpll_rst, qpll_ref_clk
+    );
+
+  modport SLAVE (
+    input qpll_rst, qpll_ref_clk
+    );
+
+  modport MONITOR (
+    input qpll_rst, qpll_ref_clk
+    );
+
+endinterface // if_gt_qpll_v1_0
+
+`endif