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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
commit 315a673005
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adi_library/jesd204/ad_ip_jesd204_tpl_adc/.lock
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adi_library/jesd204/ad_ip_jesd204_tpl_adc/.timestamp_intel
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adi_library/jesd204/ad_ip_jesd204_tpl_adc/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := ad_ip_jesd204_tpl_adc
GENERIC_DEPS += ../../common/ad_datafmt.v
GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
GENERIC_DEPS += ../../common/ad_pnmon.v
GENERIC_DEPS += ../../common/ad_rst.v
GENERIC_DEPS += ../../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../../common/up_adc_channel.v
GENERIC_DEPS += ../../common/up_adc_common.v
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += ../../common/up_clock_mon.v
GENERIC_DEPS += ../../common/up_xfer_cntrl.v
GENERIC_DEPS += ../../common/up_xfer_status.v
GENERIC_DEPS += ../../common/util_ext_sync.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_deframer.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_pnmon.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_regmap.v
XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v
XILINX_DEPS += ad_ip_jesd204_tpl_adc_ip.tcl
INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_cntrl_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_status_constr.sdc
INTEL_DEPS += ../../jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
INTEL_DEPS += ad_ip_jesd204_tpl_adc_hw.tcl
include ../../scripts/library.mk
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_adc #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 4,
parameter SAMPLES_PER_FRAME = 1,
parameter CONVERTER_RESOLUTION = 14,
parameter BITS_PER_SAMPLE = 16,
parameter DMA_BITS_PER_SAMPLE = 16,
parameter OCTETS_PER_BEAT = 4,
parameter EN_FRAME_ALIGN = 1,
parameter TWOS_COMPLEMENT = 1,
parameter EXT_SYNC = 0,
parameter PN7_ENABLE = 1,
parameter PN15_ENABLE = 1
) (
// jesd interface
// link_clk is (line-rate/40)
input link_clk,
input [OCTETS_PER_BEAT-1:0] link_sof,
input link_valid,
input [NUM_LANES*8*OCTETS_PER_BEAT-1:0] link_data,
output link_ready,
// dma interface
output [NUM_CHANNELS-1:0] enable,
output [NUM_CHANNELS-1:0] adc_valid,
output [DMA_BITS_PER_SAMPLE * OCTETS_PER_BEAT * 8 * NUM_LANES / BITS_PER_SAMPLE-1:0] adc_data,
input adc_dovf,
input adc_sync_in,
output adc_sync_manual_req_out,
input adc_sync_manual_req_in,
output adc_rst,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
output s_axi_awready,
input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
output s_axi_wready,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_bvalid,
input s_axi_bready,
output [1:0] s_axi_bresp,
input s_axi_arvalid,
output s_axi_arready,
input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata
);
// Number of samples per channel that are processed in parallel.
localparam DATA_PATH_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES / NUM_CHANNELS / BITS_PER_SAMPLE;
localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8;
localparam DMA_DATA_WIDTH = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH * NUM_CHANNELS;
localparam BYTES_PER_FRAME = (NUM_CHANNELS * BITS_PER_SAMPLE * SAMPLES_PER_FRAME) / ( 8 * NUM_LANES);
wire [NUM_CHANNELS-1:0] dfmt_enable_s;
wire [NUM_CHANNELS-1:0] dfmt_sign_extend_s;
wire [NUM_CHANNELS-1:0] dfmt_type_s;
wire [NUM_CHANNELS*4-1:0] pn_seq_sel_s;
wire [NUM_CHANNELS-1:0] pn_err_s;
wire [NUM_CHANNELS-1:0] pn_oos_s;
wire adc_rst_sync_s;
wire adc_rst_s;
wire adc_sync;
wire adc_sync_status;
assign adc_rst = adc_rst_s | adc_rst_sync_s;
// regmap
ad_ip_jesd204_tpl_adc_regmap #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_CHANNELS (NUM_CHANNELS),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.NUM_PROFILES(1),
.EXT_SYNC (EXT_SYNC)
) i_regmap (
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awprot (s_axi_awprot),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bready (s_axi_bready),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arprot (s_axi_arprot),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.link_clk (link_clk),
.dfmt_enable (dfmt_enable_s),
.dfmt_sign_extend (dfmt_sign_extend_s),
.dfmt_type (dfmt_type_s),
.pn_seq_sel (pn_seq_sel_s),
.pn_err (pn_err_s),
.pn_oos (pn_oos_s),
.enable (enable),
.adc_sync (adc_sync),
.adc_sync_status (adc_sync_status),
.adc_ext_sync_arm (adc_ext_sync_arm),
.adc_ext_sync_disarm (adc_ext_sync_disarm),
.adc_ext_sync_manual_req (adc_sync_manual_req_out),
.adc_rst (adc_rst_s),
.adc_dovf (adc_dovf),
.jesd_m (NUM_CHANNELS),
.jesd_l (NUM_LANES),
.jesd_s (SAMPLES_PER_FRAME),
.jesd_f (BYTES_PER_FRAME),
.jesd_n (CONVERTER_RESOLUTION),
.jesd_np (BITS_PER_SAMPLE),
.up_profile_sel ());
ad_ip_jesd204_tpl_adc_core #(
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
.EN_FRAME_ALIGN (EN_FRAME_ALIGN),
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.TWOS_COMPLEMENT (TWOS_COMPLEMENT),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
.EXT_SYNC (EXT_SYNC),
.PN7_ENABLE (PN7_ENABLE),
.PN15_ENABLE(PN15_ENABLE)
) i_core (
.clk (link_clk),
.dfmt_enable (dfmt_enable_s),
.dfmt_sign_extend (dfmt_sign_extend_s),
.dfmt_type (dfmt_type_s),
.pn_seq_sel (pn_seq_sel_s),
.pn_err (pn_err_s),
.pn_oos (pn_oos_s),
.link_valid (link_valid),
.link_ready (link_ready),
.link_sof (link_sof),
.link_data (link_data),
.adc_sync (adc_sync),
.adc_sync_status (adc_sync_status),
.adc_sync_in (adc_sync_in),
.adc_ext_sync_arm (adc_ext_sync_arm),
.adc_ext_sync_disarm (adc_ext_sync_disarm),
.adc_sync_manual_req (adc_sync_manual_req_in),
.adc_rst_sync (adc_rst_sync_s),
.adc_valid (adc_valid),
.adc_data (adc_data));
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
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<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
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</Simulator>
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<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
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</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
+98
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@@ -0,0 +1,98 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_adc_channel #(
parameter CONVERTER_RESOLUTION = 14,
parameter DATA_PATH_WIDTH = 2,
parameter TWOS_COMPLEMENT = 1,
parameter BITS_PER_SAMPLE = 16,
parameter PN7_ENABLE = 1,
parameter PN15_ENABLE = 1
) (
input clk,
input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] raw_data,
output [BITS_PER_SAMPLE*DATA_PATH_WIDTH-1:0] fmt_data,
// Configuration and status
input dfmt_enable,
input dfmt_type,
input dfmt_sign_extend,
input [3:0] pn_seq_sel,
output pn_oos,
output pn_err
);
// instantiations
ad_ip_jesd204_tpl_adc_pnmon #(
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.TWOS_COMPLEMENT (TWOS_COMPLEMENT),
.PN7_ENABLE (PN7_ENABLE),
.PN15_ENABLE(PN15_ENABLE)
) i_pnmon (
.clk (clk),
.data (raw_data),
.pn_seq_sel (pn_seq_sel),
.pn_oos (pn_oos),
.pn_err (pn_err));
generate
genvar n;
for (n = 0; n < DATA_PATH_WIDTH; n = n + 1) begin: g_datafmt
ad_datafmt #(
.DATA_WIDTH (CONVERTER_RESOLUTION),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE)
) i_ad_datafmt (
.clk (clk),
.valid (1'b1),
.data (raw_data[n*CONVERTER_RESOLUTION+:CONVERTER_RESOLUTION]),
.valid_out (),
.data_out (fmt_data[n*BITS_PER_SAMPLE+:BITS_PER_SAMPLE]),
.dfmt_enable (dfmt_enable),
.dfmt_type (dfmt_type),
.dfmt_se (dfmt_sign_extend));
end
endgenerate
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
+155
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@@ -0,0 +1,155 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_adc_core #(
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 1,
parameter SAMPLES_PER_FRAME = 1,
parameter CONVERTER_RESOLUTION = 14,
parameter BITS_PER_SAMPLE = 16,
parameter DMA_BITS_PER_SAMPLE = 16,
parameter OCTETS_PER_BEAT = 4,
parameter EN_FRAME_ALIGN = 0,
parameter DATA_PATH_WIDTH = 1,
parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * DMA_BITS_PER_SAMPLE * NUM_CHANNELS,
parameter TWOS_COMPLEMENT = 1,
parameter EXT_SYNC = 0,
parameter PN7_ENABLE = 1,
parameter PN15_ENABLE = 1
) (
input clk,
input [NUM_CHANNELS-1:0] dfmt_enable,
input [NUM_CHANNELS-1:0] dfmt_sign_extend,
input [NUM_CHANNELS-1:0] dfmt_type,
input [NUM_CHANNELS*4-1:0] pn_seq_sel,
output [NUM_CHANNELS-1:0] pn_err,
output [NUM_CHANNELS-1:0] pn_oos,
output [NUM_CHANNELS-1:0] adc_valid,
output [DMA_DATA_WIDTH-1:0] adc_data,
input adc_sync,
output adc_sync_status,
input adc_ext_sync_arm,
input adc_ext_sync_disarm,
input adc_sync_in,
input adc_sync_manual_req,
output adc_rst_sync,
input link_valid,
output link_ready,
input [OCTETS_PER_BEAT-1:0] link_sof,
input [LINK_DATA_WIDTH-1:0] link_data
);
// Raw and formatted channel data widths
localparam CDW_RAW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH;
localparam ADC_DATA_WIDTH = CDW_RAW * NUM_CHANNELS;
localparam CDW_FMT = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH;
wire [ADC_DATA_WIDTH-1:0] raw_data_s;
wire link_valid_tmp;
reg link_valid_d = 1'b0;
reg link_valid_dd = 1'b0;
assign link_ready = 1'b1;
assign link_valid_tmp = EN_FRAME_ALIGN ? link_valid_dd : link_valid_d;
assign adc_valid = {NUM_CHANNELS{link_valid_tmp & ~adc_sync_armed}};
assign adc_sync_status = adc_sync_armed;
assign adc_rst_sync = adc_sync_armed;
always @(posedge clk) begin
link_valid_d <= link_valid;
link_valid_dd <= link_valid_d;
end
// synchronization logic
util_ext_sync #(
.ENABLED (EXT_SYNC)
) i_util_ext_sync (
.clk (clk),
.ext_sync_arm (adc_ext_sync_arm),
.ext_sync_disarm (adc_ext_sync_disarm),
.sync_in (adc_sync_in | adc_sync_manual_req),
.sync_armed (adc_sync_armed));
ad_ip_jesd204_tpl_adc_deframer #(
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
.EN_FRAME_ALIGN (EN_FRAME_ALIGN),
.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
.ADC_DATA_WIDTH (ADC_DATA_WIDTH)
) i_deframer (
.clk (clk),
.link_sof (link_sof),
.link_data (link_data),
.adc_data (raw_data_s));
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
ad_ip_jesd204_tpl_adc_channel #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.TWOS_COMPLEMENT (TWOS_COMPLEMENT),
.BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
.PN7_ENABLE (PN7_ENABLE),
.PN15_ENABLE(PN15_ENABLE)
) i_channel (
.clk (clk),
.raw_data (raw_data_s[CDW_RAW*i+:CDW_RAW]),
.fmt_data (adc_data[CDW_FMT*i+:CDW_FMT]),
.dfmt_enable (dfmt_enable[i]),
.dfmt_sign_extend (dfmt_sign_extend[i]),
.dfmt_type (dfmt_type[i]),
.pn_seq_sel (pn_seq_sel[i*4+:4]),
.pn_err (pn_err[i]),
.pn_oos (pn_oos[i]));
end
endgenerate
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
+133
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@@ -0,0 +1,133 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_adc_deframer #(
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 4,
parameter BITS_PER_SAMPLE = 16,
parameter CONVERTER_RESOLUTION = 14,
parameter SAMPLES_PER_FRAME = 1,
parameter OCTETS_PER_BEAT = 8,
parameter EN_FRAME_ALIGN = 0,
parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
parameter ADC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
) (
// jesd interface
// clk is (line-rate/40)
input clk,
input [OCTETS_PER_BEAT-1:0] link_sof,
input [LINK_DATA_WIDTH-1:0] link_data,
// adc data output
output [ADC_DATA_WIDTH-1:0] adc_data
);
localparam SAMPLES_PER_BEAT = ADC_DATA_WIDTH / CONVERTER_RESOLUTION;
localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME;
localparam BITS_PER_LANE_PER_FRAME = BITS_PER_CHANNEL_PER_FRAME *
NUM_CHANNELS / NUM_LANES;
localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME;
wire [LINK_DATA_WIDTH-1:0] link_data_s;
wire [LINK_DATA_WIDTH-1:0] link_data_msb_s;
wire [LINK_DATA_WIDTH-1:0] frame_data_s;
wire [LINK_DATA_WIDTH-1:0] adc_data_msb;
// data multiplex
genvar i;
genvar j;
generate
/* Reorder octets MSB first */
for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_adc_data
assign link_data_msb_s[i+:8] = link_data_s[LINK_DATA_WIDTH-1-i-:8];
end
/* Slice lanes into frames */
ad_perfect_shuffle #(
.NUM_GROUPS (NUM_LANES),
.WORDS_PER_GROUP (FRAMES_PER_BEAT),
.WORD_WIDTH (BITS_PER_LANE_PER_FRAME)
) i_lanes_to_frames (
.data_in (link_data_msb_s),
.data_out (frame_data_s));
/* Slice frames into channels */
ad_perfect_shuffle #(
.NUM_GROUPS (FRAMES_PER_BEAT),
.WORDS_PER_GROUP (NUM_CHANNELS),
.WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME)
) i_frames_to_channels (
.data_in (frame_data_s),
.data_out (adc_data_msb));
/* Reorder samples LSB first and remove tail bits */
for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin: g_dac_data_msb
localparam src_w = BITS_PER_SAMPLE;
localparam dst_w = CONVERTER_RESOLUTION;
localparam src_msb = LINK_DATA_WIDTH - 1 - i * src_w ;
localparam dst_lsb = i * dst_w;
assign adc_data[dst_lsb+:dst_w] = adc_data_msb[src_msb-:dst_w];
end
endgenerate
// frame-alignment
generate
genvar n;
if (EN_FRAME_ALIGN) begin
for (n = 0; n < NUM_LANES; n = n + 1) begin: g_xcvr_if
localparam DW = OCTETS_PER_BEAT * 8;
ad_xcvr_rx_if #(
.OCTETS_PER_BEAT (OCTETS_PER_BEAT)
) i_xcvr_if (
.rx_clk (clk),
.rx_ip_sof (link_sof),
.rx_ip_data (link_data[n*DW+:DW]),
.rx_sof (),
.rx_data (link_data_s[n*DW+:DW]));
end
end else begin
assign link_data_s = link_data;
end
endgenerate
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
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###############################################################################
## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
package require qsys 14.0
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create ad_ip_jesd204_tpl_adc "JESD204 Transport Layer for ADCs" p_ad_ip_jesd204_tpl_adc_elab
set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_adc_validate
ad_ip_files ad_ip_jesd204_tpl_adc [list \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
$ad_hdl_dir/library/common/ad_pnmon.v \
$ad_hdl_dir/library/common/ad_datafmt.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
$ad_hdl_dir/library/common/up_xfer_status.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/common/up_adc_common.v \
$ad_hdl_dir/library/common/up_adc_channel.v \
$ad_hdl_dir/library/common/util_ext_sync.v \
$ad_hdl_dir/library/common/ad_xcvr_rx_if.v \
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v \
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v \
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v \
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v \
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v \
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v \
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v \
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc]
# parameters
set group "General Configuration"
ad_ip_parameter ID INTEGER 0 true [list \
DISPLAY_NAME "Core ID" \
GROUP $group \
]
ad_ip_parameter OCTETS_PER_BEAT INTEGER 4 true [list \
DISPLAY_NAME "Datapath width" \
DISPLAY_UNITS "octets" \
ALLOWED_RANGES {4 6 8 12} \
GROUP $group \
]
set group "JESD204 Deframer Configuration"
ad_ip_parameter NUM_LANES INTEGER 1 true [list \
DISPLAY_NAME "Number of Lanes (L)" \
DISPLAY_UNITS "lanes" \
ALLOWED_RANGES {1 2 3 4 8 16 24 32} \
GROUP $group \
]
ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \
DISPLAY_NAME "Number of Converters (M)" \
DISPLAY_UNITS "converters" \
ALLOWED_RANGES {1 2 4 6 8 16 32 64} \
GROUP $group \
]
ad_ip_parameter BITS_PER_SAMPLE INTEGER 16 true [list \
DISPLAY_NAME "Bits per Sample (N')" \
ALLOWED_RANGES {8 12 16} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter DMA_BITS_PER_SAMPLE INTEGER 16 true [list \
DISPLAY_NAME "DMA Bits per Sample" \
ALLOWED_RANGES {8 16} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter CONVERTER_RESOLUTION INTEGER 16 true [list \
DISPLAY_NAME "Converter Resolution (N)" \
ALLOWED_RANGES {8 11 12 14 16} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter ENABLE_SAMPLES_PER_FRAME_MANUAL BOOLEAN 0 false [list \
DISPLAY_NAME "Manual Samples per Frame" \
GROUP $group \
]
ad_ip_parameter SAMPLES_PER_FRAME INTEGER 1 true [list \
DISPLAY_NAME "Samples per Frame (S)" \
DISPLAY_UNITS "samples" \
ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
DERIVED true \
GROUP $group \
]
ad_ip_parameter SAMPLES_PER_FRAME_MANUAL INTEGER 1 false [list \
DISPLAY_NAME "Samples per Frame (S)" \
DISPLAY_UNITS "samples" \
ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
VISIBLE false \
GROUP $group \
]
ad_ip_parameter OCTETS_PER_FRAME INTEGER 1 false [list \
DISPLAY_NAME "Octets per Frame (F)" \
DISPLAY_UNITS "octets" \
ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
DERIVED true \
GROUP $group \
]
set group "Deframer Output Information"
# Parameters in this group are informative only and can be read back after the
# core has been configured to find out the expected layout of the input data.
# E.g.
# set NUM_OF_CHANNELS [get_instance_parameter_value jesd204_transport NUM_CHANNELS]
# set CHANNEL_DATA_WIDTH [get_instance_parameter_value jesd204_transport CHANNEL_DATA_WIDTH]
#
# add_instance util_adc_cpack util_cpack
# set_instance_parameter_values util_adc_cpack [list \
# CHANNEL_DATA_WIDTH $CHANNEL_DATA_WIDTH \
# NUM_OF_CHANNELS $NUM_OF_CHANNELS \
# ]
ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 false [list \
DISPLAY_NAME "Samples per Channel per Beat" \
DERIVED true \
GROUP $group \
]
ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 1 false [list \
DISPLAY_NAME "Channel Data Width" \
UNITS bits \
DERIVED true \
GROUP $group \
]
set group "Datapath Configuration"
ad_ip_parameter TWOS_COMPLEMENT boolean 1 true [list \
DISPLAY_NAME "Twos Complement" \
GROUP $group \
]
ad_ip_parameter PN7_ENABLE boolean 1 true [list \
DISPLAY_NAME "Enable PN7" \
GROUP $group \
]
ad_ip_parameter PN15_ENABLE boolean 1 true [list \
DISPLAY_NAME "Enable PN15" \
GROUP $group \
]
# axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
# core clock and start of frame
add_interface link_clk clock end
add_interface_port link_clk link_clk clk Input 1
ad_interface signal link_sof input 4 export
# We don't expect too large values for a and b, trivial implementation will do
proc gcd {a b} {
if {$a == $b} {
return $b
} elseif {$a > $b} {
return [gcd [expr $a - $b] $b]
} else {
return [gcd $a [expr $b - $a]]
}
}
# validate
proc p_ad_ip_jesd204_tpl_adc_validate {} {
set L [get_parameter_value "NUM_LANES"]
set M [get_parameter_value "NUM_CHANNELS"]
set NP [get_parameter_value "BITS_PER_SAMPLE"]
set N [get_parameter_value "CONVERTER_RESOLUTION"]
set S_manual [get_parameter_value "SAMPLES_PER_FRAME_MANUAL"]
set enable_S_manual [get_parameter_value "ENABLE_SAMPLES_PER_FRAME_MANUAL"]
# With fixed values for M, L and N' all valid values for S and F have a
# constant ratio of S / F. Choose a ratio so that S and F are co-prime.
# Choosing values for F and S that have a common factor has higher latency
# and no added benefits.
#
# Since converters often support those higher latency modes still allow a
# manual override of the S parameter in case somebody wants to use those modes
# anyway.
#
# To be able to set samples per frame manually ENABLE_SAMPLES_PER_FRAME_MANUAL
# needs to be set to true and SAMPLES_PER_FRAME_MANUAL to the desired value.
#
# When manual sample per frame selection is enabled still verify that the
# selected value is valid.
set S_min [expr $L * 8]
set F_min [expr $M * $NP]
set common_factor [gcd $S_min $F_min]
set S_min [expr $S_min / $common_factor]
set F_min [expr $F_min / $common_factor]
if {$enable_S_manual} {
if {$S_manual % $S_min != 0} {
send_message ERROR "For framer configuration (L=$L, M=$M, NP=$NP) samples per frame (S) must be an integer multiple of $S_min"
set S $S_min
set F $F_min
} else {
set S $S_manual
set F [expr $S_manual * $M * $NP / $L / 8]
}
} else {
set S $S_min
set F $F_min
}
set_parameter_value OCTETS_PER_FRAME $F
set_parameter_value SAMPLES_PER_FRAME $S
set_parameter_property SAMPLES_PER_FRAME VISIBLE [expr !$enable_S_manual]
set_parameter_property SAMPLES_PER_FRAME_MANUAL VISIBLE $enable_S_manual
set_parameter_value SAMPLES_PER_CHANNEL [expr 4 * $S / $F]
set_parameter_value CHANNEL_DATA_WIDTH [expr 16 * (4 * $S / $F)]
}
# elaborate
proc p_ad_ip_jesd204_tpl_adc_elab {} {
# read core parameters
set L [get_parameter_value "NUM_LANES"]
set M [get_parameter_value "NUM_CHANNELS"]
set NP [get_parameter_value "BITS_PER_SAMPLE"]
set OPB [get_parameter_value "OCTETS_PER_BEAT"]
set DMA_BPS [get_parameter_value "DMA_BITS_PER_SAMPLE"]
# The DMA interface is rounded to nearest power of two bytes per sample,
# e.g NP=12 is padded into 16 bits
set samples_per_beat_per_channel [expr ($OPB * 8 * $L / ($M * $NP))]
set channel_bus_width [expr $samples_per_beat_per_channel*$DMA_BPS]
# link layer interface
add_interface link_data avalon_streaming sink
add_interface_port link_data link_data data input [expr $OPB*8*$L]
add_interface_port link_data link_valid valid input 1
add_interface_port link_data link_ready ready output 1
set_interface_property link_data associatedClock link_clk
set_interface_property link_data dataBitsPerSymbol [expr $OPB*8*$L]
# dma interface
for {set i 0} {$i < $M} {incr i} {
add_interface adc_ch_$i conduit end
add_interface_port adc_ch_$i adc_enable_$i enable output 1
set_port_property adc_enable_$i fragment_list [format "enable(%d:%d)" $i $i]
add_interface_port adc_ch_$i adc_valid_$i valid output 1
set_port_property adc_valid_$i fragment_list [format "adc_valid(%d:%d)" $i $i]
add_interface_port adc_ch_$i adc_data_$i data output $channel_bus_width
set_port_property adc_data_$i fragment_list \
[format "adc_data(%d:%d)" [expr $channel_bus_width*$i+$channel_bus_width-1] [expr $channel_bus_width*$i]]
set_interface_property adc_ch_$i associatedClock link_clk
}
ad_interface signal adc_dovf input 1 ovf
}
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
+135
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###############################################################################
## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create ad_ip_jesd204_tpl_adc
adi_ip_files ad_ip_jesd204_tpl_adc [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/util_ext_sync.v" \
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"../ad_ip_jesd204_tpl_common/up_tpl_common.v" \
"ad_ip_jesd204_tpl_adc_core.v" \
"ad_ip_jesd204_tpl_adc_channel.v" \
"ad_ip_jesd204_tpl_adc_deframer.v" \
"ad_ip_jesd204_tpl_adc_pnmon.v" \
"ad_ip_jesd204_tpl_adc_regmap.v" \
"ad_ip_jesd204_tpl_adc.v" \
]
adi_ip_properties ad_ip_jesd204_tpl_adc
adi_init_bd_tcl
adi_ip_bd ad_ip_jesd204_tpl_adc "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_adc} [ipx::current_core]
set cc [ipx::current_core]
set_property display_name "JESD204 Transport Layer for ADCs" $cc
set_property description "JESD204 Transport Layer for ADCs" $cc
adi_add_bus "link" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list \
{"link_ready" "TREADY"} \
{"link_valid" "TVALID"} \
{"link_data" "TDATA"} \
]
adi_add_bus_clock "link_clk" "link"
adi_set_ports_dependency "adc_sync_in" "EXT_SYNC == 1"
adi_set_ports_dependency "adc_sync_manual_req_out" "EXT_SYNC == 1"
adi_set_ports_dependency "adc_sync_manual_req_in" "EXT_SYNC == 1"
foreach {p v} {
"NUM_LANES" "1 2 3 4 6 8 12 16 24 32" \
"NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
"BITS_PER_SAMPLE" "8 12 16" \
"DMA_BITS_PER_SAMPLE" "8 12 16" \
"CONVERTER_RESOLUTION" "8 11 12 14 16" \
"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
"OCTETS_PER_BEAT" "4 6 8 12 16 32 64" \
} { \
set_property -dict [list \
"value_validation_type" "list" \
"value_validation_list" $v \
] [ipx::get_user_parameters $p -of_objects $cc]
}
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
-parent $page0 -display_name "General Configuration"]
set p [ipgui::get_guiparamspec -name "ID" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $general_group
set_property -dict [list \
"display_name" "Core ID" \
] $p
set framer_group [ipgui::add_group -name "JESD204 Deframer Configuration" -component $cc \
-parent $page0 -display_name "JESD204 Deframer Cofiguration"]
set i 0
foreach {k v} { \
"NUM_LANES" "Number of Lanes (L)" \
"NUM_CHANNELS" "Number of Conveters (M)" \
"BITS_PER_SAMPLE" "Bits per Sample (N')" \
"DMA_BITS_PER_SAMPLE" "DMA Bits per Sample" \
"CONVERTER_RESOLUTION" "Converter Resolution (N)" \
"SAMPLES_PER_FRAME" "Samples per Frame (S)" \
"OCTETS_PER_BEAT" "Octets per Beat" \
} { \
set p [ipgui::get_guiparamspec -name $k -component $cc]
ipgui::move_param -component $cc -order $i $p -parent $framer_group
set_property -dict [list \
WIDGET "comboBox" \
DISPLAY_NAME $v \
] $p
incr i
}
set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \
-parent $page0 -display_name "Datapath Cofiguration"]
set i 0
foreach {k v w} {
"TWOS_COMPLEMENT" "Use twos complement" "checkBox" \
"EXT_SYNC" "Enable external sync" "checkBox" \
"PN7_ENABLE" "Enable PN7" "checkBox" \
"PN15_ENABLE" "Enable PN15" "checkBox" \
} { \
set p [ipgui::get_guiparamspec -name $k -component $cc]
ipgui::move_param -component $cc -order $i $p -parent $datapath_group
set_property -dict [list \
WIDGET $w \
DISPLAY_NAME $v \
] $p
incr i
}
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
+162
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_adc_pnmon #(
parameter CONVERTER_RESOLUTION = 16,
parameter DATA_PATH_WIDTH = 1,
parameter TWOS_COMPLEMENT = 1,
parameter PN7_ENABLE = 1,
parameter PN15_ENABLE = 1
) (
input clk,
// data interface
input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] data,
// pn out of sync and error
output pn_oos,
output pn_err,
// processor interface PN9 (0x0), PN23 (0x1), PN7 (0x4), PN15 (0x5)
input [3:0] pn_seq_sel
);
localparam DW = DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1;
// Max width of largest PN and data width
localparam PN_W = DW > 22 ? DW : 22;
// internal registers
reg [PN_W:0] pn_data_pn = 'd0;
// internal signals
wire [PN_W:0] pn_data_pn_s;
wire [DW:0] pn_data_in_s;
wire [PN_W:0] pn_data_init;
wire [DW:0] pn23;
wire [DW+23:0] full_state_pn23;
wire [DW:0] pn9;
wire [DW+9:0] full_state_pn9;
wire [DW:0] pn7;
wire [DW+7:0] full_state_pn7;
wire [DW:0] pn15;
wire [DW+15:0] full_state_pn15;
// pn sequence select
generate if (PN_W > DW) begin
reg [PN_W-DW-1:0] pn_data_in_d = 'd0;
always @(posedge clk) begin
pn_data_in_d <= pn_data_in_s[PN_W-DW-1:0];
end
assign pn_data_init = {pn_data_in_d, pn_data_in_s};
end else begin
assign pn_data_init = pn_data_in_s;
end
endgenerate
assign pn_data_pn_s = (pn_oos == 1'b1) ? pn_data_init : pn_data_pn;
wire tc = TWOS_COMPLEMENT ? 1'b1 : 1'b0;
generate
genvar i;
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_pn_swizzle
localparam src_lsb = i * CONVERTER_RESOLUTION;
localparam src_msb = src_lsb + CONVERTER_RESOLUTION - 1;
localparam dst_lsb = (DATA_PATH_WIDTH - i - 1) * CONVERTER_RESOLUTION;
localparam dst_msb = dst_lsb + CONVERTER_RESOLUTION - 1;
assign pn_data_in_s[dst_msb] = (~tc) ^ data[src_msb];
assign pn_data_in_s[dst_msb-1:dst_lsb] = data[src_msb-1:src_lsb];
end
endgenerate
// PN23 x^23 + x^18 + 1
assign pn23 = full_state_pn23[23+:DW+1] ^ full_state_pn23[18+:DW+1];
assign full_state_pn23 = {pn_data_pn_s[22:0],pn23};
// PN9 x^9 + x^5 + 1
assign pn9 = full_state_pn9[9+:DW+1] ^ full_state_pn9[5+:DW+1];
assign full_state_pn9 = {pn_data_pn_s[8:0],pn9};
always @(posedge clk) begin
if (pn_seq_sel == 4'd0) begin
pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn9} : pn9;
end else if (pn_seq_sel == 4'd1) begin
pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn23} : pn23;
end else if (pn_seq_sel == 4'd4) begin
pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn7} : pn7;
end else if (pn_seq_sel == 4'd5) begin
pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn15} : pn15;
end
end
// specific PN sequences
generate
if(PN7_ENABLE == 'b1) begin
// PN7 x^7 + x^6 + 1
assign pn7 = full_state_pn7[7+:DW+1] ^ full_state_pn7[6+:DW+1];
assign full_state_pn7 = {pn_data_pn_s[6:0],pn7};
end else begin
assign pn7 = 'd0;
assign full_state_pn7 = 'd0;
end
if(PN15_ENABLE == 'b1) begin
// PN15 x^15 + x^14 + 1
assign pn15 = full_state_pn15[15+:DW+1] ^ full_state_pn15[14+:DW+1];
assign full_state_pn15 = {pn_data_pn_s[14:0],pn15};
end else begin
assign pn15 = 'd0;
assign full_state_pn15 = 'd0;
end
endgenerate
// pn oos & pn err
ad_pnmon #(
.DATA_WIDTH (DW+1)
) i_pnmon (
.adc_clk (clk),
.adc_valid_in (1'b1),
.adc_data_in (pn_data_in_s),
.adc_data_pn (pn_data_pn[DW:0]),
.adc_pn_oos (pn_oos),
.adc_pn_err (pn_err));
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
+366
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@@ -0,0 +1,366 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_adc_regmap #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter NUM_CHANNELS = 1,
parameter DATA_PATH_WIDTH = 1,
parameter NUM_PROFILES = 1, // Number of supported JESD profiles
parameter EXT_SYNC = 0
) (
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
// control interface
input link_clk,
// Data format conversion configuration
output [NUM_CHANNELS-1:0] dfmt_enable,
output [NUM_CHANNELS-1:0] dfmt_sign_extend,
output [NUM_CHANNELS-1:0] dfmt_type,
// PN sequence monitor
output [NUM_CHANNELS*4-1:0] pn_seq_sel,
input [NUM_CHANNELS-1:0] pn_err,
input [NUM_CHANNELS-1:0] pn_oos,
output [NUM_CHANNELS-1:0] enable,
input adc_sync_status,
output adc_sync,
output adc_ext_sync_arm,
output adc_ext_sync_disarm,
output adc_ext_sync_manual_req,
output adc_rst,
// Underflow
input adc_dovf,
// Deframer interface
input [NUM_PROFILES*8-1: 0] jesd_m,
input [NUM_PROFILES*8-1: 0] jesd_l,
input [NUM_PROFILES*8-1: 0] jesd_s,
input [NUM_PROFILES*8-1: 0] jesd_f,
input [NUM_PROFILES*8-1: 0] jesd_n,
input [NUM_PROFILES*8-1: 0] jesd_np,
output [$clog2(NUM_PROFILES):0] up_profile_sel
);
localparam [31:0] CLK_RATIO = DATA_PATH_WIDTH;
reg up_rack = 1'b0;
reg up_wack = 1'b0;
reg [31:0] up_rdata = 32'h00;
reg [31:0] up_rdata_all;
reg up_status_pn_err = 1'b0;
reg up_status_pn_oos = 1'b0;
reg adc_status = 1'b0;
// internal clocks & resets
wire up_clk;
wire up_rstn;
wire up_wreq_s;
wire [10:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [NUM_CHANNELS+1:0] up_wack_s;
wire up_rreq_s;
wire [10:0] up_raddr_s;
wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
wire [NUM_CHANNELS+1:0] up_rack_s;
wire [NUM_CHANNELS-1:0] up_adc_pn_err_s;
wire [NUM_CHANNELS-1:0] up_adc_pn_oos_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// status
always @(posedge link_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
// up bus interface
up_axi #(
.AXI_ADDRESS_WIDTH (13)
) i_up_axi (
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr ({3'b0,s_axi_awaddr}),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr ({3'b0,s_axi_araddr}),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
integer n;
always @(*) begin
up_rdata_all = 'h00;
for (n = 0; n <= NUM_CHANNELS+1; n = n + 1) begin
up_rdata_all = up_rdata_all | up_rdata_s[n];
end
end
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= |up_adc_pn_err_s;
up_status_pn_oos <= |up_adc_pn_oos_s;
up_rdata <= up_rdata_all;
up_rack <= |up_rack_s;
up_wack <= |up_wack_s;
end
end
// common processor control
//
localparam CONFIG = (EXT_SYNC << 12);
up_adc_common #(
.COMMON_ID (6'h0),
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DRP_DISABLE (1),
.USERPORTS_DISABLE (1),
.GPIO_DISABLE (1),
.START_CODE_DISABLE (1),
.CONFIG (CONFIG)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (link_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status),
.adc_sync_status (adc_sync_status),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (CLK_RATIO),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (adc_sync),
.adc_ext_sync_arm (adc_ext_sync_arm),
.adc_ext_sync_disarm (adc_ext_sync_disarm),
.adc_ext_sync_manual_req (adc_ext_sync_manual_req),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (1'b0),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.adc_config_wr (),
.adc_config_ctrl (),
.adc_config_rd ('d0),
.adc_ctrl_status ('d0),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (NUM_CHANNELS),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_adc_ce (),
.up_pps_rcounter (32'd0),
.up_pps_status (1'b0),
.up_pps_irq_mask (),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
up_adc_channel #(
.COMMON_ID (6'h1 + i/16),
.CHANNEL_ID (i % 16),
.USERPORTS_DISABLE (1),
.DCFILTER_DISABLE (1),
.IQCORRECTION_DISABLE (1)
) i_up_adc_channel (
.adc_clk (link_clk),
.adc_rst (adc_rst),
.adc_enable (enable[i]),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_enable (dfmt_enable[i]),
.adc_dfmt_se (dfmt_sign_extend[i]),
.adc_dfmt_type (dfmt_type[i]),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (pn_seq_sel[i*4+:4]),
.adc_data_sel (),
.adc_pn_err (pn_err[i]),
.adc_pn_oos (pn_oos[i]),
.adc_or (1'b0),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_adc_pn_err (up_adc_pn_err_s[i]),
.up_adc_pn_oos (up_adc_pn_oos_s[i]),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i+1]),
.up_rreq (up_rreq_s),
.up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[i+1]),
.up_rack (up_rack_s[i+1]));
end
endgenerate
up_tpl_common #(
.COMMON_ID(2'h0), // Offset of regmap
.NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles
) i_up_tpl_adc (
.jesd_m (jesd_m),
.jesd_l (jesd_l),
.jesd_s (jesd_s),
.jesd_f (jesd_f),
.jesd_n (jesd_n),
.jesd_np (jesd_np),
.up_profile_sel (up_profile_sel),
// bus interface
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[NUM_CHANNELS+1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[NUM_CHANNELS+1]),
.up_rack (up_rack_s[NUM_CHANNELS+1]));
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_adc/bd/bd.tcl
+47
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# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
DEV_PACKAGE \
SPEED_GRADE \
FPGA_FAMILY \
FPGA_TECHNOLOGY"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
adi_library/jesd204/ad_ip_jesd204_tpl_adc/component.xml
+1450
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adi_library/jesd204/ad_ip_jesd204_tpl_adc/temporary_case_dependencies.mk
+2
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CLEAN_TARGET += bd
CLEAN_TARGET += temporary_case_dependencies.mk
adi_library/jesd204/ad_ip_jesd204_tpl_adc/xgui/ad_ip_jesd204_tpl_adc_v1_0.tcl
+277
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "EN_FRAME_ALIGN" -parent ${Page_0}
#Adding Group
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}]
ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}
#Adding Group
set JESD204_Deframer_Configuration [ipgui::add_group $IPINST -name "JESD204 Deframer Configuration" -parent ${Page_0} -display_name {JESD204 Deframer Cofiguration}]
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${JESD204_Deframer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "NUM_CHANNELS" -parent ${JESD204_Deframer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "BITS_PER_SAMPLE" -parent ${JESD204_Deframer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "DMA_BITS_PER_SAMPLE" -parent ${JESD204_Deframer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "CONVERTER_RESOLUTION" -parent ${JESD204_Deframer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "SAMPLES_PER_FRAME" -parent ${JESD204_Deframer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "OCTETS_PER_BEAT" -parent ${JESD204_Deframer_Configuration} -widget comboBox
#Adding Group
set Datapath_Configuration [ipgui::add_group $IPINST -name "Datapath Configuration" -parent ${Page_0} -display_name {Datapath Cofiguration}]
ipgui::add_param $IPINST -name "TWOS_COMPLEMENT" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "EXT_SYNC" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "PN7_ENABLE" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "PN15_ENABLE" -parent ${Datapath_Configuration} -widget checkBox
#Adding Group
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
}
proc update_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
# Procedure called to update BITS_PER_SAMPLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
# Procedure called to validate BITS_PER_SAMPLE
return true
}
proc update_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
# Procedure called to update CONVERTER_RESOLUTION when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
# Procedure called to validate CONVERTER_RESOLUTION
return true
}
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to validate DEV_PACKAGE
return true
}
proc update_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } {
# Procedure called to update DMA_BITS_PER_SAMPLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } {
# Procedure called to validate DMA_BITS_PER_SAMPLE
return true
}
proc update_PARAM_VALUE.EN_FRAME_ALIGN { PARAM_VALUE.EN_FRAME_ALIGN } {
# Procedure called to update EN_FRAME_ALIGN when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.EN_FRAME_ALIGN { PARAM_VALUE.EN_FRAME_ALIGN } {
# Procedure called to validate EN_FRAME_ALIGN
return true
}
proc update_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } {
# Procedure called to update EXT_SYNC when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } {
# Procedure called to validate EXT_SYNC
return true
}
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to validate FPGA_FAMILY
return true
}
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to validate FPGA_TECHNOLOGY
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
# Procedure called to update NUM_CHANNELS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
# Procedure called to validate NUM_CHANNELS
return true
}
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to validate NUM_LANES
return true
}
proc update_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
# Procedure called to update OCTETS_PER_BEAT when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
# Procedure called to validate OCTETS_PER_BEAT
return true
}
proc update_PARAM_VALUE.PN15_ENABLE { PARAM_VALUE.PN15_ENABLE } {
# Procedure called to update PN15_ENABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PN15_ENABLE { PARAM_VALUE.PN15_ENABLE } {
# Procedure called to validate PN15_ENABLE
return true
}
proc update_PARAM_VALUE.PN7_ENABLE { PARAM_VALUE.PN7_ENABLE } {
# Procedure called to update PN7_ENABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PN7_ENABLE { PARAM_VALUE.PN7_ENABLE } {
# Procedure called to validate PN7_ENABLE
return true
}
proc update_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
# Procedure called to update SAMPLES_PER_FRAME when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
# Procedure called to validate SAMPLES_PER_FRAME
return true
}
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to validate SPEED_GRADE
return true
}
proc update_PARAM_VALUE.TWOS_COMPLEMENT { PARAM_VALUE.TWOS_COMPLEMENT } {
# Procedure called to update TWOS_COMPLEMENT when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TWOS_COMPLEMENT { PARAM_VALUE.TWOS_COMPLEMENT } {
# Procedure called to validate TWOS_COMPLEMENT
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
}
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
}
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
}
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
}
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
}
proc update_MODELPARAM_VALUE.NUM_CHANNELS { MODELPARAM_VALUE.NUM_CHANNELS PARAM_VALUE.NUM_CHANNELS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_CHANNELS}] ${MODELPARAM_VALUE.NUM_CHANNELS}
}
proc update_MODELPARAM_VALUE.SAMPLES_PER_FRAME { MODELPARAM_VALUE.SAMPLES_PER_FRAME PARAM_VALUE.SAMPLES_PER_FRAME } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_FRAME}] ${MODELPARAM_VALUE.SAMPLES_PER_FRAME}
}
proc update_MODELPARAM_VALUE.CONVERTER_RESOLUTION { MODELPARAM_VALUE.CONVERTER_RESOLUTION PARAM_VALUE.CONVERTER_RESOLUTION } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CONVERTER_RESOLUTION}] ${MODELPARAM_VALUE.CONVERTER_RESOLUTION}
}
proc update_MODELPARAM_VALUE.BITS_PER_SAMPLE { MODELPARAM_VALUE.BITS_PER_SAMPLE PARAM_VALUE.BITS_PER_SAMPLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.BITS_PER_SAMPLE}
}
proc update_MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE { MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE PARAM_VALUE.DMA_BITS_PER_SAMPLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DMA_BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE}
}
proc update_MODELPARAM_VALUE.OCTETS_PER_BEAT { MODELPARAM_VALUE.OCTETS_PER_BEAT PARAM_VALUE.OCTETS_PER_BEAT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_BEAT}] ${MODELPARAM_VALUE.OCTETS_PER_BEAT}
}
proc update_MODELPARAM_VALUE.EN_FRAME_ALIGN { MODELPARAM_VALUE.EN_FRAME_ALIGN PARAM_VALUE.EN_FRAME_ALIGN } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.EN_FRAME_ALIGN}] ${MODELPARAM_VALUE.EN_FRAME_ALIGN}
}
proc update_MODELPARAM_VALUE.TWOS_COMPLEMENT { MODELPARAM_VALUE.TWOS_COMPLEMENT PARAM_VALUE.TWOS_COMPLEMENT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TWOS_COMPLEMENT}] ${MODELPARAM_VALUE.TWOS_COMPLEMENT}
}
proc update_MODELPARAM_VALUE.EXT_SYNC { MODELPARAM_VALUE.EXT_SYNC PARAM_VALUE.EXT_SYNC } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.EXT_SYNC}] ${MODELPARAM_VALUE.EXT_SYNC}
}
proc update_MODELPARAM_VALUE.PN7_ENABLE { MODELPARAM_VALUE.PN7_ENABLE PARAM_VALUE.PN7_ENABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PN7_ENABLE}] ${MODELPARAM_VALUE.PN7_ENABLE}
}
proc update_MODELPARAM_VALUE.PN15_ENABLE { MODELPARAM_VALUE.PN15_ENABLE PARAM_VALUE.PN15_ENABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PN15_ENABLE}] ${MODELPARAM_VALUE.PN15_ENABLE}
}
adi_library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
+137
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_tpl_common #(
// parameters
parameter COMMON_ID = 2'h0, // Offset of regmap
parameter NUM_PROFILES = 1 // Number of JESD profiles
) (
input [NUM_PROFILES*8-1: 0] jesd_m,
input [NUM_PROFILES*8-1: 0] jesd_l,
input [NUM_PROFILES*8-1: 0] jesd_s,
input [NUM_PROFILES*8-1: 0] jesd_f,
input [NUM_PROFILES*8-1: 0] jesd_n,
input [NUM_PROFILES*8-1: 0] jesd_np,
output reg [$clog2(NUM_PROFILES):0] up_profile_sel = 'h0,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [10:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [10:0] up_raddr,
output [31:0] up_rdata,
output up_rack
);
// internal registers
reg up_rack_int = 'd0;
reg up_wack_int = 'd0;
reg [31:0] up_rdata_int = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
reg [31:0] up_rdata_jesd_params;
// decode block select
assign up_wreq_s = (up_waddr[10:7] == {COMMON_ID,1'b1}) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[10:7] == {COMMON_ID,1'b1}) ? up_rreq : 1'b0;
// processor write interface
assign up_wack = up_wack_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack_int <= 'd0;
up_profile_sel <= 'd0;
end else begin
up_wack_int <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h00)) begin
up_profile_sel <= up_wdata[$clog2(NUM_PROFILES):0];
end
end
end
// processor read interface
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack_int <= 'd0;
up_rdata_int <= 'd0;
end else begin
up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[6:0])
7'h00: up_rdata_int <= up_profile_sel;
7'h01: up_rdata_int <= NUM_PROFILES;
default: up_rdata_int <= up_rdata_jesd_params;
endcase
end else begin
up_rdata_int <= 32'd0;
end
end
end
integer i;
always @(*) begin
for (i=0; i<NUM_PROFILES; i = i + 1) begin:jesd_param
up_rdata_jesd_params = 0;
if (up_rreq_s == 1'b1) begin
if (up_raddr[6:0] == 7'h10 + {i[5:0],1'b0}) begin
up_rdata_jesd_params = {jesd_f[i*8+:8], jesd_s[i*8+:8],
jesd_l[i*8+:8], jesd_m[i*8+:8]};
end
if (up_raddr[6:0] == 7'h11 + {i[5:0],1'b0}) begin
up_rdata_jesd_params = {16'b0,jesd_np[i*8+:8], jesd_n[i*8+:8]};
end
end
end
end
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9135.qprs
+57
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9135 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 11" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 12" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 13" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9136.qprs
+57
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9136 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 11" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 12" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 13" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9144.qprs
+93
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9144 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9152.qprs
+57
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9152 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9152 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9152 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9152 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9152 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9152 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9154.qprs
+93
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9154 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9161.qprs
+57
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9161 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9161">
<parameter name="PART" value="AD9161" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9161 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9161">
<parameter name="PART" value="AD9161" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9161 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9161">
<parameter name="PART" value="AD9161" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="3" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="3" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9161 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9161">
<parameter name="PART" value="AD9161" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9161 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9161">
<parameter name="PART" value="AD9161" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="6" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="3" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9161 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9161">
<parameter name="PART" value="AD9161" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9162.qprs
+57
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9162 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9162">
<parameter name="PART" value="AD9162" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9162 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9162">
<parameter name="PART" value="AD9162" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9162 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9162">
<parameter name="PART" value="AD9162" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="3" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="3" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9162 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9162">
<parameter name="PART" value="AD9162" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9162 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9162">
<parameter name="PART" value="AD9162" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="6" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="3" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9162 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9162">
<parameter name="PART" value="AD9162" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9163.qprs
+57
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9163 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9163">
<parameter name="PART" value="AD9163" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9163 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9163">
<parameter name="PART" value="AD9163" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9163 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9163">
<parameter name="PART" value="AD9163" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="3" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="3" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9163 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9163">
<parameter name="PART" value="AD9163" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9163 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9163">
<parameter name="PART" value="AD9163" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="6" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="3" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9163 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9163">
<parameter name="PART" value="AD9163" />
<parameter name="NUM_CHANNELS" value="2" />
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<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9164.qprs
+57
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9164 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9164">
<parameter name="PART" value="AD9164" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9164 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9164">
<parameter name="PART" value="AD9164" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9164 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9164">
<parameter name="PART" value="AD9164" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="3" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="3" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9164 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9164">
<parameter name="PART" value="AD9164" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9164 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9164">
<parameter name="PART" value="AD9164" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="6" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="3" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9164 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9164">
<parameter name="PART" value="AD9164" />
<parameter name="NUM_CHANNELS" value="2" />
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<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9171.qprs
+30
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9171 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9171">
<parameter name="PART" value="AD9171" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9171 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9171">
<parameter name="PART" value="AD9171" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9171 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9171">
<parameter name="PART" value="AD9171" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9172.qprs
+156
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9172 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="6" />
<parameter name="NUM_LANES" value="3" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9172 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9172 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 11" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="4" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 12" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="8" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9172 Mode 18" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 19" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="4" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 20" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="4" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 21" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="8" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9173.qprs
+138
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9173 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="6" />
<parameter name="NUM_LANES" value="3" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9173 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9173 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
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<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 13" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 14" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 15" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 16" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="4" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 17" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="8" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/Makefile
+49
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@@ -0,0 +1,49 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := ad_ip_jesd204_tpl_dac
GENERIC_DEPS += ../../common/ad_dds.v
GENERIC_DEPS += ../../common/ad_dds_1.v
GENERIC_DEPS += ../../common/ad_dds_2.v
GENERIC_DEPS += ../../common/ad_dds_cordic_pipe.v
GENERIC_DEPS += ../../common/ad_dds_sine.v
GENERIC_DEPS += ../../common/ad_dds_sine_cordic.v
GENERIC_DEPS += ../../common/ad_iqcor.v
GENERIC_DEPS += ../../common/ad_mux.v
GENERIC_DEPS += ../../common/ad_mux_core.v
GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
GENERIC_DEPS += ../../common/ad_rst.v
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += ../../common/up_clock_mon.v
GENERIC_DEPS += ../../common/up_dac_channel.v
GENERIC_DEPS += ../../common/up_dac_common.v
GENERIC_DEPS += ../../common/up_xfer_cntrl.v
GENERIC_DEPS += ../../common/up_xfer_status.v
GENERIC_DEPS += ../../common/util_ext_sync.v
GENERIC_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_channel.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_core.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_framer.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_pn.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_regmap.v
XILINX_DEPS += ../../xilinx/common/ad_mul.v
XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += ad_ip_jesd204_tpl_dac_ip.tcl
INTEL_DEPS += ../../intel/common/ad_mul.v
INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_cntrl_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_status_constr.sdc
INTEL_DEPS += ad_ip_jesd204_tpl_dac_hw.tcl
include ../../scripts/library.mk
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
+291
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@@ -0,0 +1,291 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter NUM_LANES = 4,
parameter NUM_CHANNELS = 2,
parameter SAMPLES_PER_FRAME = 1,
parameter CONVERTER_RESOLUTION = 16, // JESD_N
parameter BITS_PER_SAMPLE = 16, // JESD_NP
parameter DMA_BITS_PER_SAMPLE = 16,
parameter PADDING_TO_MSB_LSB_N = 0,
parameter OCTETS_PER_BEAT = 4,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter DDS_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter EXT_SYNC = 0,
parameter XBAR_ENABLE = 0
) (
// jesd interface
// link_clk is (line-rate/40)
input link_clk,
output link_valid,
input link_ready,
output [NUM_LANES*8*OCTETS_PER_BEAT-1:0] link_data,
// dma interface
output [NUM_CHANNELS-1:0] enable,
output [NUM_CHANNELS-1:0] dac_valid,
input [DMA_BITS_PER_SAMPLE * OCTETS_PER_BEAT * 8 * NUM_LANES / BITS_PER_SAMPLE-1:0] dac_ddata,
input dac_dunf,
output dac_rst,
// external sync, should be on the link_clk clock domain
input dac_sync_in,
output dac_sync_manual_req_out,
input dac_sync_manual_req_in,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
output s_axi_awready,
input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
output s_axi_wready,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_bvalid,
input s_axi_bready,
output [1:0] s_axi_bresp,
input s_axi_arvalid,
output s_axi_arready,
input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp
);
localparam DATA_PATH_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES / NUM_CHANNELS / BITS_PER_SAMPLE;
localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8;
localparam DMA_DATA_WIDTH = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH * NUM_CHANNELS;
localparam BYTES_PER_FRAME = (NUM_CHANNELS * BITS_PER_SAMPLE * SAMPLES_PER_FRAME) / ( 8 * NUM_LANES);
// internal signals
wire dac_sync;
wire dac_ext_sync_arm;
wire dac_sync_in_status;
wire dac_dds_format;
wire [NUM_CHANNELS*16-1:0] dac_dds_scale_0_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_scale_1_s;
wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0_s;
wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0_s;
wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1_s;
wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1_s;
wire [NUM_CHANNELS*16-1:0] dac_pat_data_0_s;
wire [NUM_CHANNELS*16-1:0] dac_pat_data_1_s;
wire [NUM_CHANNELS*4-1:0] dac_data_sel_s;
wire [NUM_CHANNELS-1:0] dac_mask_enable_s;
wire [NUM_CHANNELS-1:0] dac_iqcor_enb;
wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1;
wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2;
wire [NUM_CHANNELS*8-1:0] dac_src_chan_sel;
reg [LINK_DATA_WIDTH-1:0] dac_ddata_cr;
// regmap
ad_ip_jesd204_tpl_dac_regmap #(
.ID (ID),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.XBAR_ENABLE (XBAR_ENABLE),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_CHANNELS (NUM_CHANNELS),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.PADDING_TO_MSB_LSB_N (PADDING_TO_MSB_LSB_N),
.NUM_PROFILES(1),
.EXT_SYNC (EXT_SYNC),
.DDS_PHASE_DW (DDS_PHASE_DW)
) i_regmap (
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awprot (s_axi_awprot),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_bresp (s_axi_bresp),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arprot (s_axi_arprot),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.s_axi_rready (s_axi_rready),
.link_clk (link_clk),
.dac_dunf (dac_dunf),
.dac_sync (dac_sync),
.dac_ext_sync_arm (dac_ext_sync_arm),
.dac_ext_sync_disarm (dac_ext_sync_disarm),
.dac_ext_sync_manual_req (dac_sync_manual_req_out),
.dac_sync_in_status (dac_sync_in_status),
.dac_dds_format (dac_dds_format),
.dac_dds_scale_0 (dac_dds_scale_0_s),
.dac_dds_init_0 (dac_dds_init_0_s),
.dac_dds_incr_0 (dac_dds_incr_0_s),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_pat_data_0 (dac_pat_data_0_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_data_sel (dac_data_sel_s),
.dac_mask_enable (dac_mask_enable_s),
.dac_iqcor_enb (dac_iqcor_enb),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2),
.dac_src_chan_sel (dac_src_chan_sel),
.jesd_m (NUM_CHANNELS),
.jesd_l (NUM_LANES),
.jesd_s (SAMPLES_PER_FRAME),
.jesd_f (BYTES_PER_FRAME),
.jesd_n (CONVERTER_RESOLUTION),
.jesd_np (BITS_PER_SAMPLE),
.up_profile_sel ());
// core
ad_ip_jesd204_tpl_dac_core #(
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.XBAR_ENABLE (XBAR_ENABLE),
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.DDS_PHASE_DW (DDS_PHASE_DW),
.EXT_SYNC (EXT_SYNC)
) i_core (
.clk (link_clk),
.link_valid (link_valid),
.link_ready (link_ready),
.link_data (link_data),
.enable (enable),
.dac_valid (dac_valid),
.dac_ddata (dac_ddata_cr),
.dac_rst (dac_rst),
.dac_sync (dac_sync),
.dac_ext_sync_arm (dac_ext_sync_arm),
.dac_ext_sync_disarm (dac_ext_sync_disarm),
.dac_sync_in_status (dac_sync_in_status),
.dac_sync_in (dac_sync_in),
.dac_sync_manual_req (dac_sync_manual_req_in),
.dac_dds_format (dac_dds_format),
.dac_dds_scale_0 (dac_dds_scale_0_s),
.dac_dds_init_0 (dac_dds_init_0_s),
.dac_dds_incr_0 (dac_dds_incr_0_s),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_pat_data_0 (dac_pat_data_0_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_data_sel (dac_data_sel_s),
.dac_mask_enable (dac_mask_enable_s),
.dac_iqcor_enb (dac_iqcor_enb),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2),
.dac_src_chan_sel (dac_src_chan_sel));
// Drop DMA padding bits from the LSB or MSB based on configuration
integer i;
always @(*) begin
for (i=0;i<NUM_CHANNELS*DATA_PATH_WIDTH;i=i+1) begin
if (PADDING_TO_MSB_LSB_N==1) begin
dac_ddata_cr[i*BITS_PER_SAMPLE +: BITS_PER_SAMPLE] = dac_ddata[i*DMA_BITS_PER_SAMPLE +: BITS_PER_SAMPLE];
end else begin
dac_ddata_cr[i*BITS_PER_SAMPLE +: BITS_PER_SAMPLE] = dac_ddata[((i+1)*DMA_BITS_PER_SAMPLE)-1 -: BITS_PER_SAMPLE];
end
end
end
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.xpr
+605
View File
@@ -0,0 +1,605 @@
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<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
+181
View File
@@ -0,0 +1,181 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_channel #(
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16,
parameter BITS_PER_SAMPLE = 16,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter DDS_PHASE_DW = 16,
parameter Q_OR_I_N = 0
) (
// dac interface
input clk,
input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dma_data,
output reg [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] dac_data = 'h00,
// PN data
input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data,
input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data,
// Configuration
input dac_data_sync,
input dac_dds_format,
input [3:0] dac_data_sel,
input dac_mask_enable,
input [15:0] dac_dds_scale_0,
input [15:0] dac_dds_scale_1,
input [DDS_PHASE_DW-1:0] dac_dds_init_0,
input [DDS_PHASE_DW-1:0] dac_dds_incr_0,
input [DDS_PHASE_DW-1:0] dac_dds_init_1,
input [DDS_PHASE_DW-1:0] dac_dds_incr_1,
input [15:0] dac_pat_data_0,
input [15:0] dac_pat_data_1,
input dac_iqcor_enb,
input [15:0] dac_iqcor_coeff_1,
input [15:0] dac_iqcor_coeff_2,
input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dac_iqcor_data_in,
output reg dac_enable = 1'b0
);
localparam CR = CONVERTER_RESOLUTION;
localparam CHANNEL_DATA_WIDTH = DATA_PATH_WIDTH * CR;
// internal signals
wire [CHANNEL_DATA_WIDTH-1:0] dac_dds_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_dma_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_pat_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_iqcor_data_s;
generate
if (DATA_PATH_WIDTH > 1) begin
assign dac_pat_data_s = {DATA_PATH_WIDTH/2{dac_pat_data_1[0+:CR],dac_pat_data_0[0+:CR]}};
end else begin
reg dac_pat_data_sel = 1'b0;
always @(posedge clk) begin
if (dac_data_sync == 1'b1) begin
dac_pat_data_sel <= 1'b0;
end else begin
dac_pat_data_sel <= ~dac_pat_data_sel;
end
end
assign dac_pat_data_s = dac_pat_data_sel == 1'b0 ?
dac_pat_data_0[0+:CR] : dac_pat_data_1[0+:CR];
end
genvar i;
/* Data is expected to be LSB aligned, drop unused MSBs */
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_dac_dma_data
assign dac_dma_data_s[CR*i+:CR] = dma_data[BITS_PER_SAMPLE*i+:CR];
end
endgenerate
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE),
.CR (CR),
.DPW (DATA_PATH_WIDTH)
) i_ad_iqcor (
.clk (clk),
.valid (1'b1),
.data_in (dac_dma_data_s),
.data_iq (dac_iqcor_data_in),
.valid_out (),
.data_out (dac_iqcor_data_s),
.iqcor_enable (dac_iqcor_enb),
.iqcor_coeff_1 (dac_iqcor_coeff_1),
.iqcor_coeff_2 (dac_iqcor_coeff_2));
// dac data select
always @(posedge clk) begin
dac_enable <= dac_mask_enable ? 1'b0 : (dac_data_sel == 4'h2);
casex ({dac_mask_enable,dac_data_sel})
5'h07: dac_data <= pn15_data;
5'h06: dac_data <= pn7_data;
5'h05: dac_data <= ~pn15_data;
5'h04: dac_data <= ~pn7_data;
5'h03: dac_data <= 'h00;
5'h02: dac_data <= dac_iqcor_data_s;
5'h01: dac_data <= dac_pat_data_s;
5'h1x: dac_data <= dac_iqcor_data_s;
default: dac_data <= dac_dds_data_s;
endcase
end
// dds
ad_dds #(
.DISABLE (DATAPATH_DISABLE),
.DDS_DW (CONVERTER_RESOLUTION),
.PHASE_DW (DDS_PHASE_DW),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.CLK_RATIO (DATA_PATH_WIDTH)
) i_dds (
.clk (clk),
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
.dac_valid (1'b1),
.tone_1_scale (dac_dds_scale_0),
.tone_2_scale (dac_dds_scale_1),
.tone_1_init_offset (dac_dds_init_0),
.tone_2_init_offset (dac_dds_init_1),
.tone_1_freq_word (dac_dds_incr_0),
.tone_2_freq_word (dac_dds_incr_1),
.dac_dds_data (dac_dds_data_s));
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
+234
View File
@@ -0,0 +1,234 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_core #(
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter XBAR_ENABLE = 1,
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 1,
parameter BITS_PER_SAMPLE = 16,
parameter CONVERTER_RESOLUTION = 16,
parameter SAMPLES_PER_FRAME = 1,
parameter OCTETS_PER_BEAT = 4,
parameter DATA_PATH_WIDTH = 4,
parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter DDS_PHASE_DW = 16,
parameter EXT_SYNC = 0
) (
// dac interface
input clk,
output link_valid,
input link_ready,
output [LINK_DATA_WIDTH-1:0] link_data,
// dma interface
output [NUM_CHANNELS-1:0] dac_valid,
input [LINK_DATA_WIDTH-1:0] dac_ddata,
output dac_rst,
// Configuration interface
input dac_sync,
input dac_ext_sync_arm,
input dac_ext_sync_disarm,
input dac_sync_in,
input dac_sync_manual_req,
output dac_sync_in_status,
input dac_dds_format,
input [NUM_CHANNELS*4-1:0] dac_data_sel,
input [NUM_CHANNELS-1:0] dac_mask_enable,
input [NUM_CHANNELS*16-1:0] dac_dds_scale_0,
input [NUM_CHANNELS*16-1:0] dac_dds_scale_1,
input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0,
input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0,
input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1,
input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1,
input [NUM_CHANNELS*16-1:0] dac_pat_data_0,
input [NUM_CHANNELS*16-1:0] dac_pat_data_1,
input [NUM_CHANNELS-1:0] dac_iqcor_enb,
input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1,
input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2,
input [NUM_CHANNELS*8-1:0] dac_src_chan_sel,
output [NUM_CHANNELS-1:0] enable
);
localparam DAC_CDW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH;
localparam DAC_DATA_WIDTH = DAC_CDW * NUM_CHANNELS;
wire [DAC_DATA_WIDTH-1:0] dac_data_s;
wire [DAC_DATA_WIDTH-1:0] dac_ddata_muxed;
wire [DAC_CDW-1:0] pn7_data;
wire [DAC_CDW-1:0] pn15_data;
wire [LINK_DATA_WIDTH-1:0] dac_ddata_int;
assign link_valid = 1'b1;
assign dac_sync_in_status = dac_sync_armed;
util_ext_sync #(
.ENABLED (EXT_SYNC)
) i_util_ext_sync (
.clk (clk),
.ext_sync_arm (dac_ext_sync_arm),
.ext_sync_disarm (dac_ext_sync_disarm),
.sync_in (dac_sync_in | dac_sync_manual_req),
.sync_armed (dac_sync_armed));
// Sync either from external or software source
assign dac_sync_int = dac_sync_armed | dac_sync;
// device interface
ad_ip_jesd204_tpl_dac_framer #(
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
.DAC_DATA_WIDTH (DAC_DATA_WIDTH)
) i_framer (
.link_data (link_data),
.dac_data (dac_data_s));
// PN generator
ad_ip_jesd204_tpl_dac_pn #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION)
) i_pn_gen (
.clk (clk),
.reset (dac_sync_int),
.pn7_data (pn7_data),
.pn15_data (pn15_data));
// dac valid
assign dac_valid = {NUM_CHANNELS{~dac_sync_armed}};
assign dac_rst = dac_sync_armed;
// Gate input data
assign dac_ddata_int = dac_sync_armed ? {LINK_DATA_WIDTH{1'b0}} : dac_ddata;
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
// Find the pair of the current channel for I/Q channels
// Assuming even channels are I, odd channels are Q
// Assuming channel count is even other case do not pair channels
localparam IQ_PAIR_CH_INDEX = (NUM_CHANNELS%2) ? i :
(i%2) ? i-1 : i+1;
if (XBAR_ENABLE == 1) begin
// NUM_CHANNELS : 1 mux
ad_mux #(
.CH_W (DAC_CDW),
.CH_CNT (NUM_CHANNELS),
.EN_REG (1)
) channel_mux (
.clk (clk),
.data_in (dac_ddata_int),
.ch_sel (dac_src_chan_sel[8*i+:8]),
.data_out (dac_ddata_muxed[DAC_CDW*i+:DAC_CDW]));
end else begin
assign dac_ddata_muxed[DAC_CDW*i+:DAC_CDW] = dac_ddata_int[DAC_CDW*i+:DAC_CDW];
end
ad_ip_jesd204_tpl_dac_channel #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.DDS_PHASE_DW (DDS_PHASE_DW),
.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE),
.Q_OR_I_N(i%2)
) i_channel (
.clk (clk),
.dac_enable (enable[i]),
.dac_data (dac_data_s[DAC_CDW*i+:DAC_CDW]),
.dma_data (dac_ddata_muxed[DAC_CDW*i+:DAC_CDW]),
.pn7_data (pn7_data),
.pn15_data (pn15_data),
.dac_data_sync (dac_sync_int),
.dac_dds_format (dac_dds_format),
.dac_data_sel (dac_data_sel[4*i+:4]),
.dac_mask_enable (dac_mask_enable[i]),
.dac_dds_scale_0 (dac_dds_scale_0[16*i+:16]),
.dac_dds_scale_1 (dac_dds_scale_1[16*i+:16]),
.dac_dds_init_0 (dac_dds_init_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]),
.dac_dds_incr_0 (dac_dds_incr_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]),
.dac_dds_init_1 (dac_dds_init_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]),
.dac_dds_incr_1 (dac_dds_incr_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]),
.dac_pat_data_0 (dac_pat_data_0[16*i+:16]),
.dac_pat_data_1 (dac_pat_data_1[16*i+:16]),
.dac_iqcor_enb (dac_iqcor_enb[i]),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]),
.dac_iqcor_data_in (dac_ddata_muxed[DAC_CDW*IQ_PAIR_CH_INDEX+:DAC_CDW]));
end
endgenerate
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_framer #(
parameter NUM_LANES = 8,
parameter NUM_CHANNELS = 4,
parameter BITS_PER_SAMPLE = 16,
parameter CONVERTER_RESOLUTION = 16,
parameter SAMPLES_PER_FRAME = 2,
parameter OCTETS_PER_BEAT = 4,
parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
parameter DAC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
) (
// jesd interface
output [LINK_DATA_WIDTH-1:0] link_data,
// dac interface
input [DAC_DATA_WIDTH-1:0] dac_data
);
/*
* The framer module takes sample data and maps it onto the format that the
* JESD204 link expects for the specified framer configuration.
*
* The input sample data in dac_data is expected to be grouped by converter.
* The first sample is in the LSBs. Each sample has CONVERTER_RESOLUTION bits.
*
* Or in other words the data in dac_data is expected to have the following
* layout.
*
* MSB LSB
* [ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
*
* Where MjSi refers to the i-th sample of the j-th converter. With m being
* the number of converters and n the number of samples per converter per
* beat.
*
* In the default configuration the framer module processes 4 octets per beat.
* This means it can support settings with either 1, 2 or 4 octets per frame
* (F). Depending on the octets per frame the frames per beat will either be
* 4, 2 or 1 respectively. For other settings of OCTETS_PER_BEAT similar
* reasoning applies.
*
* The number of samples per frame (S) and the number of frames processed per
* beat gives the number of samples per converter per beat. This is either
* S * 4 (for F=1), S * 2 (for F=2) or S (for F=1).
*
* The framer module does not have a parameter for the octets per frame (F)
* since it can be derived from all other parameters given the following
* relationship: F = (M * N' * S) / (L * 8)
*
*
* Mapping in performed in two steps. First samples are grouped into frames,
* as there might be more than one frame pert beat. In the second step the
* frames are distributed onto the lanes.
*
* In the JESD204 standard samples and octets are ordered MSB first, this
* means earlier data is in the MSBs. This core on the other hand expects
* samples and octets to be LSB first ordered. This means earlier data is in
* the LSBs. To accommodate this two additional steps are required to order
* data from LSB to MSB before the framing process and back from MSB to LSB
* after it.
*
* The data itself that is contained within the samples and octets is LSB
* ordered in either case. That means lower bits are in the LSBs.
*/
localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME;
localparam BITS_PER_LANE_PER_FRAME = BITS_PER_CHANNEL_PER_FRAME *
NUM_CHANNELS / NUM_LANES;
localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME;
localparam SAMPLES_PER_BEAT = DAC_DATA_WIDTH / CONVERTER_RESOLUTION;
localparam TAIL_BITS = BITS_PER_SAMPLE - CONVERTER_RESOLUTION;
wire [LINK_DATA_WIDTH-1:0] link_data_msb_s;
wire [LINK_DATA_WIDTH-1:0] frame_data_s;
wire [LINK_DATA_WIDTH-1:0] dac_data_msb;
generate
genvar i;
genvar j;
/* Reorder samples MSB first and insert tail bits */
for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin: g_dac_data_msb
localparam src_w = CONVERTER_RESOLUTION;
localparam dst_w = BITS_PER_SAMPLE;
localparam src_lsb = i * src_w;
localparam dst_msb = LINK_DATA_WIDTH - 1 - i * dst_w;
assign dac_data_msb[dst_msb-:src_w] = dac_data[src_lsb+:src_w];
if (TAIL_BITS > 0) begin
assign dac_data_msb[dst_msb-src_w-:TAIL_BITS] = {TAIL_BITS{1'b0}};
end
end
/* Slice channel and pack it into frames */
ad_perfect_shuffle #(
.NUM_GROUPS (NUM_CHANNELS),
.WORDS_PER_GROUP (FRAMES_PER_BEAT),
.WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME)
) i_channels_to_frames (
.data_in (dac_data_msb),
.data_out (frame_data_s));
/* Slice frame and pack it into lanes */
ad_perfect_shuffle #(
.NUM_GROUPS (FRAMES_PER_BEAT),
.WORDS_PER_GROUP (NUM_LANES),
.WORD_WIDTH (BITS_PER_LANE_PER_FRAME)
) i_frames_to_lanes (
.data_in (frame_data_s),
.data_out (link_data_msb_s));
/* Reorder octets LSB first */
for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_link_data
assign link_data[i+:8] = link_data_msb_s[LINK_DATA_WIDTH-1-i-:8];
end
endgenerate
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
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###############################################################################
## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
package require qsys 14.0
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create ad_ip_jesd204_tpl_dac "JESD204 Transport Layer for DACs" p_ad_ip_jesd204_tpl_dac_elab
set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_dac_validate
ad_ip_files ad_ip_jesd204_tpl_dac [list \
$ad_hdl_dir/library/intel/common/ad_mul.v \
$ad_hdl_dir/library/common/ad_mux.v \
$ad_hdl_dir/library/common/ad_mux_core.v \
$ad_hdl_dir/library/common/ad_dds_sine.v \
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
$ad_hdl_dir/library/common/ad_dds_2.v \
$ad_hdl_dir/library/common/ad_dds_1.v \
$ad_hdl_dir/library/common/ad_dds.v \
$ad_hdl_dir/library/common/ad_iqcor.v \
$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
$ad_hdl_dir/library/common/up_xfer_status.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/common/up_dac_common.v \
$ad_hdl_dir/library/common/up_dac_channel.v \
$ad_hdl_dir/library/common/util_ext_sync.v \
\
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
\
ad_ip_jesd204_tpl_dac.v \
ad_ip_jesd204_tpl_dac_channel.v \
ad_ip_jesd204_tpl_dac_core.v \
ad_ip_jesd204_tpl_dac_framer.v \
ad_ip_jesd204_tpl_dac_pn.v \
ad_ip_jesd204_tpl_dac_regmap.v \
../ad_ip_jesd204_tpl_common/up_tpl_common.v \
]
# parameters
set group "General Configuration"
ad_ip_parameter ID INTEGER 0 true [list \
DISPLAY_NAME "Core ID" \
GROUP $group \
]
ad_ip_parameter OCTETS_PER_BEAT INTEGER 4 true [list \
DISPLAY_NAME "Datapath width" \
DISPLAY_UNITS "octets" \
ALLOWED_RANGES {4 6 8 12} \
GROUP $group \
]
set group "JESD204 Framer Configuration"
ad_ip_parameter PART STRING "Generic" false [list \
DISPLAY_NAME "Part" \
ALLOWED_RANGES { \
"Generic" \
"AD9135" \
"AD9136" \
"AD9144" \
"AD9152" \
"AD9154" \
"AD9161" \
"AD9162" \
"AD9163" \
"AD9164" \
"AD9171" \
"AD9172" \
"AD9173" \
} \
GROUP $group \
]
ad_ip_parameter NUM_LANES INTEGER 1 true [list \
DISPLAY_NAME "Number of Lanes (L)" \
DISPLAY_UNITS "lanes" \
ALLOWED_RANGES {1 2 3 4 8 16 24 32} \
GROUP $group \
]
ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \
DISPLAY_NAME "Number of Converters (M)" \
DISPLAY_UNITS "converters" \
ALLOWED_RANGES {1 2 4 6 8 16 32 64} \
GROUP $group \
]
ad_ip_parameter BITS_PER_SAMPLE INTEGER 16 true [list \
DISPLAY_NAME "Bits per Sample (N')" \
ALLOWED_RANGES {8 12 16} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter DMA_BITS_PER_SAMPLE INTEGER 16 true [list \
DISPLAY_NAME "DMA Bits per Sample" \
ALLOWED_RANGES {8 16} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter CONVERTER_RESOLUTION INTEGER 16 true [list \
DISPLAY_NAME "Converter Resolution (N)" \
ALLOWED_RANGES {8 11 12 16} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter ENABLE_SAMPLES_PER_FRAME_MANUAL BOOLEAN 0 false [list \
DISPLAY_NAME "Manual Samples per Frame" \
GROUP $group \
]
ad_ip_parameter SAMPLES_PER_FRAME INTEGER 1 true [list \
DISPLAY_NAME "Samples per Frame (S)" \
DISPLAY_UNITS "samples" \
ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
DERIVED true \
GROUP $group \
]
ad_ip_parameter SAMPLES_PER_FRAME_MANUAL INTEGER 1 false [list \
DISPLAY_NAME "Samples per Frame (S)" \
DISPLAY_UNITS "samples" \
ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
VISIBLE false \
GROUP $group \
]
ad_ip_parameter OCTETS_PER_FRAME INTEGER 1 false [list \
DISPLAY_NAME "Octets per Frame (F)" \
DISPLAY_UNITS "octets" \
ALLOWED_RANGES {1 2 3 4 6 8} \
DERIVED true \
GROUP $group \
]
set group "Framer Input Information"
# Parameters in this group are informative only and can be read back after the
# core has been configured to find out the expected layout of the input data.
# E.g.
# set NUM_OF_CHANNELS [get_instance_parameter_value jesd204_transport NUM_CHANNELS]
# set CHANNEL_DATA_WIDTH [get_instance_parameter_value jesd204_transport CHANNEL_DATA_WIDTH]
#
# add_instance util_dac_upack util_upack
# set_instance_parameter_values util_dac_upack [list \
# CHANNEL_DATA_WIDTH $CHANNEL_DATA_WIDTH \
# NUM_OF_CHANNELS $NUM_OF_CHANNELS \
# ]
ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 false [list \
DISPLAY_NAME "Samples per Channel per Beat" \
DERIVED true \
GROUP $group \
]
ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 1 false [list \
DISPLAY_NAME "Channel Data Width" \
UNITS bits \
DERIVED true \
GROUP $group \
]
set group "Datapath Configuration"
ad_ip_parameter DATAPATH_DISABLE boolean 0 true [list \
DISPLAY_NAME "Disable Datapath" \
GROUP $group \
]
ad_ip_parameter DDS_TYPE INTEGER 1 true [list \
DISPLAY_NAME "DDS Type" \
ALLOWED_RANGES {"0:Polynominal" "1:CORDIC"} \
GROUP $group \
]
ad_ip_parameter DDS_CORDIC_DW INTEGER 16 true [list \
DISPLAY_NAME "CORDIC DDS Data Width" \
ALLOWED_RANGES {8:20} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter DDS_CORDIC_PHASE_DW INTEGER 16 true [list \
DISPLAY_NAME "CORDIC DDS Phase Width" \
ALLOWED_RANGES {8:20} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter XBAR_ENABLE boolean 0 true [list \
DISPLAY_NAME "Channel Crossbar Enable" \
GROUP $group \
]
# axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
# core clock and start of frame
add_interface link_clk clock end
add_interface_port link_clk link_clk clk Input 1
# We don't expect too large values for a and b, trivial implementation will do
proc gcd {a b} {
if {$a == $b} {
return $b
} elseif {$a > $b} {
return [gcd [expr $a - $b] $b]
} else {
return [gcd $a [expr $b - $a]]
}
}
# M L S F N NP
set ad9136_modes { \
{1 4 2 1 16 16} \
{1 2 1 1 16 16} \
{1 1 1 2 16 16} \
{2 8 2 1 16 16} \
{2 4 1 1 16 16} \
{2 2 1 2 16 16} \
}
set ad9144_modes { \
{4 8 1 1 16 16} \
{4 8 2 2 16 16} \
{4 4 1 2 16 16} \
{4 2 1 4 16 16} \
{2 4 1 1 16 16} \
{2 4 2 2 16 16} \
{2 2 1 2 16 16} \
{2 1 1 4 16 16} \
{1 2 1 1 16 16} \
{1 1 1 2 16 16} \
}
set ad9152_modes { \
{2 4 1 1 16 16} \
{2 4 2 2 16 16} \
{2 2 1 2 16 16} \
{2 1 1 4 16 16} \
{1 2 1 1 16 16} \
{1 1 1 2 16 16} \
}
set ad9161_modes { \
{2 1 1 4 16 16} \
{2 2 1 2 16 16} \
{2 3 3 4 16 16} \
{2 4 1 1 16 16} \
{2 6 3 2 16 16} \
{1 8 4 1 16 16} \
{2 8 2 1 16 16} \
}
set ad9163_modes { \
{2 1 1 4 16 16} \
{2 2 1 2 16 16} \
{2 3 3 4 16 16} \
{2 4 1 1 16 16} \
{2 6 3 2 16 16} \
{2 8 2 1 16 16} \
}
set ad9171_modes { \
{2 1 1 4 16 16} \
{2 2 1 2 16 16} \
{2 1 1 3 12 12} \
}
set ad9172_modes { \
{2 1 1 4 16 16} \
{4 2 1 4 16 16} \
{6 3 1 4 16 16} \
{2 2 1 2 16 16} \
{4 4 1 2 16 16} \
{2 1 1 3 12 12} \
{4 2 1 3 12 12} \
{4 1 1 8 16 16} \
{2 4 1 1 16 16} \
{2 4 2 2 16 16} \
{2 8 2 1 16 16} \
{2 8 4 2 16 16} \
{2 8 8 3 12 12} \
{1 4 2 1 16 16} \
{1 4 4 2 16 16} \
{1 8 4 1 16 16} \
{1 8 8 2 16 16} \
}
set ad9173_modes { \
{2 1 1 4 16 16} \
{4 2 1 4 16 16} \
{6 3 1 4 16 16} \
{2 2 1 2 16 16} \
{4 4 1 2 16 16} \
{2 1 1 3 12 12} \
{4 2 1 3 12 12} \
{4 1 1 8 16 16} \
{2 4 1 1 16 16} \
{2 4 2 2 16 16} \
{2 4 1 1 11 16} \
{2 4 2 2 11 16} \
{2 8 2 1 11 16} \
{2 8 4 2 11 16} \
{2 8 8 3 11 12} \
}
# validate
proc p_ad_ip_jesd204_tpl_dac_validate {} {
set L [get_parameter_value "NUM_LANES"]
set M [get_parameter_value "NUM_CHANNELS"]
set NP [get_parameter_value "BITS_PER_SAMPLE"]
set N [get_parameter_value "CONVERTER_RESOLUTION"]
set S_manual [get_parameter_value "SAMPLES_PER_FRAME_MANUAL"]
set enable_S_manual [get_parameter_value "ENABLE_SAMPLES_PER_FRAME_MANUAL"]
# With fixed values for M, L and N' all valid values for S and F have a
# constant ratio of S / F. Choose a ratio so that S and F are co-prime.
# Choosing values for F and S that have a common factor has higher latency
# and no added benefits.
#
# Since converters often support those higher latency modes still allow a
# manual override of the S parameter in case somebody wants to use those modes
# anyway.
#
# To be able to set samples per frame manually ENABLE_SAMPLES_PER_FRAME_MANUAL
# needs to be set to true and SAMPLES_PER_FRAME_MANUAL to the desired value.
#
# When manual sample per frame selection is enabled still verify that the
# selected value is valid.
set S_min [expr $L * 8]
set F_min [expr $M * $NP]
set common_factor [gcd $S_min $F_min]
set S_min [expr $S_min / $common_factor]
set F_min [expr $F_min / $common_factor]
if {$enable_S_manual} {
if {$S_manual % $S_min != 0} {
send_message ERROR "For framer configuration (L=$L, M=$M, NP=$NP) samples per frame (S) must be an integer multiple of $S_min"
set S $S_min
set F $F_min
} else {
set S $S_manual
set F [expr $S_manual * $M * $NP / $L / 8]
}
} else {
set S $S_min
set F $F_min
}
set_parameter_value OCTETS_PER_FRAME $F
set_parameter_value SAMPLES_PER_FRAME $S
set_parameter_property SAMPLES_PER_FRAME VISIBLE [expr !$enable_S_manual]
set_parameter_property SAMPLES_PER_FRAME_MANUAL VISIBLE $enable_S_manual
set_parameter_value SAMPLES_PER_CHANNEL [expr 4 * $S / $F]
set_parameter_value CHANNEL_DATA_WIDTH [expr 16 * (4 * $S / $F)]
set data_path_enabled [expr ![get_parameter_value DATAPATH_DISABLE]]
set cordic_enabled [expr $data_path_enabled && [get_parameter_value DDS_TYPE] == 1]
set_parameter_property DDS_TYPE ENABLED $data_path_enabled
set_parameter_property DDS_CORDIC_DW ENABLED $cordic_enabled
set_parameter_property DDS_CORDIC_PHASE_DW ENABLED $cordic_enabled
set part [get_parameter_value "PART"]
if {$part == "AD9135" || $part == "AD9136"} {
global ad9136_modes
set modes $ad9136_modes
} elseif {$part == "AD9144" || $part == "AD9154"} {
global ad9144_modes
set modes $ad9144_modes
} elseif {$part == "AD9152"} {
global ad9152_modes
set modes $ad9152_modes
} elseif {$part == "AD9161" || $part == "AD9162" || $part == "AD9164"} {
global ad9161_modes
set modes $ad9161_modes
} elseif {$part == "AD9163"} {
global ad9163_modes
set modes $ad9163_modes
} elseif {$part == "AD9171"} {
global ad9171_modes
set modes $ad9171_modes
} elseif {$part == "AD9172"} {
global ad9172_modes
set modes $ad9172_modes
} elseif {$part == "AD9173"} {
global ad9173_modes
set modes $ad9173_modes
} else {
set modes {}
}
if {$modes != {}} {
set allowed_channels {}
set allowed_lanes {}
set allowed_samples_per_frame {}
set allowed_resolution {}
set allowed_bits_per_sample {}
set valid_mode false
foreach m $modes {
if {$m == [list $M $L $S $F $N $NP]} {
set valid_mode true
}
lappend allowed_channels [lindex $m 0]
lappend allowed_lanes [lindex $m 1]
lappend allowed_samples_per_frame [lindex $m 2]
lappend allowed_resolution [lindex $m 4]
lappend allowed_bits_per_sample [lindex $m 5]
}
set allowed_channels [lsort -unique -integer $allowed_channels]
set allowed_lanes [lsort -unique -integer $allowed_lanes]
set allowed_samples_per_frame [lsort -unique -integer $allowed_samples_per_frame]
set allowed_resolution [lsort -unique -integer $allowed_resolution]
set allowed_bits_per_sample [lsort -unique -integer $allowed_bits_per_sample]
if {!$valid_mode} {
send_message ERROR "Framer configuration (L=$L, M=$M, N=$N, NP=$NP, S=$S, F=$F) not supported by $part"
}
} else {
set allowed_channels {1 2 4 6 8 16 32 64}
set allowed_lanes {1 2 3 4 8 16}
set allowed_samples_per_frame {1 2 3 4 6 8 12 16}
set allowed_resolution {8 11 12 16}
set allowed_bits_per_sample {8 12 16}
}
set_parameter_property "NUM_CHANNELS" "ALLOWED_RANGES" $allowed_channels
set_parameter_property "NUM_LANES" "ALLOWED_RANGES" $allowed_lanes
set_parameter_property "SAMPLES_PER_FRAME" "ALLOWED_RANGES" $allowed_samples_per_frame
set_parameter_property "CONVERTER_RESOLUTION" "ALLOWED_RANGES" $allowed_resolution
set_parameter_property "BITS_PER_SAMPLE" "ALLOWED_RANGES" $allowed_bits_per_sample
if {$enable_S_manual} {
set allowed_S {}
foreach i {1 2 4} {
if {$F_min * $i <= 4 && $S_min * $i <= 16} {
set new_S [expr $S_min * $i]
if {[lsearch -integer $allowed_samples_per_frame $new_S] != -1} {
lappend allowed_S $new_S
}
}
}
set_parameter_property SAMPLES_PER_FRAME_MANUAL ALLOWED_RANGES $allowed_S
} else {
set_parameter_property SAMPLES_PER_FRAME_MANUAL ALLOWED_RANGES {1 2 3 4 6 8 12 16}
}
}
# elaborate
proc p_ad_ip_jesd204_tpl_dac_elab {} {
# read core parameters
set L [get_parameter_value "NUM_LANES"]
set M [get_parameter_value "NUM_CHANNELS"]
set NP [get_parameter_value "BITS_PER_SAMPLE"]
set OPB [get_parameter_value "OCTETS_PER_BEAT"]
set DMA_BPS [get_parameter_value "DMA_BITS_PER_SAMPLE"]
# The DMA interface is rounded to nearest power of two bytes per sample,
# e.g NP=12 is padded into 16 bits
set samples_per_beat_per_channel [expr ($OPB * 8 * $L / ($M * $NP))]
set channel_bus_width [expr $samples_per_beat_per_channel*$DMA_BPS]
# link layer interface
add_interface link_data avalon_streaming source
add_interface_port link_data link_data data output [expr $OPB*8*$L]
add_interface_port link_data link_valid valid output 1
add_interface_port link_data link_ready ready input 1
set_interface_property link_data associatedClock link_clk
set_interface_property link_data dataBitsPerSymbol [expr $OPB*8*$L]
# dma interface
for {set i 0} {$i < $M} {incr i} {
add_interface dac_ch_$i conduit end
add_interface_port dac_ch_$i dac_enable_$i enable output 1
set_port_property dac_enable_$i fragment_list [format "enable(%d:%d)" $i $i]
add_interface_port dac_ch_$i dac_valid_$i valid output 1
set_port_property dac_valid_$i fragment_list [format "dac_valid(%d:%d)" $i $i]
add_interface_port dac_ch_$i dac_data_$i data input $channel_bus_width
set_port_property dac_data_$i fragment_list \
[format "dac_ddata(%d:%d)" [expr $channel_bus_width*$i+$channel_bus_width-1] [expr $channel_bus_width*$i]]
set_interface_property dac_ch_$i associatedClock link_clk
}
ad_interface signal dac_dunf input 1 unf
}
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
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###############################################################################
## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create ad_ip_jesd204_tpl_dac
adi_ip_files ad_ip_jesd204_tpl_dac [list \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_mux.v" \
"$ad_hdl_dir/library/common/ad_mux_core.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/util_ext_sync.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"../ad_ip_jesd204_tpl_common/up_tpl_common.v" \
"ad_ip_jesd204_tpl_dac_channel.v" \
"ad_ip_jesd204_tpl_dac_core.v" \
"ad_ip_jesd204_tpl_dac_framer.v" \
"ad_ip_jesd204_tpl_dac_regmap.v" \
"ad_ip_jesd204_tpl_dac_pn.v" \
"ad_ip_jesd204_tpl_dac.v" ]
adi_ip_properties ad_ip_jesd204_tpl_dac
adi_init_bd_tcl
adi_ip_bd ad_ip_jesd204_tpl_dac "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac} [ipx::current_core]
set cc [ipx::current_core]
set_property display_name "JESD204 Transport Layer for DACs" $cc
set_property description "JESD204 Transport Layer for DACs" $cc
# ADD missing stuff #######################################################
adi_add_bus "link" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list \
{"link_ready" "TREADY"} \
{"link_valid" "TVALID"} \
{"link_data" "TDATA"} \
]
adi_add_bus_clock "link_clk" "link"
adi_set_ports_dependency "dac_sync_in" "EXT_SYNC == 1"
adi_set_ports_dependency "dac_sync_manual_req_out" "EXT_SYNC == 1"
adi_set_ports_dependency "dac_sync_manual_req_in" "EXT_SYNC == 1"
set_property -dict [list \
"value_validation_type" "pairs" \
"value_validation_pairs" {"Polynominal" "0" "CORDIC" "1"} \
"enablement_tcl_expr" "\$DATAPATH_DISABLE == 0" \
] [ipx::get_user_parameters DDS_TYPE -of_objects $cc]
foreach p {DDS_CORDIC_DW DDS_CORDIC_PHASE_DW} {
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" 8 \
"value_validation_range_maximum" 20 \
"enablement_tcl_expr" "\$DATAPATH_DISABLE == 0 && \$DDS_TYPE == 1" \
] [ipx::get_user_parameters $p -of_objects $cc]
}
foreach {p v} {
"NUM_LANES" "1 2 3 4 6 8 12 16 24 32" \
"NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
"BITS_PER_SAMPLE" "8 12 16" \
"DMA_BITS_PER_SAMPLE" "8 12 16" \
"CONVERTER_RESOLUTION" "8 11 12 16" \
"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
"OCTETS_PER_BEAT" "4 6 8 12 16 32 64" \
} { \
set_property -dict [list \
"value_validation_type" "list" \
"value_validation_list" $v \
] [ipx::get_user_parameters $p -of_objects $cc]
}
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
-parent $page0 -display_name "General Configuration"]
set p [ipgui::get_guiparamspec -name "ID" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $general_group
set_property -dict [list \
"display_name" "Core ID" \
] $p
set framer_group [ipgui::add_group -name "JESD204 Framer Configuration" -component $cc \
-parent $page0 -display_name "JESD204 Framer Cofiguration"]
set i 0
foreach {k v} { \
"NUM_LANES" "Number of Lanes (L)" \
"NUM_CHANNELS" "Number of Conveters (M)" \
"BITS_PER_SAMPLE" "Bits per Sample (N')" \
"DMA_BITS_PER_SAMPLE" "DMA Bits per Sample" \
"CONVERTER_RESOLUTION" "Converter Resolution (N)" \
"SAMPLES_PER_FRAME" "Samples per Frame (S)" \
"OCTETS_PER_BEAT" "Octets per Beat" \
} { \
set p [ipgui::get_guiparamspec -name $k -component $cc]
ipgui::move_param -component $cc -order $i $p -parent $framer_group
set_property -dict [list \
WIDGET "comboBox" \
DISPLAY_NAME $v \
] $p
incr i
}
set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \
-parent $page0 -display_name "Datapath Cofiguration"]
set i 0
foreach {k v w} {
"DATAPATH_DISABLE" "Disable Datapath" "checkBox" \
"EXT_SYNC" "Enable external SYNC" "checkBox" \
"IQCORRECTION_DISABLE" "Disable IQ Correction" "checkBox" \
"XBAR_ENABLE" "Enable user data XBAR" "checkBox" \
"DDS_TYPE" "DDS Type" "comboBox" \
"DDS_PHASE_DW" "DDS Phase Width" "text" \
"DDS_CORDIC_DW" "CORDIC DDS Data Width" "text" \
"DDS_CORDIC_PHASE_DW" "CORDIC DDS Phase Width" "text" \
} { \
set p [ipgui::get_guiparamspec -name $k -component $cc]
ipgui::move_param -component $cc -order $i $p -parent $datapath_group
set_property -dict [list \
WIDGET $w \
DISPLAY_NAME $v \
] $p
incr i
}
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_pn #(
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16
) (
input clk,
input reset,
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data,
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data
);
localparam CR = CONVERTER_RESOLUTION;
localparam DW = DATA_PATH_WIDTH * CR - 1;
/* We need at least enough bits to store the PN state */
localparam PN7_W = DW > 6 ? DW : 6;
localparam PN15_W = DW > 14 ? DW : 14;
reg [PN7_W:0] pn7_state = {PN7_W+1{1'b1}};
reg [PN15_W:0] pn15_state = {PN15_W+1{1'b1}};
wire [DW:0] pn7;
wire [DW+7:0] pn7_full_state;
wire [PN7_W:0] pn7_reset;
wire [DW:0] pn15;
wire [DW+15:0] pn15_full_state;
wire [PN15_W:0] pn15_reset;
/* PN7 x^7 + x^6 + 1 */
assign pn7 = pn7_full_state[7+:DW+1] ^ pn7_full_state[6+:DW+1];
assign pn7_full_state = {pn7_state[6:0],pn7};
/* PN15 x^15 + x^14 + 1 */
assign pn15 = pn15_full_state[15+:DW+1] ^ pn15_full_state[14+:DW+1];
assign pn15_full_state = {pn15_state[14:0],pn15};
assign pn7_reset[PN7_W-:7] = {7{1'b1}};
assign pn15_reset[PN15_W-:15] = {15{1'b1}};
generate
if (PN7_W >= 7) begin
assign pn7_reset[PN7_W-7:0] = pn7_reset[PN7_W:7] ^ pn7_reset[PN7_W-1:6];
end
if (PN15_W >= 15) begin
assign pn15_reset[PN15_W-15:0] = pn15_reset[PN15_W:15] ^ pn15_reset[PN15_W-1:14];
end
endgenerate
always @(posedge clk) begin
if (reset == 1'b1) begin
pn7_state <= pn7_reset;
pn15_state <= pn15_reset;
end else begin
pn7_state <= pn7_full_state[PN7_W:0];
pn15_state <= pn15_full_state[PN15_W:0];
end
end
generate
/*
* The first sample contains the first MSB of the PN sequence, but the first
* sample is also in the LSB of the output data. So extract data at the MSB
* sample of the PN state and put it into the LSB sample of the output data.
*/
genvar i;
for (i = 0; i <= DW; i = i + CR) begin: g_pn_swizzle
assign pn7_data[i+:CR] = pn7_state[PN7_W-i-:CR];
assign pn15_data[i+:CR] = pn15_state[PN15_W-i-:CR];
end
endgenerate
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_regmap #(
parameter ID = 0,
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter XBAR_ENABLE = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter NUM_CHANNELS = 2,
parameter DATA_PATH_WIDTH = 16,
parameter PADDING_TO_MSB_LSB_N = 0,
parameter EXT_SYNC = 0,
parameter NUM_PROFILES = 1, // Number of supported JESD profiles
parameter DDS_PHASE_DW = 16
) (
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
output s_axi_awready,
input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
output s_axi_wready,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_arvalid,
output s_axi_arready,
input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_bvalid,
input s_axi_bready,
output [1:0] s_axi_bresp,
input link_clk,
input dac_dunf,
output dac_sync,
output dac_ext_sync_arm,
output dac_ext_sync_disarm,
output dac_ext_sync_manual_req,
input dac_sync_in_status,
output [NUM_CHANNELS*4-1:0] dac_data_sel,
output [NUM_CHANNELS-1:0] dac_mask_enable,
output dac_dds_format,
output [NUM_CHANNELS*16-1:0] dac_dds_scale_0,
output [NUM_CHANNELS*16-1:0] dac_dds_scale_1,
output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0,
output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0,
output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1,
output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1,
output [NUM_CHANNELS*16-1:0] dac_pat_data_0,
output [NUM_CHANNELS*16-1:0] dac_pat_data_1,
output [NUM_CHANNELS-1:0] dac_iqcor_enb,
output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1,
output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2,
output [NUM_CHANNELS*8-1:0] dac_src_chan_sel,
// Framer interface
input [NUM_PROFILES*8-1: 0] jesd_m,
input [NUM_PROFILES*8-1: 0] jesd_l,
input [NUM_PROFILES*8-1: 0] jesd_s,
input [NUM_PROFILES*8-1: 0] jesd_f,
input [NUM_PROFILES*8-1: 0] jesd_n,
input [NUM_PROFILES*8-1: 0] jesd_np,
output [$clog2(NUM_PROFILES):0] up_profile_sel
);
// internal registers
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'h00;
reg [31:0] up_rdata_all;
wire up_wreq_s;
wire [10:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [NUM_CHANNELS+1:0] up_wack_s;
wire up_rreq_s;
wire [10:0] up_raddr_s;
wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
wire [NUM_CHANNELS+1:0] up_rack_s;
// internal clocks and resets
wire up_clk;
wire up_rstn;
wire dac_rst;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// up bus interface
up_axi #(
.AXI_ADDRESS_WIDTH (13)
) i_up_axi (
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
integer n;
always @(*) begin
up_rdata_all = 'h00;
for (n = 0; n < NUM_CHANNELS + 2; n = n + 1) begin
up_rdata_all = up_rdata_all | up_rdata_s[n];
end
end
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_all;
up_rack <= |up_rack_s;
up_wack <= |up_wack_s;
end
end
// dac common processor interface
localparam CONFIG = (EXT_SYNC << 12) |
(PADDING_TO_MSB_LSB_N << 11) |
(XBAR_ENABLE << 10) |
(DATAPATH_DISABLE << 6) |
(IQCORRECTION_DISABLE << 0);
up_dac_common #(
.COMMON_ID(6'h0),
.ID (ID),
.CONFIG(CONFIG),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DRP_DISABLE (1),
.USERPORTS_DISABLE (1),
.GPIO_DISABLE (1)
) i_up_dac_common (
.mmcm_rst (),
.dac_clk (link_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync),
.dac_ext_sync_arm (dac_ext_sync_arm),
.dac_ext_sync_disarm (dac_ext_sync_disarm),
.dac_ext_sync_manual_req (dac_ext_sync_manual_req),
.dac_sync_in_status (dac_sync_in_status),
.dac_frame (),
.dac_clksel (),
.dac_custom_wr(),
.dac_custom_rd(32'b0),
.dac_custom_control(),
.dac_status_if_busy(1'b0),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_dds_format),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (DATA_PATH_WIDTH),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (NUM_CHANNELS),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_dac_ce (),
.up_pps_rcounter ('h00),
.up_pps_status (1'b0),
.up_pps_irq_mask (),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
up_dac_channel #(
.COMMON_ID(6'h1 + i/16),
.CHANNEL_ID (i % 16),
.CHANNEL_NUMBER (i),
.DDS_PHASE_DW (DDS_PHASE_DW),
.USERPORTS_DISABLE (1),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.XBAR_ENABLE (XBAR_ENABLE)
) i_up_dac_channel (
.dac_clk (link_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_0[16*i+:16]),
.dac_dds_init_1 (dac_dds_init_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]),
.dac_dds_incr_1 (dac_dds_incr_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]),
.dac_dds_scale_2 (dac_dds_scale_1[16*i+:16]),
.dac_dds_init_2 (dac_dds_init_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]),
.dac_dds_incr_2 (dac_dds_incr_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]),
.dac_pat_data_1 (dac_pat_data_0[16*i+:16]),
.dac_pat_data_2 (dac_pat_data_1[16*i+:16]),
.dac_data_sel (dac_data_sel[4*i+:4]),
.dac_mask_enable (dac_mask_enable[i]),
.dac_iq_mode (),
.dac_iqcor_enb (dac_iqcor_enb[i]),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]),
.dac_src_chan_sel (dac_src_chan_sel[8*i+:8]),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i+1]),
.up_rreq (up_rreq_s),
.up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[i+1]),
.up_rack (up_rack_s[i+1]));
end
endgenerate
up_tpl_common #(
.COMMON_ID(2'h0), // Offset of regmap
.NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles
) i_up_tpl_dac (
.jesd_m (jesd_m),
.jesd_l (jesd_l),
.jesd_s (jesd_s),
.jesd_f (jesd_f),
.jesd_n (jesd_n),
.jesd_np (jesd_np),
.up_profile_sel (up_profile_sel),
// bus interface
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[NUM_CHANNELS+1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[NUM_CHANNELS+1]),
.up_rack (up_rack_s[NUM_CHANNELS+1]));
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/bd/bd.tcl
+47
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# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
DEV_PACKAGE \
SPEED_GRADE \
FPGA_FAMILY \
FPGA_TECHNOLOGY"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
adi_library/jesd204/ad_ip_jesd204_tpl_dac/component.xml
+1566
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adi_library/jesd204/ad_ip_jesd204_tpl_dac/gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl
+4
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# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_DDS_TYPE_ENABLEMENT {DATAPATH_DISABLE } {expr $DATAPATH_DISABLE == 0}
proc gen_USERPARAMETER_DDS_CORDIC_DW_ENABLEMENT {DATAPATH_DISABLE DDS_TYPE } {expr $DATAPATH_DISABLE == 0 && $DDS_TYPE == 1}
proc gen_USERPARAMETER_DDS_CORDIC_PHASE_DW_ENABLEMENT {DATAPATH_DISABLE DDS_TYPE } {expr $DATAPATH_DISABLE == 0 && $DDS_TYPE == 1}
adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py
Executable
+53
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#!/usr/bin/env python3
###############################################################################
## Copyright (C) 2018 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
import math
import os
import sys
path = os.path.dirname(sys.argv[0])
f = open(os.path.join(path, 'modes.txt'))
conv = {}
for l in f:
if l[0] == "#":
continue
x = l.split()
if len(x) == 0:
continue
if len(x) == 1:
name = x[0]
modes = []
conv[name] = modes
continue
modes.append(list(map(int, x)))
f.close()
for name, modes in conv.items():
f = open(os.path.join(path, '..', '{}.qprs'.format(name)), 'w')
f.write('<?xml version="1.0" encoding="UTF-8"?>\n<ip><presets version="17.1">\n')
for m in modes:
f.write('\t<preset name="{} Mode {:02d}" kind="ad_ip_jesd204_tpl_dac" version="All" description="{}">\n'.format(name, m[0], name))
f.write('\t\t<parameter name="PART" value="{}" />\n'.format(name))
f.write('\t\t<parameter name="NUM_CHANNELS" value="{}" />\n'.format(m[1]))
f.write('\t\t<parameter name="NUM_LANES" value="{}" />\n'.format(m[2]))
if math.gcd(m[4], m[3]) != 1:
f.write('\t\t<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />\n')
else:
f.write('\t\t<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />\n')
f.write('\t\t<parameter name="SAMPLES_PER_FRAME_MANUAL" value="{}" />\n'.format(m[3]))
f.write('\t\t<parameter name="CONVERTER_RESOLUTION" value="{}" />\n'.format(m[6]))
f.write('\t\t<parameter name="BITS_PER_SAMPLE" value="{}" />\n'.format(m[7]))
f.write('\t</preset>\n')
f.write('</presets></ip>\n')
f.close()
adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/modes.txt
+121
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# Mode M L S F HD N NP
AD9135
8 1 4 2 1 1 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
11 2 8 2 1 1 16 16
12 2 4 1 1 1 16 16
13 2 2 1 2 0 16 16
AD9136
8 1 4 2 1 1 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
11 2 8 2 1 1 16 16
12 2 4 1 1 1 16 16
13 2 2 1 2 0 16 16
AD9144
0 4 8 1 1 1 16 16
1 4 8 2 2 0 16 16
2 4 4 1 2 0 16 16
3 4 2 1 4 0 16 16
4 2 4 1 1 1 16 16
5 2 4 2 2 0 16 16
6 2 2 1 2 0 16 16
7 2 1 1 4 0 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
AD9152
4 2 4 1 1 1 16 16
5 2 4 2 2 0 16 16
6 2 2 1 2 0 16 16
7 2 1 1 4 0 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
AD9154
0 4 8 1 1 1 16 16
1 4 8 2 2 0 16 16
2 4 4 1 2 0 16 16
3 4 2 1 4 0 16 16
4 2 4 1 1 1 16 16
5 2 4 2 2 0 16 16
6 2 2 1 2 0 16 16
7 2 1 1 4 0 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
AD9161
1 2 1 1 4 1 16 16
2 2 2 2 2 1 16 16
3 2 3 3 4 1 16 16
4 2 4 1 1 1 16 16
6 2 6 3 2 1 16 16
8 2 8 2 1 1 16 16
AD9162
1 2 1 1 4 1 16 16
2 2 2 2 2 1 16 16
3 2 3 3 4 1 16 16
4 2 4 1 1 1 16 16
6 2 6 3 2 1 16 16
8 2 8 2 1 1 16 16
AD9163
1 2 1 1 4 1 16 16
2 2 2 2 2 1 16 16
3 2 3 3 4 1 16 16
4 2 4 1 1 1 16 16
6 2 6 3 2 1 16 16
8 2 8 2 1 1 16 16
AD9164
1 2 1 1 4 1 16 16
2 2 2 2 2 1 16 16
3 2 3 3 4 1 16 16
4 2 4 1 1 1 16 16
6 2 6 3 2 1 16 16
8 2 8 2 1 1 16 16
AD9171
0 2 1 1 4 1 16 16
3 2 2 1 2 1 16 16
5 2 1 1 3 1 12 12
AD9172
0 2 1 1 4 1 16 16
1 4 2 1 4 1 16 16
2 6 3 1 4 1 16 16
3 2 2 1 2 1 16 16
4 4 4 1 2 1 16 16
5 2 1 1 3 1 12 12
6 4 2 1 3 1 12 12
7 4 1 1 8 1 16 16
8 2 4 1 1 1 16 16
9 2 4 2 2 1 16 16
10 2 8 2 1 1 16 16
11 2 8 4 2 1 16 16
12 2 8 8 3 1 12 12
18 1 4 2 1 1 16 16
19 1 4 4 2 1 16 16
20 1 8 4 1 1 16 16
21 1 8 8 2 1 16 16
AD9173
0 2 1 1 4 1 16 16
1 4 2 1 4 1 16 16
2 6 3 1 4 1 16 16
3 2 2 1 2 1 16 16
4 4 4 1 2 1 16 16
5 2 1 1 3 1 12 12
6 4 2 1 3 1 12 12
7 4 1 1 8 1 16 16
8 2 4 1 1 1 16 16
9 2 4 2 2 1 16 16
13 2 4 1 1 1 11 16
14 2 4 2 2 1 11 16
15 2 8 2 1 1 11 16
16 2 8 4 2 1 11 16
17 2 8 8 3 1 11 12
adi_library/jesd204/ad_ip_jesd204_tpl_dac/temporary_case_dependencies.mk
+2
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CLEAN_TARGET += bd
CLEAN_TARGET += temporary_case_dependencies.mk
adi_library/jesd204/ad_ip_jesd204_tpl_dac/xgui/ad_ip_jesd204_tpl_dac_v1_0.tcl
+372
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# Loading additional proc with user specified bodies to compute parameter values.
source [file join [file dirname [file dirname [info script]]] gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl]
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "PADDING_TO_MSB_LSB_N" -parent ${Page_0}
#Adding Group
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}]
ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}
#Adding Group
set JESD204_Framer_Configuration [ipgui::add_group $IPINST -name "JESD204 Framer Configuration" -parent ${Page_0} -display_name {JESD204 Framer Cofiguration}]
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "NUM_CHANNELS" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "BITS_PER_SAMPLE" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "DMA_BITS_PER_SAMPLE" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "CONVERTER_RESOLUTION" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "SAMPLES_PER_FRAME" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "OCTETS_PER_BEAT" -parent ${JESD204_Framer_Configuration} -widget comboBox
#Adding Group
set Datapath_Configuration [ipgui::add_group $IPINST -name "Datapath Configuration" -parent ${Page_0} -display_name {Datapath Cofiguration}]
ipgui::add_param $IPINST -name "DATAPATH_DISABLE" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "EXT_SYNC" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "IQCORRECTION_DISABLE" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "XBAR_ENABLE" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "DDS_TYPE" -parent ${Datapath_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "DDS_PHASE_DW" -parent ${Datapath_Configuration}
ipgui::add_param $IPINST -name "DDS_CORDIC_DW" -parent ${Datapath_Configuration}
ipgui::add_param $IPINST -name "DDS_CORDIC_PHASE_DW" -parent ${Datapath_Configuration}
#Adding Group
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
}
proc update_PARAM_VALUE.DDS_CORDIC_DW { PARAM_VALUE.DDS_CORDIC_DW PARAM_VALUE.DATAPATH_DISABLE PARAM_VALUE.DDS_TYPE } {
# Procedure called to update DDS_CORDIC_DW when any of the dependent parameters in the arguments change
set DDS_CORDIC_DW ${PARAM_VALUE.DDS_CORDIC_DW}
set DATAPATH_DISABLE ${PARAM_VALUE.DATAPATH_DISABLE}
set DDS_TYPE ${PARAM_VALUE.DDS_TYPE}
set values(DATAPATH_DISABLE) [get_property value $DATAPATH_DISABLE]
set values(DDS_TYPE) [get_property value $DDS_TYPE]
if { [gen_USERPARAMETER_DDS_CORDIC_DW_ENABLEMENT $values(DATAPATH_DISABLE) $values(DDS_TYPE)] } {
set_property enabled true $DDS_CORDIC_DW
} else {
set_property enabled false $DDS_CORDIC_DW
}
}
proc validate_PARAM_VALUE.DDS_CORDIC_DW { PARAM_VALUE.DDS_CORDIC_DW } {
# Procedure called to validate DDS_CORDIC_DW
return true
}
proc update_PARAM_VALUE.DDS_CORDIC_PHASE_DW { PARAM_VALUE.DDS_CORDIC_PHASE_DW PARAM_VALUE.DATAPATH_DISABLE PARAM_VALUE.DDS_TYPE } {
# Procedure called to update DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
set DDS_CORDIC_PHASE_DW ${PARAM_VALUE.DDS_CORDIC_PHASE_DW}
set DATAPATH_DISABLE ${PARAM_VALUE.DATAPATH_DISABLE}
set DDS_TYPE ${PARAM_VALUE.DDS_TYPE}
set values(DATAPATH_DISABLE) [get_property value $DATAPATH_DISABLE]
set values(DDS_TYPE) [get_property value $DDS_TYPE]
if { [gen_USERPARAMETER_DDS_CORDIC_PHASE_DW_ENABLEMENT $values(DATAPATH_DISABLE) $values(DDS_TYPE)] } {
set_property enabled true $DDS_CORDIC_PHASE_DW
} else {
set_property enabled false $DDS_CORDIC_PHASE_DW
}
}
proc validate_PARAM_VALUE.DDS_CORDIC_PHASE_DW { PARAM_VALUE.DDS_CORDIC_PHASE_DW } {
# Procedure called to validate DDS_CORDIC_PHASE_DW
return true
}
proc update_PARAM_VALUE.DDS_TYPE { PARAM_VALUE.DDS_TYPE PARAM_VALUE.DATAPATH_DISABLE } {
# Procedure called to update DDS_TYPE when any of the dependent parameters in the arguments change
set DDS_TYPE ${PARAM_VALUE.DDS_TYPE}
set DATAPATH_DISABLE ${PARAM_VALUE.DATAPATH_DISABLE}
set values(DATAPATH_DISABLE) [get_property value $DATAPATH_DISABLE]
if { [gen_USERPARAMETER_DDS_TYPE_ENABLEMENT $values(DATAPATH_DISABLE)] } {
set_property enabled true $DDS_TYPE
} else {
set_property enabled false $DDS_TYPE
}
}
proc validate_PARAM_VALUE.DDS_TYPE { PARAM_VALUE.DDS_TYPE } {
# Procedure called to validate DDS_TYPE
return true
}
proc update_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
# Procedure called to update BITS_PER_SAMPLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
# Procedure called to validate BITS_PER_SAMPLE
return true
}
proc update_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
# Procedure called to update CONVERTER_RESOLUTION when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
# Procedure called to validate CONVERTER_RESOLUTION
return true
}
proc update_PARAM_VALUE.DATAPATH_DISABLE { PARAM_VALUE.DATAPATH_DISABLE } {
# Procedure called to update DATAPATH_DISABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DATAPATH_DISABLE { PARAM_VALUE.DATAPATH_DISABLE } {
# Procedure called to validate DATAPATH_DISABLE
return true
}
proc update_PARAM_VALUE.DDS_PHASE_DW { PARAM_VALUE.DDS_PHASE_DW } {
# Procedure called to update DDS_PHASE_DW when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DDS_PHASE_DW { PARAM_VALUE.DDS_PHASE_DW } {
# Procedure called to validate DDS_PHASE_DW
return true
}
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to validate DEV_PACKAGE
return true
}
proc update_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } {
# Procedure called to update DMA_BITS_PER_SAMPLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } {
# Procedure called to validate DMA_BITS_PER_SAMPLE
return true
}
proc update_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } {
# Procedure called to update EXT_SYNC when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } {
# Procedure called to validate EXT_SYNC
return true
}
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to validate FPGA_FAMILY
return true
}
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to validate FPGA_TECHNOLOGY
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.IQCORRECTION_DISABLE { PARAM_VALUE.IQCORRECTION_DISABLE } {
# Procedure called to update IQCORRECTION_DISABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IQCORRECTION_DISABLE { PARAM_VALUE.IQCORRECTION_DISABLE } {
# Procedure called to validate IQCORRECTION_DISABLE
return true
}
proc update_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
# Procedure called to update NUM_CHANNELS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
# Procedure called to validate NUM_CHANNELS
return true
}
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to validate NUM_LANES
return true
}
proc update_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
# Procedure called to update OCTETS_PER_BEAT when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
# Procedure called to validate OCTETS_PER_BEAT
return true
}
proc update_PARAM_VALUE.PADDING_TO_MSB_LSB_N { PARAM_VALUE.PADDING_TO_MSB_LSB_N } {
# Procedure called to update PADDING_TO_MSB_LSB_N when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PADDING_TO_MSB_LSB_N { PARAM_VALUE.PADDING_TO_MSB_LSB_N } {
# Procedure called to validate PADDING_TO_MSB_LSB_N
return true
}
proc update_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
# Procedure called to update SAMPLES_PER_FRAME when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
# Procedure called to validate SAMPLES_PER_FRAME
return true
}
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to validate SPEED_GRADE
return true
}
proc update_PARAM_VALUE.XBAR_ENABLE { PARAM_VALUE.XBAR_ENABLE } {
# Procedure called to update XBAR_ENABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.XBAR_ENABLE { PARAM_VALUE.XBAR_ENABLE } {
# Procedure called to validate XBAR_ENABLE
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
}
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
}
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
}
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
}
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
}
proc update_MODELPARAM_VALUE.NUM_CHANNELS { MODELPARAM_VALUE.NUM_CHANNELS PARAM_VALUE.NUM_CHANNELS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_CHANNELS}] ${MODELPARAM_VALUE.NUM_CHANNELS}
}
proc update_MODELPARAM_VALUE.SAMPLES_PER_FRAME { MODELPARAM_VALUE.SAMPLES_PER_FRAME PARAM_VALUE.SAMPLES_PER_FRAME } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_FRAME}] ${MODELPARAM_VALUE.SAMPLES_PER_FRAME}
}
proc update_MODELPARAM_VALUE.CONVERTER_RESOLUTION { MODELPARAM_VALUE.CONVERTER_RESOLUTION PARAM_VALUE.CONVERTER_RESOLUTION } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CONVERTER_RESOLUTION}] ${MODELPARAM_VALUE.CONVERTER_RESOLUTION}
}
proc update_MODELPARAM_VALUE.BITS_PER_SAMPLE { MODELPARAM_VALUE.BITS_PER_SAMPLE PARAM_VALUE.BITS_PER_SAMPLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.BITS_PER_SAMPLE}
}
proc update_MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE { MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE PARAM_VALUE.DMA_BITS_PER_SAMPLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DMA_BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE}
}
proc update_MODELPARAM_VALUE.PADDING_TO_MSB_LSB_N { MODELPARAM_VALUE.PADDING_TO_MSB_LSB_N PARAM_VALUE.PADDING_TO_MSB_LSB_N } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PADDING_TO_MSB_LSB_N}] ${MODELPARAM_VALUE.PADDING_TO_MSB_LSB_N}
}
proc update_MODELPARAM_VALUE.OCTETS_PER_BEAT { MODELPARAM_VALUE.OCTETS_PER_BEAT PARAM_VALUE.OCTETS_PER_BEAT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_BEAT}] ${MODELPARAM_VALUE.OCTETS_PER_BEAT}
}
proc update_MODELPARAM_VALUE.DDS_TYPE { MODELPARAM_VALUE.DDS_TYPE PARAM_VALUE.DDS_TYPE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DDS_TYPE}] ${MODELPARAM_VALUE.DDS_TYPE}
}
proc update_MODELPARAM_VALUE.DDS_CORDIC_DW { MODELPARAM_VALUE.DDS_CORDIC_DW PARAM_VALUE.DDS_CORDIC_DW } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DDS_CORDIC_DW}
}
proc update_MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW PARAM_VALUE.DDS_CORDIC_PHASE_DW } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW}
}
proc update_MODELPARAM_VALUE.DDS_PHASE_DW { MODELPARAM_VALUE.DDS_PHASE_DW PARAM_VALUE.DDS_PHASE_DW } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DDS_PHASE_DW}] ${MODELPARAM_VALUE.DDS_PHASE_DW}
}
proc update_MODELPARAM_VALUE.DATAPATH_DISABLE { MODELPARAM_VALUE.DATAPATH_DISABLE PARAM_VALUE.DATAPATH_DISABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DATAPATH_DISABLE}
}
proc update_MODELPARAM_VALUE.IQCORRECTION_DISABLE { MODELPARAM_VALUE.IQCORRECTION_DISABLE PARAM_VALUE.IQCORRECTION_DISABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IQCORRECTION_DISABLE}] ${MODELPARAM_VALUE.IQCORRECTION_DISABLE}
}
proc update_MODELPARAM_VALUE.EXT_SYNC { MODELPARAM_VALUE.EXT_SYNC PARAM_VALUE.EXT_SYNC } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.EXT_SYNC}] ${MODELPARAM_VALUE.EXT_SYNC}
}
proc update_MODELPARAM_VALUE.XBAR_ENABLE { MODELPARAM_VALUE.XBAR_ENABLE PARAM_VALUE.XBAR_ENABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.XBAR_ENABLE}] ${MODELPARAM_VALUE.XBAR_ENABLE}
}
adi_library/jesd204/axi_jesd204_common/Makefile
+18
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@@ -0,0 +1,18 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_jesd204_common
GENERIC_DEPS += jesd204_up_common.v
GENERIC_DEPS += jesd204_up_sysref.v
XILINX_DEPS += ../../common/up_clock_mon.v
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += axi_jesd204_common_ip.tcl
XILINX_LIB_DEPS += util_cdc
include ../../scripts/library.mk
adi_library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr
+420
View File
@@ -0,0 +1,420 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="eaddf6ca246c4a3c8aced5d95e931dbe"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../xilinx/common/up_clock_mon_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../common/up_clock_mon.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/jesd204_up_common.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/jesd204_up_sysref.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl
+31
View File
@@ -0,0 +1,31 @@
###############################################################################
## Copyright (C) 2016, 2017, 2019, 2022, 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_jesd204_common
add_files -fileset [get_filesets sources_1] [list \
"../../xilinx/common/up_clock_mon_constr.xdc" \
"../../common/up_clock_mon.v" \
"jesd204_up_common.v" \
"jesd204_up_sysref.v" \
]
set_property source_mgmt_mode DisplayOnly [current_project]
adi_ip_properties_lite axi_jesd204_common
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
set_property display_name "ADI AXI JESD204B Common Library" [ipx::current_core]
set_property description "ADI AXI JESD204B Common Library" [ipx::current_core]
set_property hide_in_gui {1} [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/jesd204/axi_jesd204_common/component.xml
+388
View File
@@ -0,0 +1,388 @@
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adi_library/jesd204/axi_jesd204_common/jesd204_up_common.v
Executable
+399
View File
@@ -0,0 +1,399 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module jesd204_up_common #(
parameter PCORE_VERSION = 0,
parameter PCORE_MAGIC = 0,
parameter ID = 0,
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter DATA_PATH_WIDTH_LOG2 = 2,
parameter NUM_IRQS = 1,
parameter EXTRA_CFG_WIDTH = 1,
parameter DEV_EXTRA_CFG_WIDTH = 1,
parameter ENABLE_LINK_STATS = 0
) (
input up_clk,
input ext_resetn,
output up_reset,
output up_reset_synchronizer,
input core_clk,
input core_reset_ext,
output core_reset,
input device_clk,
output device_reset,
input [11:0] up_raddr,
output reg [31:0] up_rdata,
input up_wreq,
input [11:0] up_waddr,
input [31:0] up_wdata,
input [EXTRA_CFG_WIDTH-1:0] up_extra_cfg,
input [DEV_EXTRA_CFG_WIDTH-1:0] up_dev_extra_cfg,
input [NUM_IRQS-1:0] up_irq_trigger,
output reg irq,
output up_cfg_is_writeable,
output reg [NUM_LANES-1:0] core_cfg_lanes_disable = {NUM_LANES{1'b0}},
output reg [NUM_LINKS-1:0] core_cfg_links_disable = {NUM_LINKS{1'b0}},
output reg [9:0] core_cfg_octets_per_multiframe = 'h00,
output reg [7:0] core_cfg_octets_per_frame = 'h00,
output reg core_cfg_disable_scrambler = 'h00,
output reg core_cfg_disable_char_replacement = 'h00,
output reg [EXTRA_CFG_WIDTH-1:0] core_extra_cfg = 'h00,
output reg [DEV_EXTRA_CFG_WIDTH-1:0] device_extra_cfg = 'h00,
output reg [9:0] device_cfg_octets_per_multiframe = 'h00,
output reg [7:0] device_cfg_octets_per_frame = 'h00,
output reg [7:0] device_cfg_beats_per_multiframe = 'h00,
input [31:0] status_synth_params0,
input [31:0] status_synth_params1,
input [31:0] status_synth_params2
);
reg [31:0] up_scratch = 32'h00000000;
reg [7:0] up_cfg_octets_per_frame = 'h00;
reg [9:0] up_cfg_octets_per_multiframe = {DATA_PATH_WIDTH_LOG2{1'b1}};
reg [7:0] up_cfg_beats_per_multiframe = 'h00;
reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}};
reg [NUM_LINKS-1:0] up_cfg_links_disable = {NUM_LINKS{1'b0}};
reg up_cfg_disable_char_replacement = 1'b0;
reg up_cfg_disable_scrambler = 1'b0;
/* Reset for the register map */
reg [2:0] up_reset_vector = 3'b111;
assign up_reset = up_reset_vector[0];
/* Reset signal generation for the JESD core */
reg [4:0] core_reset_vector = 5'b11111;
assign core_reset = core_reset_vector[0];
reg [4:0] device_reset_vector = 5'b11111;
assign device_reset = device_reset_vector[0];
/* Transfer the reset signal back to the up domain, used to keep the
* synchronizers in reset until the core is ready. This is done in order to
* prevent bogus data to propagate to the register map. */
reg [1:0] up_reset_synchronizer_vector = 2'b11;
assign up_reset_synchronizer = up_reset_synchronizer_vector[0];
/*
* Synchronize the external core reset to the register map domain so the status
* can be shown in the register map. This is useful for debugging.
*/
reg [1:0] up_core_reset_ext_synchronizer_vector = 2'b11;
wire up_core_reset_ext;
assign up_core_reset_ext = up_core_reset_ext_synchronizer_vector[0];
/* Transfer two cycles before the core comes out of reset */
wire core_cfg_transfer_en;
assign core_cfg_transfer_en = core_reset_vector[2] ^ core_reset_vector[1];
wire device_cfg_transfer_en;
assign device_cfg_transfer_en = device_reset_vector[2] ^ device_reset_vector[1];
reg up_reset_core = 1'b1;
assign up_cfg_is_writeable = up_reset_core;
always @(posedge up_clk or negedge ext_resetn) begin
if (ext_resetn == 1'b0) begin
up_reset_vector <= 3'b111;
end else begin
up_reset_vector <= {1'b0,up_reset_vector[2:1]};
end
end
wire core_reset_all = up_reset_core | core_reset_ext;
always @(posedge core_clk or posedge core_reset_all) begin
if (core_reset_all == 1'b1) begin
core_reset_vector <= 5'b11111;
end else begin
core_reset_vector <= {1'b0,core_reset_vector[4:1]};
end
end
always @(posedge device_clk or posedge core_reset_all) begin
if (core_reset_all == 1'b1) begin
device_reset_vector <= 5'b11111;
end else begin
device_reset_vector <= {1'b0,device_reset_vector[4:1]};
end
end
always @(posedge up_clk or posedge core_reset) begin
if (core_reset == 1'b1) begin
up_reset_synchronizer_vector <= 2'b11;
end else begin
up_reset_synchronizer_vector <= {1'b0,up_reset_synchronizer_vector[1]};
end
end
always @(posedge up_clk or posedge core_reset_ext) begin
if (core_reset_ext == 1'b1) begin
up_core_reset_ext_synchronizer_vector <= 2'b11;
end else begin
up_core_reset_ext_synchronizer_vector <= {1'b0,up_core_reset_ext_synchronizer_vector[1]};
end
end
always @(posedge core_clk) begin
if (core_cfg_transfer_en == 1'b1) begin
core_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe;
core_cfg_octets_per_frame <= up_cfg_octets_per_frame;
core_cfg_lanes_disable <= up_cfg_lanes_disable;
core_cfg_links_disable <= up_cfg_links_disable;
core_cfg_disable_scrambler <= up_cfg_disable_scrambler;
core_cfg_disable_char_replacement <= up_cfg_disable_char_replacement;
core_extra_cfg <= up_extra_cfg;
end
end
always @(posedge device_clk) begin
if (device_cfg_transfer_en == 1'b1) begin
device_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe;
device_cfg_octets_per_frame <= up_cfg_octets_per_frame;
device_cfg_beats_per_multiframe <= up_cfg_beats_per_multiframe;
device_extra_cfg <= up_dev_extra_cfg;
end
end
/* Interupt handling */
reg [NUM_IRQS-1:0] up_irq_enable = {NUM_IRQS{1'b0}};
reg [NUM_IRQS-1:0] up_irq_source = 'h00;
reg [NUM_IRQS-1:0] up_irq_clear;
wire [NUM_IRQS-1:0] up_irq_pending;
assign up_irq_pending = up_irq_source & up_irq_enable;
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
irq <= 1'b0;
end else begin
irq <= |up_irq_pending;
end
end
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
up_irq_source <= 'h00;
end else begin
up_irq_source <= (up_irq_source & ~up_irq_clear) | up_irq_trigger;
end
end
/* Count link enable */
wire [8*16-1:0] up_irq_event_cnt_bus;
wire [15:0] up_link_enable_cnt_s;
genvar i;
generate if (ENABLE_LINK_STATS == 1) begin : g_link_stats
reg [15:0] up_link_enable_cnt = 'h0;
reg up_reset_core_d1 = 'b1;
wire up_stat_clear;
assign up_stat_clear = (up_waddr == 12'h0b0 && up_wreq && up_wdata[0]);
always @(posedge up_clk) begin
up_reset_core_d1 <= up_reset_core;
if (up_stat_clear) begin
up_link_enable_cnt <= 'h0;
end else begin
if (~up_reset_core & up_reset_core_d1) begin
up_link_enable_cnt <= up_link_enable_cnt + 16'd1;
end
end
end
assign up_link_enable_cnt_s = up_link_enable_cnt;
/* Count IRQ events for max 8 interrupt sources */
for (i = 0; i < NUM_IRQS; i=i+1) begin : irq_cnt
reg [15:0] up_irq_event_cnt = 'h0;
always @(posedge up_clk) begin
if (up_stat_clear) begin
up_irq_event_cnt <= 'h0;
end else if (up_irq_trigger[i]) begin
up_irq_event_cnt <= up_irq_event_cnt + 16'd1;
end
end
assign up_irq_event_cnt_bus[i*16 +: 16] = up_irq_event_cnt;
end
end else begin : g_no_link_stats
assign up_irq_event_cnt_bus = 'h0;
assign up_link_enable_cnt_s = 'h0;
end
endgenerate
wire [20:0] clk_mon_count;
wire [20:0] device_clk_mon_count;
always @(*) begin
case (up_raddr)
/* Standard registers */
12'h000: up_rdata = PCORE_VERSION;
12'h001: up_rdata = ID;
12'h002: up_rdata = up_scratch;
12'h003: up_rdata = PCORE_MAGIC;
/* Core configuration */
12'h004: up_rdata = status_synth_params0;
12'h005: up_rdata = status_synth_params1;
12'h006: up_rdata = status_synth_params2;
/* 0x07-0x0f reserved for future use */
/* 0x10-0x1f reserved for core specific HDL configuration information */
/* IRQ block */
12'h020: up_rdata = up_irq_enable;
12'h021: up_rdata = up_irq_pending;
12'h022: up_rdata = up_irq_source;
/* 0x23-0x30 reserved for future use */
/* JESD common control */
12'h030: up_rdata = up_reset_core;
12'h031: up_rdata = {up_core_reset_ext, up_reset_synchronizer}; /* core ready */
12'h032: up_rdata = {11'h00, clk_mon_count}; /* Make it 16.16 */
12'h033: up_rdata = {11'h00, device_clk_mon_count}; /* Make it 16.16 */
/* 0x34-0x34 reserver for future use */
12'h080: up_rdata = up_cfg_lanes_disable;
/* 0x82-0x83 reserved for future lane disable bits (max 128 lanes) */
12'h084: up_rdata = {
/* 24-31 */ 8'h00, /* Reserved for future extensions of octets_per_frame */
/* 16-23 */ up_cfg_octets_per_frame,
/* 10-15 */ 6'b000000, /* Reserved for future extensions of beats_per_multiframe */
/* 00-09 */ up_cfg_octets_per_multiframe
};
12'h85: up_rdata = {
/* 02-31 */ 30'h00, /* Reserved for future additions */
/* 01 */ up_cfg_disable_char_replacement, /* Disable character replacement */
/* 00 */ up_cfg_disable_scrambler /* Disable scrambler */
};
12'h086: up_rdata = up_cfg_links_disable;
12'h087: up_rdata = up_cfg_beats_per_multiframe;
/* 0x88-0x8f reserved for future use */
/* 0x90-0x9f reserved for core specific configuration options */
/* 0xb0 Stat control */
12'h0b1: up_rdata = up_link_enable_cnt_s;
/* 0xb4-0xb7 IRQ Stat, max 8 interrupt sources */
12'h0b4: up_rdata = up_irq_event_cnt_bus[0*32 +: 32];
12'h0b5: up_rdata = up_irq_event_cnt_bus[1*32 +: 32];
12'h0b6: up_rdata = up_irq_event_cnt_bus[2*32 +: 32];
12'h0b7: up_rdata = up_irq_event_cnt_bus[3*32 +: 32];
default: up_rdata = 'h00;
endcase
end
/* IRQ pending register is write-1-to-clear */
always @(*) begin
if (up_wreq == 1'b1 && up_waddr == 12'h21) begin
up_irq_clear = up_wdata[NUM_IRQS-1:0];
end else begin
up_irq_clear = {NUM_IRQS{1'b0}};
end
end
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
up_scratch <= 'h00;
up_irq_enable <= {NUM_IRQS{1'b0}};
up_reset_core <= 1'b1;
up_cfg_octets_per_frame <= 'h00;
up_cfg_octets_per_multiframe <= {DATA_PATH_WIDTH_LOG2{1'b1}};
up_cfg_lanes_disable <= {NUM_LANES{1'b0}};
up_cfg_links_disable <= {NUM_LINKS{1'b0}};
up_cfg_beats_per_multiframe <= 'h00;
up_cfg_disable_char_replacement <= 1'b0;
up_cfg_disable_scrambler <= 1'b0;
end else if (up_wreq == 1'b1) begin
case (up_waddr)
/* Standard registers */
12'h002: up_scratch <= up_wdata;
/* IRQ block */
12'h020: up_irq_enable <= up_wdata[NUM_IRQS-1:0];
/* JESD common control */
12'h030: up_reset_core <= up_wdata[0];
endcase
/*
* The configuration needs to be static while the core is
* active. To enforce this writes to configuration registers
* will be ignored while the core is out of reset.
*/
if (up_cfg_is_writeable == 1'b1) begin
case (up_waddr)
12'h080: begin
up_cfg_lanes_disable <= up_wdata[NUM_LANES-1:0];
end
12'h084: begin
up_cfg_octets_per_frame <= up_wdata[23:16];
up_cfg_octets_per_multiframe <= {up_wdata[9:DATA_PATH_WIDTH_LOG2],
{DATA_PATH_WIDTH_LOG2{1'b1}}};
end
12'h085: begin
up_cfg_disable_char_replacement <= up_wdata[1];
up_cfg_disable_scrambler <= up_wdata[0];
end
12'h086: begin
up_cfg_links_disable <= up_wdata[NUM_LINKS-1:0];
end
12'h087: begin
up_cfg_beats_per_multiframe <= up_wdata[7:0];
end
endcase
end
end
end
up_clock_mon #(
.TOTAL_WIDTH(21)
) i_clock_mon (
.up_rstn(~up_reset),
.up_clk(up_clk),
.up_d_count(clk_mon_count),
.d_rst(1'b0),
.d_clk(core_clk));
up_clock_mon #(
.TOTAL_WIDTH(21)
) i_dev_clock_mon (
.up_rstn(~up_reset),
.up_clk(up_clk),
.up_d_count(device_clk_mon_count),
.d_rst(1'b0),
.d_clk(device_clk));
endmodule
adi_library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
Executable
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved.
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module jesd204_up_sysref (
input up_clk,
input up_reset,
input core_clk,
input device_clk,
input [11:0] up_raddr,
output reg [31:0] up_rdata,
input up_wreq,
input [11:0] up_waddr,
input [31:0] up_wdata,
input up_cfg_is_writeable,
output reg up_cfg_sysref_oneshot,
output reg [7:0] up_cfg_lmfc_offset,
output reg up_cfg_sysref_disable,
input device_event_sysref_alignment_error,
input device_event_sysref_edge
);
reg [1:0] up_sysref_status;
reg [1:0] up_sysref_status_clear;
wire [1:0] up_sysref_event;
sync_event #(
.NUM_OF_EVENTS(2)
) i_cdc_sysref_event (
.in_clk(device_clk),
.in_event({
device_event_sysref_alignment_error,
device_event_sysref_edge
}),
.out_clk(up_clk),
.out_event(up_sysref_event));
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
up_sysref_status <= 2'b00;
end else begin
up_sysref_status <= (up_sysref_status & ~up_sysref_status_clear) | up_sysref_event;
end
end
always @(*) begin
case (up_raddr)
/* JESD SYSREF configuraton */
12'h040: up_rdata = {
/* 02-31 */ 30'h00, /* Reserved for future use */
/* 01 */ up_cfg_sysref_oneshot,
/* 00 */ up_cfg_sysref_disable
};
12'h041: up_rdata = {
/* 10-31 */ 22'h00, /* Reserved for future use */
/* 02-09 */ up_cfg_lmfc_offset,
/* 00-01 */ 2'b00 /* data path alignment for cfg_lmfc_offset */
};
12'h042: up_rdata = {
/* 02-31 */ 30'h00,
/* 00-01 */ up_sysref_status
};
default: up_rdata = 32'h00000000;
endcase
end
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
up_cfg_sysref_oneshot <= 1'b0;
up_cfg_lmfc_offset <= 'h00;
up_cfg_sysref_disable <= 1'b0;
end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
case (up_waddr)
/* JESD SYSREF configuraton */
12'h040: begin
up_cfg_sysref_oneshot <= up_wdata[1];
up_cfg_sysref_disable <= up_wdata[0];
end
12'h041: begin
/* Must be aligned to data path width */
up_cfg_lmfc_offset <= up_wdata;
end
endcase
end
end
always @(*) begin
if (up_wreq == 1'b1 && up_waddr == 12'h042) begin
up_sysref_status_clear = up_wdata[1:0];
end else begin
up_sysref_status_clear = 2'b00;
end
end
endmodule
adi_library/jesd204/axi_jesd204_common/xgui/jesd204_up_sysref_v1_0.tcl
+10
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
ipgui::add_page $IPINST -name "Page 0"
}
adi_library/jesd204/axi_jesd204_rx/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_jesd204_rx
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += axi_jesd204_rx.v
GENERIC_DEPS += jesd204_up_ilas_mem.v
GENERIC_DEPS += jesd204_up_rx.v
GENERIC_DEPS += jesd204_up_rx_lane.v
XILINX_DEPS += axi_jesd204_rx_constr.xdc
XILINX_DEPS += axi_jesd204_rx_ip.tcl
XILINX_DEPS += axi_jesd204_rx_ooc.ttcl
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
XILINX_LIB_DEPS += jesd204/axi_jesd204_common
XILINX_INTERFACE_DEPS += jesd204/interfaces
INTEL_DEPS += ../../common/up_clock_mon.v
INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../../util_cdc/sync_data.v
INTEL_DEPS += ../../util_cdc/sync_event.v
INTEL_DEPS += ../axi_jesd204_common/jesd204_up_common.v
INTEL_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v
INTEL_DEPS += axi_jesd204_rx_constr.sdc
INTEL_DEPS += axi_jesd204_rx_hw.tcl
include ../../scripts/library.mk
adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
Executable
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_jesd204_rx #(
parameter ID = 0,
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
parameter ENABLE_LINK_STATS = 0,
parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4
) (
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [13:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [13:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
output irq,
input core_clk,
input core_reset_ext,
output core_reset,
input device_clk,
output device_reset,
output [NUM_LANES-1:0] core_cfg_lanes_disable,
output [NUM_LINKS-1:0] core_cfg_links_disable,
output [9:0] core_cfg_octets_per_multiframe,
output [7:0] core_cfg_octets_per_frame,
output core_cfg_disable_scrambler,
output core_cfg_disable_char_replacement,
output [7:0] core_cfg_frame_align_err_threshold,
output [9:0] device_cfg_octets_per_multiframe,
output [7:0] device_cfg_octets_per_frame,
output [7:0] device_cfg_beats_per_multiframe,
output [7:0] device_cfg_lmfc_offset,
output device_cfg_sysref_oneshot,
output device_cfg_sysref_disable,
output device_cfg_buffer_early_release,
output [7:0] device_cfg_buffer_delay,
input [NUM_LANES-1:0] core_ilas_config_valid,
input [2*NUM_LANES-1:0] core_ilas_config_addr,
input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] core_ilas_config_data,
input device_event_sysref_alignment_error,
input device_event_sysref_edge,
input core_event_frame_alignment_error,
input core_event_unexpected_lane_state_error,
output [6:0] core_ctrl_err_statistics_mask,
output core_ctrl_err_statistics_reset,
input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
input [1:0] core_status_ctrl_state,
input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
input [3*NUM_LANES-1:0] core_status_lane_emb_state,
input [NUM_LANES-1:0] core_status_lane_ifs_ready,
input [14*NUM_LANES-1:0] core_status_lane_latency,
input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt,
input [31:0] status_synth_params0,
input [31:0] status_synth_params1,
input [31:0] status_synth_params2
);
localparam PCORE_VERSION = 32'h00010761; // 1.07.a
localparam PCORE_MAGIC = 32'h32303452; // 204R
/* Register interface signals */
reg [31:0] up_rdata = 'h0;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg up_rreq_d1 = 1'b0;
wire up_wreq;
wire up_rreq;
wire [31:0] up_wdata;
wire [11:0] up_waddr;
wire [11:0] up_raddr;
wire [31:0] up_rdata_common;
wire [31:0] up_rdata_sysref;
wire [31:0] up_rdata_rx;
wire [4:0] up_irq_trigger;
wire up_cfg_is_writeable;
wire up_cfg_sysref_oneshot;
wire up_cfg_sysref_disable;
wire up_cfg_buffer_early_release;
wire [7:0] up_cfg_buffer_delay;
wire [7:0] up_cfg_lmfc_offset;
wire [7:0] up_cfg_frame_align_err_threshold;
wire up_reset;
wire up_reset_synchronizer;
wire up_event_frame_alignment_error;
wire up_event_unexpected_lane_state_error;
sync_event #(
.NUM_OF_EVENTS (2)
) i_sync_frame_align_err (
.in_clk(core_clk),
.in_event({core_event_unexpected_lane_state_error,
core_event_frame_alignment_error}),
.out_clk(s_axi_aclk),
.out_event({up_event_unexpected_lane_state_error,
up_event_frame_alignment_error}));
assign up_irq_trigger = {3'b0,
up_event_unexpected_lane_state_error,
up_event_frame_alignment_error} &
{5{~up_cfg_is_writeable}};
up_axi #(
.AXI_ADDRESS_WIDTH (14)
) i_up_axi (
.up_rstn(~up_reset),
.up_clk(s_axi_aclk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
jesd204_up_common #(
.PCORE_VERSION(PCORE_VERSION),
.PCORE_MAGIC(PCORE_MAGIC),
.ID(ID),
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS),
.NUM_IRQS(5),
.EXTRA_CFG_WIDTH(8),
.DEV_EXTRA_CFG_WIDTH(19),
.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
) i_up_common (
.up_clk(s_axi_aclk),
.ext_resetn(s_axi_aresetn),
.up_reset(up_reset),
.up_reset_synchronizer(up_reset_synchronizer),
.core_clk(core_clk),
.core_reset_ext(core_reset_ext),
.core_reset(core_reset),
.device_clk(device_clk),
.device_reset(device_reset),
.up_raddr(up_raddr),
.up_rdata(up_rdata_common),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_cfg_is_writeable(up_cfg_is_writeable),
.up_irq_trigger(up_irq_trigger),
.irq(irq),
.core_cfg_octets_per_multiframe(core_cfg_octets_per_multiframe),
.core_cfg_octets_per_frame(core_cfg_octets_per_frame),
.core_cfg_lanes_disable(core_cfg_lanes_disable),
.core_cfg_links_disable(core_cfg_links_disable),
.core_cfg_disable_scrambler(core_cfg_disable_scrambler),
.core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
.up_extra_cfg({
/* 00-07 */ up_cfg_frame_align_err_threshold
}),
.core_extra_cfg({
/* 00-07 */ core_cfg_frame_align_err_threshold
}),
.device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
.device_cfg_octets_per_frame(device_cfg_octets_per_frame),
.device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe),
.up_dev_extra_cfg({
/* 18 */ up_cfg_sysref_disable,
/* 17 */ up_cfg_sysref_oneshot,
/* 16 */ up_cfg_buffer_early_release,
/* 15-08 */ up_cfg_buffer_delay,
/* 00-07 */ up_cfg_lmfc_offset
}),
.device_extra_cfg({
/* 18 */ device_cfg_sysref_disable,
/* 17 */ device_cfg_sysref_oneshot,
/* 16 */ device_cfg_buffer_early_release,
/* 15-08 */ device_cfg_buffer_delay,
/* 00-07 */ device_cfg_lmfc_offset
}),
.status_synth_params0(status_synth_params0),
.status_synth_params1(status_synth_params1),
.status_synth_params2(status_synth_params2));
jesd204_up_sysref i_up_sysref (
.up_clk(s_axi_aclk),
.up_reset(up_reset),
.core_clk(core_clk),
.device_clk(device_clk),
.device_event_sysref_edge(device_event_sysref_edge),
.device_event_sysref_alignment_error(device_event_sysref_alignment_error),
.up_raddr(up_raddr),
.up_rdata(up_rdata_sysref),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_cfg_is_writeable(up_cfg_is_writeable),
.up_cfg_lmfc_offset(up_cfg_lmfc_offset),
.up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
.up_cfg_sysref_disable(up_cfg_sysref_disable));
jesd204_up_rx #(
.NUM_LANES(NUM_LANES),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_up_rx (
.up_clk(s_axi_aclk),
.up_reset(up_reset),
.up_reset_synchronizer(up_reset_synchronizer),
.core_clk(core_clk),
.core_reset(core_reset),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata_rx),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_cfg_is_writeable(up_cfg_is_writeable),
.up_cfg_buffer_early_release(up_cfg_buffer_early_release),
.up_cfg_buffer_delay(up_cfg_buffer_delay),
.up_cfg_frame_align_err_threshold(up_cfg_frame_align_err_threshold),
.core_ctrl_err_statistics_reset(core_ctrl_err_statistics_reset),
.core_ctrl_err_statistics_mask(core_ctrl_err_statistics_mask),
.core_status_ctrl_state(core_status_ctrl_state),
.core_status_lane_cgs_state(core_status_lane_cgs_state),
.core_status_lane_emb_state(core_status_lane_emb_state),
.core_status_lane_ifs_ready(core_status_lane_ifs_ready),
.core_status_lane_latency(core_status_lane_latency),
.core_status_lane_frame_align_err_cnt(core_status_lane_frame_align_err_cnt),
.core_status_err_statistics_cnt(core_status_err_statistics_cnt),
.core_ilas_config_valid(core_ilas_config_valid),
.core_ilas_config_addr(core_ilas_config_addr),
.core_ilas_config_data(core_ilas_config_data));
always @(posedge s_axi_aclk) begin
up_wack <= up_wreq;
// ILAS memory takes one clock cycle before the data is ready, hence the extra
// delay.
up_rreq_d1 <= up_rreq;
up_rack <= up_rreq_d1;
if (up_rreq_d1 == 1'b1) begin
up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_rx;
end
end
endmodule
adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr
+435
View File
@@ -0,0 +1,435 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="65fc52178778410ba1471c34ea6a8f11"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="SimulatorVersionXsim" Val="2023.2"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
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<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/axi_jesd204_rx.v">
<FileInfo>
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</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_jesd204_rx"/>
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</FileSet>
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<Config>
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<Config>
<Option Name="DesignMode" Val="RTL"/>
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<Option Name="SrcSet" Val="sources_1"/>
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</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
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<Simulator Name="XSim">
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<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
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<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Id" Val="Place 30-73"/>
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<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
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<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
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<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
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<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
+54
View File
@@ -0,0 +1,54 @@
###############################################################################
## Copyright (C) 2016-2018, 2021 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
set script_dir [file dirname [info script]]
source "$script_dir/util_cdc_constr.tcl"
util_cdc_sync_data_constr {*|jesd204_up_rx:i_up_rx|sync_data:i_cdc_status}
util_cdc_sync_data_constr {*|jesd204_up_rx:i_up_rx|sync_data:i_cdc_cfg}
util_cdc_sync_event_constr {*|jesd204_up_sysref:i_up_sysref|sync_event:i_cdc_sysref_event}
util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|sync_bits:i_cdc_status_ready}
# set_max_skew?
set_false_path \
-to [get_registers {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|up_status_latency[*]}]
util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|jesd204_up_ilas_mem:i_ilas_mem|sync_bits:i_cdc_ilas_ready}
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
-to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}]
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
-to [get_registers {*|jesd204_up_common:i_up_common|device_reset_vector[*]}]
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \
-to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}]
set_false_path \
-to [get_pins -compatibility_mode {*|jesd204_up_common:i_up_common|up_core_reset_ext_synchronizer_vector[*]|clrn}]
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}]
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|device_cfg_*}]
set_false_path \
-from [get_registers {*|jesd204_up_rx:i_up_rx|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
set_false_path \
-from [get_registers {*|jesd204_up_rx:i_up_rx|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}]
set_false_path \
-from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}]
adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
Executable
+129
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###############################################################################
## Copyright (C) 2016-2018, 2020-2021 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set core_clk [get_clocks -of_objects [get_ports core_clk]]
set device_clk [get_clocks -of_objects [get_ports device_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier {*cdc_sync_stage1_reg*}] \
[get_cells -hier {*cdc_sync_stage2_reg*}]
# Used for synchronizing resets with asynchronous de-assert
set_property ASYNC_REG TRUE \
[get_cells -hier {up_reset_vector_reg*}] \
[get_cells -hier {core_reset_vector_reg*}] \
[get_cells -hier {up_reset_synchronizer_vector_reg*}] \
[get_cells -hier {up_core_reset_ext_synchronizer_vector_reg*}]
set_false_path \
-from [get_pins {i_up_rx/i_cdc_status/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_rx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_rx/i_cdc_status/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_rx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_rx/i_cdc_cfg/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_rx/i_cdc_cfg/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_rx/i_cdc_cfg/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_rx/i_cdc_cfg/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \
-to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}]
set_false_path \
-from [get_pins {i_sync_frame_align_err/in_toggle_d1_reg/C}] \
-to [get_pins {i_sync_frame_align_err/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_sync_frame_align_err/out_toggle_d1_reg/C}] \
-to [get_pins {i_sync_frame_align_err/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_sync_frame_align_err/cdc_hold_reg*/C}] \
-to [get_pins {i_sync_frame_align_err/out_event_reg*/D}]
# Don't place them too far appart
set_max_delay -datapath_only \
-from [get_pins {i_up_rx/i_cdc_status/cdc_hold_reg[*]/C}] \
-to [get_pins {i_up_rx/i_cdc_status/out_data_reg[*]/D}] \
[get_property -min PERIOD $axi_clk]
set_false_path \
-from $core_clk \
-to [get_pins {i_up_rx/*i_up_rx_lane/i_cdc_status_ready/cdc_sync_stage1_reg*/D}]
set_max_delay -datapath_only \
-from [get_pins {i_up_rx/i_cdc_cfg/cdc_hold_reg[*]/C}] \
-to [get_pins {i_up_rx/i_cdc_cfg/out_data_reg[*]/D}] \
[get_property -min PERIOD $core_clk]
set_max_delay -datapath_only \
-from $core_clk \
-to [get_pins {i_up_rx/*i_up_rx_lane/up_status_latency_reg[*]/D}] \
[get_property -min PERIOD $axi_clk]
set_false_path \
-from $core_clk \
-to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_cdc_ilas_ready/cdc_sync_stage1_reg[0]/D}]
# Use -quiet here since the ILAS mem is missing in non 8b10b configuration
set_max_delay -quiet -datapath_only \
-from [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/mem_reg*/*/CLK}] \
-to [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/dp_*_gen.up_rdata_reg*/D}] \
[get_property -min PERIOD $axi_clk]
set_false_path \
-from [get_pins {i_up_common/up_reset_core_reg/C}] \
-to [get_pins {i_up_common/core_reset_vector_reg[*]/PRE}]
set_false_path \
-from [get_pins {i_up_common/up_reset_core_reg/C}] \
-to [get_pins {i_up_common/device_reset_vector_reg[*]/PRE}]
set_false_path \
-from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \
-to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[*]/PRE}]
set_false_path \
-to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}]
set_max_delay -datapath_only \
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/core_cfg_*_reg*/D}] \
[get_property -min PERIOD $core_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/device_cfg_*_reg*/D}] \
[get_property -min PERIOD $device_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_rx/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \
[get_property -min PERIOD $core_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_rx/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \
[get_property -min PERIOD $device_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \
[get_property -min PERIOD $device_clk]
adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
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###############################################################################
## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
package require qsys 14.0
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create axi_jesd204_rx "ADI JESD204 Receive AXI Interface"
set_module_property INTERNAL true
# files
ad_ip_files axi_jesd204_rx [list \
axi_jesd204_rx.v \
axi_jesd204_rx_constr.sdc \
jesd204_up_rx.v \
jesd204_up_rx_lane.v \
jesd204_up_ilas_mem.v \
../axi_jesd204_common/jesd204_up_common.v \
../axi_jesd204_common/jesd204_up_sysref.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/util_cdc/sync_bits.v \
$ad_hdl_dir/library/util_cdc/sync_data.v \
$ad_hdl_dir/library/util_cdc/sync_event.v \
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
]
# parameters
add_parameter ID NATURAL 0
set_parameter_property ID DISPLAY_NAME "Peripheral ID"
set_parameter_property ID HDL_PARAMETER true
add_parameter NUM_LANES INTEGER 1
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
set_parameter_property NUM_LANES ALLOWED_RANGES 1:32
set_parameter_property NUM_LANES HDL_PARAMETER true
add_parameter NUM_LINKS INTEGER 1
set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links"
set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8
set_parameter_property NUM_LINKS HDL_PARAMETER true
# axi4 slave interface
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 14
# interrupt
add_interface interrupt interrupt end
set_interface_property interrupt associatedClock s_axi_clock
set_interface_property interrupt associatedReset s_axi_reset
#set_interface_property interrupt associatedAddressablePoint s_axi
add_interface_port interrupt irq irq Output 1
# core clock
add_interface core_clock clock end
add_interface_port core_clock core_clk clk Input 1
# device clock
add_interface device_clock clock end
add_interface_port device_clock device_clk clk Input 1
# core reset ext
add_interface core_reset_ext reset end
set_interface_property core_reset_ext associatedClock core_clock
add_interface_port core_reset_ext core_reset_ext reset Input 1
# core reset
add_interface core_reset reset start
set_interface_property core_reset associatedClock core_clock
set_interface_property core_reset associatedResetSinks core_reset_ext
add_interface_port core_reset core_reset reset Output 1
# device reset
add_interface device_reset reset start
set_interface_property device_reset associatedClock device_clock
set_interface_property device_reset associatedResetSinks core_reset_ext
add_interface_port device_reset device_reset reset Output 1
# link clock domain config interface
add_interface config conduit end
set_interface_property config associatedClock core_clock
set_interface_property config associatedReset core_reset
add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES
add_interface_port config core_cfg_links_disable links_disable Output NUM_LINKS
add_interface_port config core_cfg_octets_per_multiframe octets_per_multiframe Output 10
add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8
add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1
add_interface_port config core_cfg_frame_align_err_threshold frame_align_err_threshold Output 8
add_interface_port config core_ctrl_err_statistics_reset err_statistics_reset Output 1
add_interface_port config core_ctrl_err_statistics_mask err_statistics_mask Output 3
# device clock domain config interface
add_interface device_config conduit end
set_interface_property device_config associatedClock device_clock
set_interface_property device_config associatedReset device_reset
add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Output 10
add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Output 8
add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Output 8
add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Output 8
add_interface_port device_config device_cfg_sysref_disable sysref_disable Output 1
add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Output 1
add_interface_port device_config device_cfg_buffer_delay buffer_delay Output 8
add_interface_port device_config device_cfg_buffer_early_release buffer_early_release Output 1
# status interface
add_interface status conduit end
set_interface_property status associatedClock core_clock
set_interface_property status associatedReset core_reset
add_interface_port status core_status_ctrl_state ctrl_state Input 2
add_interface_port status core_status_lane_cgs_state lane_cgs_state Input 2*NUM_LANES
add_interface_port status core_status_lane_ifs_ready lane_ifs_ready Input NUM_LANES
add_interface_port status core_status_lane_latency lane_latency Input 14*NUM_LANES
add_interface_port status core_status_lane_frame_align_err_cnt lane_frame_align_err_cnt Input 8*NUM_LANES
add_interface_port status core_status_err_statistics_cnt err_statistics_cnt Input 32*NUM_LANES
add_interface_port status status_synth_params0 synth_params0 Input 32
add_interface_port status status_synth_params1 synth_params1 Input 32
add_interface_port status status_synth_params2 synth_params2 Input 32
# event interface
add_interface device_event conduit end
set_interface_property device_event associatedClock device_clock
set_interface_property device_event associatedReset device_reset
add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Input 1
add_interface_port device_event device_event_sysref_edge sysref_edge Input 1
# ilas_config
add_interface ilas_config conduit end
set_interface_property ilas_config associatedClock core_clock
set_interface_property ilas_config associatedReset core_reset
add_interface_port ilas_config core_ilas_config_addr addr Input 2*NUM_LANES
add_interface_port ilas_config core_ilas_config_data data Input 32*NUM_LANES
add_interface_port ilas_config core_ilas_config_valid valid Input NUM_LANES
adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
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###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_jesd204_rx
adi_ip_files axi_jesd204_rx [list \
"../../common/up_axi.v" \
"jesd204_up_rx.v" \
"jesd204_up_rx_lane.v" \
"jesd204_up_ilas_mem.v" \
"axi_jesd204_rx_constr.xdc" \
"axi_jesd204_rx_ooc.ttcl" \
"axi_jesd204_rx.v" \
]
set_property source_mgmt_mode DisplayOnly [current_project]
adi_ip_properties axi_jesd204_rx
adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl"
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx} [ipx::current_core]
set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \
-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
-filter {NAME =~ *synthesis*}]]
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:axi_jesd204_common:1.0 \
]
set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core]
set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core]
adi_add_bus "rx_cfg" "master" \
"analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
"analog.com:interface:jesd204_rx_cfg:1.0" \
{ \
{ "core_cfg_lanes_disable" "lanes_disable" } \
{ "core_cfg_links_disable" "links_disable" } \
{ "core_cfg_octets_per_multiframe" "octets_per_multiframe" } \
{ "core_cfg_octets_per_frame" "octets_per_frame" } \
{ "core_cfg_disable_char_replacement" "disable_char_replacement" } \
{ "core_cfg_disable_scrambler" "disable_scrambler" } \
{ "core_cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
{ "device_cfg_octets_per_multiframe" "device_octets_per_multiframe" } \
{ "device_cfg_octets_per_frame" "device_octets_per_frame" } \
{ "device_cfg_beats_per_multiframe" "device_beats_per_multiframe" } \
{ "device_cfg_lmfc_offset" "device_lmfc_offset" } \
{ "device_cfg_sysref_oneshot" "device_sysref_oneshot" } \
{ "device_cfg_sysref_disable" "device_sysref_disable" } \
{ "device_cfg_buffer_early_release" "device_buffer_early_release" } \
{ "device_cfg_buffer_delay" "device_buffer_delay" } \
{ "core_ctrl_err_statistics_reset" "err_statistics_reset" } \
{ "core_ctrl_err_statistics_mask" "err_statistics_mask" } \
}
adi_add_bus "rx_ilas_config" "slave" \
"analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \
"analog.com:interface:jesd204_rx_ilas_config:1.0" \
{ \
{ "core_ilas_config_valid" "valid" } \
{ "core_ilas_config_addr" "addr" } \
{ "core_ilas_config_data" "data" } \
}
adi_add_bus "rx_event" "slave" \
"analog.com:interface:jesd204_rx_event_rtl:1.0" \
"analog.com:interface:jesd204_rx_event:1.0" \
{ \
{ "device_event_sysref_alignment_error" "sysref_alignment_error" } \
{ "device_event_sysref_edge" "sysref_edge" } \
{ "core_event_frame_alignment_error" "frame_alignment_error" } \
{ "core_event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
}
adi_add_bus "rx_status" "slave" \
"analog.com:interface:jesd204_rx_status_rtl:1.0" \
"analog.com:interface:jesd204_rx_status:1.0" \
{ \
{ "core_status_ctrl_state" "ctrl_state" } \
{ "core_status_lane_cgs_state" "lane_cgs_state" } \
{ "core_status_lane_emb_state" "lane_emb_state" } \
{ "core_status_lane_ifs_ready" "lane_ifs_ready" } \
{ "core_status_lane_latency" "lane_latency" } \
{ "core_status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
{ "core_status_err_statistics_cnt" "err_statistics_cnt" } \
{ "status_synth_params0" "synth_params0" } \
{ "status_synth_params1" "synth_params1" } \
{ "status_synth_params2" "synth_params2" } \
}
ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \
"core_reset" "master"
set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
set cc [ipx::current_core]
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# Link layer mode
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $page0
set_property -dict [list \
"display_name" "Link Layer mode" \
"tooltip" "Link Layer mode" \
"widget" "comboBox" \
] $p
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {64B66B 2 8B10B 1} \
] [ipx::get_user_parameters $p -of_objects $cc]
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
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###############################################################################
## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
<: setFileUsedIn { out_of_context synthesis implementation } :>
<: ;#Component and file information :>
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName $ComponentName :>
<: setFileExtension "_ooc.xdc" :>
# This XDC is used only for OOC mode of synthesis, implementation.
# These are default values for timing driven synthesis during OOC flow.
# These values will be overwritten during implementation with information
# from top level.
create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk]
create_clock -name core_clk -period 2.5 [get_ports core_clk]
create_clock -name device_clk -period 2.5 [get_ports device_clk]
################################################################################
adi_library/jesd204/axi_jesd204_rx/component.xml
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adi_library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2019, 2021-2022 Analog Devices, Inc. All rights reserved.
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module jesd204_up_ilas_mem #(
parameter DATA_PATH_WIDTH = 4
) (
input up_clk,
input up_rreq,
input [1:0] up_raddr,
output reg [31:0] up_rdata,
input core_clk,
input core_reset,
input core_ilas_config_valid,
input [1:0] core_ilas_config_addr,
input [DATA_PATH_WIDTH*8-1:0] core_ilas_config_data,
output up_ilas_ready
);
localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2;
reg [DATA_PATH_WIDTH*8-1:0] mem[0:ILAS_DATA_LENGTH-1];
reg core_ilas_captured = 1'b0;
sync_bits i_cdc_ilas_ready (
.in_bits(core_ilas_captured),
.out_resetn(1'b1),
.out_clk(up_clk),
.out_bits(up_ilas_ready));
always @(posedge core_clk) begin
if (core_reset == 1'b1) begin
core_ilas_captured <= 1'b0;
end else begin
if (core_ilas_config_valid == 1'b1 && core_ilas_config_addr == ILAS_DATA_LENGTH-1) begin
core_ilas_captured <= 1'b1;
end
end
end
generate
if(DATA_PATH_WIDTH == 4) begin : dp_4_gen
always @(posedge up_clk) begin
if (up_rreq == 1'b1) begin
up_rdata <= mem[up_raddr];
end
end
end else if(DATA_PATH_WIDTH == 8) begin : dp_8_gen
always @(posedge up_clk) begin
if (up_rreq == 1'b1) begin
up_rdata <= mem[up_raddr[1]] >> (up_raddr[0]*32);
end
end
end
endgenerate
always @(posedge core_clk) begin
if (core_ilas_config_valid == 1'b1) begin
mem[core_ilas_config_addr] <= core_ilas_config_data;
end
end
/*
* Shift register with variable tap for accessing the stored data.
*
* This has slightly better utilization on Xilinx based platforms than the dual
* port RAM approach, but there is no equivalent primitive on Intel resulting
* in increased utilization since it needs to be implemented used registers and
* muxes.
*
* We might make this a device dependent configuration option at some point.
reg [3:0] mem[0:31];
generate
genvar i;
for (i = 0; i < 32; i = i + 1) begin: gen_ilas_mem
assign up_rdata[i] = mem[i][~up_raddr];
always @(posedge core_clk) begin
if (core_ilas_config_valid == 1'b1) begin
mem[i] <= {mem[i][2:0],core_ilas_config_data[i]};
end
end
end
endgenerate
*/
endmodule
adi_library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved.
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module jesd204_up_rx #(
parameter NUM_LANES = 1,
parameter DATA_PATH_WIDTH = 4
) (
input up_clk,
input up_reset,
input up_reset_synchronizer,
input up_rreq,
input [11:0] up_raddr,
output reg [31:0] up_rdata,
input up_wreq,
input [11:0] up_waddr,
input [31:0] up_wdata,
input core_clk,
input core_reset,
input [NUM_LANES-1:0] core_ilas_config_valid,
input [2*NUM_LANES-1:0] core_ilas_config_addr,
input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] core_ilas_config_data,
input [1:0] core_status_ctrl_state,
input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
input [3*NUM_LANES-1:0] core_status_lane_emb_state,
input [NUM_LANES-1:0] core_status_lane_ifs_ready,
input [14*NUM_LANES-1:0] core_status_lane_latency,
input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt,
input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
output [6:0] core_ctrl_err_statistics_mask,
output core_ctrl_err_statistics_reset,
input up_cfg_is_writeable,
output reg up_cfg_buffer_early_release,
output reg [7:0] up_cfg_buffer_delay,
output reg [7:0] up_cfg_frame_align_err_threshold
);
localparam ELASTIC_BUFFER_SIZE = 256;
wire [1:0] up_status_ctrl_state;
wire [2*NUM_LANES-1:0] up_status_lane_cgs_state;
wire [8*NUM_LANES-1:0] up_status_lane_frame_align_err_cnt;
wire [3*NUM_LANES-1:0] up_status_lane_emb_state;
wire [31:0] up_lane_rdata[0:NUM_LANES-1];
wire [32*NUM_LANES-1:0] up_status_err_statistics_cnt;
reg up_ctrl_err_statistics_reset = 0;
reg [6:0] up_ctrl_err_statistics_mask = 7'h0;
sync_data #(
.NUM_OF_BITS(2+NUM_LANES*(3+2+32+8))
) i_cdc_status (
.in_clk(core_clk),
.in_data({
core_status_err_statistics_cnt,
core_status_ctrl_state,
core_status_lane_cgs_state,
core_status_lane_emb_state,
core_status_lane_frame_align_err_cnt
}),
.out_clk(up_clk),
.out_data({
up_status_err_statistics_cnt,
up_status_ctrl_state,
up_status_lane_cgs_state,
up_status_lane_emb_state,
up_status_lane_frame_align_err_cnt
}));
sync_data #(
.NUM_OF_BITS(8)
) i_cdc_cfg (
.in_clk(up_clk),
.in_data({
up_ctrl_err_statistics_mask,
up_ctrl_err_statistics_reset
}),
.out_clk(core_clk),
.out_data({
core_ctrl_err_statistics_mask,
core_ctrl_err_statistics_reset
}));
localparam LANE_BASE_ADDR = 'h300 / 32;
always @(*) begin
case (up_raddr)
/* Core configuration */
12'h010: up_rdata = ELASTIC_BUFFER_SIZE; /* Elastic buffer size in octets */
/* JESD RX configuraton */
12'h090: up_rdata = {
/* 17-31 */ 15'h00, /* Reserved for future additions */
/* 16 */ up_cfg_buffer_early_release, /* Release buffer as soon as all lanes are ready. */
/* 10-15 */ 6'b0000, /* Reserved for future extensions of buffer_delay */
/* 02-09 */ up_cfg_buffer_delay, /* Buffer release delay */
/* 00-01 */ 2'b00 /* Data path width alignment */
};
12'h91: up_rdata = {
/* 15-31 */ 17'h00, /* Reserved for future additions */
/* 08-14 */ up_ctrl_err_statistics_mask,
/* 01-07 */ 7'h0,
/* 00 */ up_ctrl_err_statistics_reset
};
12'h92: up_rdata = {
/* 08-31 */ 24'h0,
/* 00-07 */ up_cfg_frame_align_err_threshold
};
/* 0x93-0x9f reserved for future use */
/* JESD RX status */
12'ha0: up_rdata = {
/* 04-31 */ 28'h00, /* Reserved for future additions */
/* 02-03 */ 2'b00, /* Reserved for future extensions of ctrl_state */
/* 00-01 */ up_status_ctrl_state /* State of the internal state machine */
};
default: begin
if (up_raddr[11:3] >= LANE_BASE_ADDR &&
up_raddr[11:3] < LANE_BASE_ADDR + NUM_LANES) begin
up_rdata = up_lane_rdata[up_raddr[11:3] - LANE_BASE_ADDR];
end else begin
up_rdata = 'h00;
end
end
endcase
end
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
up_cfg_buffer_early_release <= 1'b0;
up_cfg_buffer_delay <= 'h00;
up_ctrl_err_statistics_mask <= 7'h0;
up_ctrl_err_statistics_reset <= 1'b0;
up_cfg_frame_align_err_threshold <= 8'd4;
end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
case (up_waddr)
/* JESD RX configuraton */
12'h090: begin
up_cfg_buffer_early_release <= up_wdata[16];
up_cfg_buffer_delay <= up_wdata[7:0];
end
endcase
end else if (up_wreq == 1'b1) begin
case (up_waddr)
12'h91: begin
up_ctrl_err_statistics_mask <= up_wdata[14:8];
up_ctrl_err_statistics_reset <= up_wdata[0];
end
12'h92: begin
up_cfg_frame_align_err_threshold <= up_wdata[7:0];
end
endcase
end
end
genvar i;
generate for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
jesd204_up_rx_lane #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_up_rx_lane (
.up_clk(up_clk),
.up_reset_synchronizer(up_reset_synchronizer),
.up_rreq(up_rreq),
.up_raddr(up_raddr[2:0]),
.up_rdata(up_lane_rdata[i]),
.up_status_cgs_state(up_status_lane_cgs_state[2*i+1:2*i]),
.up_status_err_statistics_cnt(up_status_err_statistics_cnt[32*i+31:32*i]),
.up_status_emb_state(up_status_lane_emb_state[3*i+2:3*i]),
.up_status_lane_frame_align_err_cnt(up_status_lane_frame_align_err_cnt[8*i+7:8*i]),
.core_clk(core_clk),
.core_reset(core_reset),
.core_ilas_config_valid(core_ilas_config_valid[i]),
.core_ilas_config_addr(core_ilas_config_addr[2*i+1:2*i]),
.core_ilas_config_data(core_ilas_config_data[(DATA_PATH_WIDTH*8*i)+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i]),
.core_status_ifs_ready(core_status_lane_ifs_ready[i]),
.core_status_latency(core_status_lane_latency[14*i+13:14*i]));
end
endgenerate
endmodule
adi_library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
Executable
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module jesd204_up_rx_lane #(
parameter DATA_PATH_WIDTH = 4
) (
input up_clk,
input up_reset_synchronizer,
input up_rreq,
input [2:0] up_raddr,
output reg [31:0] up_rdata,
input [1:0] up_status_cgs_state,
input [31:0] up_status_err_statistics_cnt,
input [2:0] up_status_emb_state,
input [7:0] up_status_lane_frame_align_err_cnt,
input core_clk,
input core_reset,
input core_ilas_config_valid,
input [1:0] core_ilas_config_addr,
input [DATA_PATH_WIDTH*8-1:0] core_ilas_config_data,
input core_status_ifs_ready,
input [13:0] core_status_latency
);
wire [1:0] up_status_ctrl_state;
wire up_status_ifs_ready;
reg [13:0] up_status_latency = 'h00;
wire [31:0] up_ilas_rdata;
wire up_ilas_ready;
sync_bits #(
.NUM_OF_BITS(1)
) i_cdc_status_ready (
.in_bits({
core_status_ifs_ready
}),
.out_clk(up_clk),
.out_resetn(1'b1),
.out_bits({
up_status_ifs_ready
}));
always @(posedge up_clk) begin
if (up_reset_synchronizer == 1'b1) begin
up_status_latency <= 'h00;
end else begin
if (up_status_ifs_ready == 1'b1) begin
up_status_latency <= core_status_latency;
end
end
end
always @(*) begin
if (up_raddr[2] == 1'b1) begin
if (up_ilas_ready == 1'b1) begin
up_rdata = up_ilas_rdata;
end else begin
up_rdata = 'h00;
end
end else begin
case (up_raddr[1:0])
2'b00: up_rdata = {
/* 11-31 */ 21'h0, /* Reserved for future use */
/* 08-10 */ up_status_emb_state,
/* 06-07 */ 2'h00,
/* 05 */ up_ilas_ready,
/* 04 */ up_status_ifs_ready,
/* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */
/* 00-01 */ up_status_cgs_state
};
2'b01: up_rdata = {
/* 14-31 */ 18'h00, /* Reserved for future use */
/* 00-13 */ up_status_latency
};
2'b10: up_rdata = {
/* 00-31 */ up_status_err_statistics_cnt
};
2'b11: up_rdata = {
/* 08-31 */ 24'h0, /* Reserved for future use */
/* 00-07 */ up_status_lane_frame_align_err_cnt
};
default: up_rdata = 'h00;
endcase
end
end
jesd204_up_ilas_mem #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_ilas_mem (
.up_clk(up_clk),
.up_rreq(up_rreq),
.up_raddr(up_raddr[1:0]),
.up_rdata(up_ilas_rdata),
.up_ilas_ready(up_ilas_ready),
.core_clk(core_clk),
.core_reset(core_reset),
.core_ilas_config_valid(core_ilas_config_valid),
.core_ilas_config_addr(core_ilas_config_addr),
.core_ilas_config_data(core_ilas_config_data));
endmodule
adi_library/jesd204/axi_jesd204_rx/xgui/axi_jesd204_rx_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "ENABLE_LINK_STATS" -parent ${Page_0}
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0}
}
proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to validate DATA_PATH_WIDTH
return true
}
proc update_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
# Procedure called to update ENABLE_LINK_STATS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
# Procedure called to validate ENABLE_LINK_STATS
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to validate LINK_MODE
return true
}
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to validate NUM_LANES
return true
}
proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
# Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
# Procedure called to validate NUM_LINKS
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
}
proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS}
}
proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
}
proc update_MODELPARAM_VALUE.ENABLE_LINK_STATS { MODELPARAM_VALUE.ENABLE_LINK_STATS PARAM_VALUE.ENABLE_LINK_STATS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ENABLE_LINK_STATS}] ${MODELPARAM_VALUE.ENABLE_LINK_STATS}
}
proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH}
}
adi_library/jesd204/axi_jesd204_tx/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_jesd204_tx
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += axi_jesd204_tx.v
GENERIC_DEPS += jesd204_up_tx.v
XILINX_DEPS += axi_jesd204_tx_constr.xdc
XILINX_DEPS += axi_jesd204_tx_ip.tcl
XILINX_DEPS += axi_jesd204_tx_ooc.ttcl
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml
XILINX_LIB_DEPS += jesd204/axi_jesd204_common
XILINX_INTERFACE_DEPS += jesd204/interfaces
INTEL_DEPS += ../../common/up_clock_mon.v
INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../../util_cdc/sync_data.v
INTEL_DEPS += ../../util_cdc/sync_event.v
INTEL_DEPS += ../axi_jesd204_common/jesd204_up_common.v
INTEL_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v
INTEL_DEPS += axi_jesd204_tx_constr.sdc
INTEL_DEPS += axi_jesd204_tx_hw.tcl
include ../../scripts/library.mk
adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
Executable
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_jesd204_tx #(
parameter ID = 0,
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
parameter ENABLE_LINK_STATS = 0,
parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4
) (
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [13:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [13:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
output irq,
input core_clk,
input core_reset_ext,
output core_reset,
input device_clk,
output device_reset,
output [NUM_LANES-1:0] core_cfg_lanes_disable,
output [NUM_LINKS-1:0] core_cfg_links_disable,
output [9:0] core_cfg_octets_per_multiframe,
output [7:0] core_cfg_octets_per_frame,
output core_cfg_continuous_cgs,
output core_cfg_continuous_ilas,
output core_cfg_skip_ilas,
output [7:0] core_cfg_mframes_per_ilas,
output core_cfg_disable_char_replacement,
output core_cfg_disable_scrambler,
output [9:0] device_cfg_octets_per_multiframe,
output [7:0] device_cfg_octets_per_frame,
output [7:0] device_cfg_beats_per_multiframe,
output [7:0] device_cfg_lmfc_offset,
output device_cfg_sysref_oneshot,
output device_cfg_sysref_disable,
input core_ilas_config_rd,
input [1:0] core_ilas_config_addr,
output [DATA_PATH_WIDTH*8*NUM_LANES-1:0] core_ilas_config_data,
input device_event_sysref_alignment_error,
input device_event_sysref_edge,
output core_ctrl_manual_sync_request,
input [1:0] core_status_state,
input [NUM_LINKS-1:0] core_status_sync,
input [31:0] status_synth_params0,
input [31:0] status_synth_params1,
input [31:0] status_synth_params2
);
localparam PCORE_VERSION = 32'h00010661; // 1.06.a
localparam PCORE_MAGIC = 32'h32303454; // 204T
wire up_reset;
/* Register interface signals */
reg [31:0] up_rdata = 'd0;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
wire up_wreq;
wire up_rreq;
wire [31:0] up_wdata;
wire [11:0] up_waddr;
wire [11:0] up_raddr;
wire [31:0] up_rdata_common;
wire [31:0] up_rdata_sysref;
wire [31:0] up_rdata_tx;
wire up_cfg_skip_ilas;
wire up_cfg_continuous_ilas;
wire up_cfg_continuous_cgs;
wire [7:0] up_cfg_mframes_per_ilas;
wire [7:0] up_cfg_lmfc_offset;
wire up_cfg_sysref_oneshot;
wire up_cfg_sysref_disable;
wire up_cfg_is_writeable;
wire [4:0] up_irq_trigger;
assign up_irq_trigger[4:0] = 5'b00000;
up_axi #(
.AXI_ADDRESS_WIDTH (14)
) i_up_axi (
.up_rstn(~up_reset),
.up_clk(s_axi_aclk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
jesd204_up_common #(
.PCORE_VERSION(PCORE_VERSION),
.PCORE_MAGIC(PCORE_MAGIC),
.ID(ID),
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS),
.NUM_IRQS(5),
.EXTRA_CFG_WIDTH(11),
.DEV_EXTRA_CFG_WIDTH(10),
.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
) i_up_common (
.up_clk(s_axi_aclk),
.ext_resetn(s_axi_aresetn),
.up_reset(up_reset),
.up_reset_synchronizer(),
.core_clk(core_clk),
.core_reset_ext(core_reset_ext),
.core_reset(core_reset),
.device_clk(device_clk),
.device_reset(device_reset),
.up_raddr(up_raddr),
.up_rdata(up_rdata_common),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_cfg_is_writeable(up_cfg_is_writeable),
.up_irq_trigger(up_irq_trigger),
.irq(irq),
.core_cfg_octets_per_multiframe(core_cfg_octets_per_multiframe),
.core_cfg_octets_per_frame(core_cfg_octets_per_frame),
.core_cfg_lanes_disable(core_cfg_lanes_disable),
.core_cfg_links_disable(core_cfg_links_disable),
.core_cfg_disable_scrambler(core_cfg_disable_scrambler),
.core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
.up_extra_cfg({
/* 10 */ up_cfg_continuous_cgs,
/* 09 */ up_cfg_continuous_ilas,
/* 08 */ up_cfg_skip_ilas,
/* 00-07 */ up_cfg_mframes_per_ilas
}),
.core_extra_cfg({
/* 10 */ core_cfg_continuous_cgs,
/* 09 */ core_cfg_continuous_ilas,
/* 08 */ core_cfg_skip_ilas,
/* 00-07 */ core_cfg_mframes_per_ilas
}),
.device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
.device_cfg_octets_per_frame(device_cfg_octets_per_frame),
.device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe),
.up_dev_extra_cfg({
/* 09 */ up_cfg_sysref_disable,
/* 08 */ up_cfg_sysref_oneshot,
/* 00-07 */ up_cfg_lmfc_offset
}),
.device_extra_cfg({
/* 09 */ device_cfg_sysref_disable,
/* 08 */ device_cfg_sysref_oneshot,
/* 00-07 */ device_cfg_lmfc_offset
}),
.status_synth_params0(status_synth_params0),
.status_synth_params1(status_synth_params1),
.status_synth_params2(status_synth_params2));
jesd204_up_sysref i_up_sysref (
.up_clk(s_axi_aclk),
.up_reset(up_reset),
.core_clk(core_clk),
.device_clk(device_clk),
.device_event_sysref_alignment_error(device_event_sysref_alignment_error),
.device_event_sysref_edge(device_event_sysref_edge),
.up_cfg_lmfc_offset(up_cfg_lmfc_offset),
.up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
.up_cfg_sysref_disable(up_cfg_sysref_disable),
.up_raddr(up_raddr),
.up_rdata(up_rdata_sysref),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_cfg_is_writeable(up_cfg_is_writeable));
jesd204_up_tx #(
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_up_tx (
.up_clk(s_axi_aclk),
.up_reset(up_reset),
.core_clk(core_clk),
.core_ilas_config_rd(core_ilas_config_rd),
.core_ilas_config_addr(core_ilas_config_addr),
.core_ilas_config_data(core_ilas_config_data),
.core_ctrl_manual_sync_request(core_ctrl_manual_sync_request),
.core_status_state(core_status_state),
.core_status_sync(core_status_sync),
.up_raddr(up_raddr),
.up_rdata(up_rdata_tx),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_cfg_is_writeable(up_cfg_is_writeable),
.up_cfg_continuous_cgs(up_cfg_continuous_cgs),
.up_cfg_continuous_ilas(up_cfg_continuous_ilas),
.up_cfg_skip_ilas(up_cfg_skip_ilas),
.up_cfg_mframes_per_ilas(up_cfg_mframes_per_ilas));
always @(posedge s_axi_aclk) begin
up_wack <= up_wreq;
up_rack <= up_rreq;
if (up_rreq == 1'b1) begin
up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_tx;
end
end
endmodule
adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr
+421
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@@ -0,0 +1,421 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="9162f4c9af3f47ffb44e034cdca2df90"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../common/up_axi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/axi_jesd204_tx_ooc.ttcl"/>
<File Path="$PPRDIR/jesd204_up_tx.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
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</File>
<File Path="$PPRDIR/axi_jesd204_tx.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_jesd204_tx"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/axi_jesd204_tx_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
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<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
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<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Synth 8-2490"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
+52
View File
@@ -0,0 +1,52 @@
###############################################################################
## Copyright (C) 2016-2018, 2021 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
set script_dir [file dirname [info script]]
source "$script_dir/util_cdc_constr.tcl"
util_cdc_sync_event_constr {*|jesd204_up_sysref:i_up_sysref|sync_event:i_cdc_sysref_event}
util_cdc_sync_event_constr {*|jesd204_up_tx:i_up_tx|sync_event:i_cdc_manual_sync_request}
util_cdc_sync_data_constr {*|jesd204_up_tx:i_up_tx|sync_data:i_cdc_status}
util_cdc_sync_bits_constr {*|jesd204_up_tx:i_up_tx|sync_bits:i_cdc_sync}
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
-to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}]
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
-to [get_registers {*|jesd204_up_common:i_up_common|device_reset_vector[*]}]
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \
-to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}]
set_false_path \
-to [get_pins -compatibility_mode {*|jesd204_up_common:i_up_common|up_core_reset_ext_synchronizer_vector[*]|clrn}]
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}]
set_false_path \
-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|device_cfg_*}]
set_false_path \
-from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_ilas_data_*}] \
-to [get_registers {*|jesd204_up_tx:i_up_tx|core_ilas_config_data[*]}]
set_false_path \
-from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
set_false_path \
-from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}]
set_false_path \
-from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \
-to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}]
adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
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###############################################################################
## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set core_clk [get_clocks -of_objects [get_ports core_clk]]
set device_clk [get_clocks -of_objects [get_ports device_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier {*cdc_sync_stage1_reg*}] \
[get_cells -hier {*cdc_sync_stage2_reg*}]
# Used for synchronizing resets with asynchronous de-assert
set_property ASYNC_REG TRUE \
[get_cells -hier {up_reset_vector_reg*}] \
[get_cells -hier {core_reset_vector_reg*}] \
[get_cells -hier {up_reset_synchronizer_vector_reg*}] \
[get_cells -hier {up_core_reset_ext_synchronizer_vector_reg*}]
set_false_path \
-from [get_pins {i_up_tx/i_cdc_status/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_tx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_tx/i_cdc_status/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_tx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \
-to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}]
# Don't place them too far appart
set_max_delay -datapath_only \
-from [get_pins {i_up_tx/i_cdc_status/cdc_hold_reg[*]/C}] \
-to [get_pins {i_up_tx/i_cdc_status/out_data_reg[*]/D}] \
[get_property -min PERIOD $axi_clk]
set_false_path \
-from $core_clk \
-to [get_pins {i_up_tx/i_cdc_sync/cdc_sync_stage1_reg[*]/D}]
set_false_path \
-from [get_pins {i_up_common/up_reset_core_reg/C}] \
-to [get_pins {i_up_common/core_reset_vector_reg[*]/PRE}]
set_false_path \
-from [get_pins {i_up_common/up_reset_core_reg/C}] \
-to [get_pins {i_up_common/device_reset_vector_reg[*]/PRE}]
set_false_path \
-from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \
-to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[*]/PRE}]
set_false_path \
-to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}]
set_max_delay -datapath_only \
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/core_cfg_*_reg*/D}] \
[get_property -min PERIOD $core_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/device_cfg_*_reg*/D}] \
[get_property -min PERIOD $device_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \
-to [get_cells {i_up_tx/*core_ilas_config_data_reg*}] \
[get_property -min PERIOD $core_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \
[get_property -min PERIOD $core_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \
[get_property -min PERIOD $device_clk]
set_max_delay -datapath_only \
-from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \
-to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \
[get_property -min PERIOD $device_clk]
set_false_path \
-from [get_pins {i_up_tx/i_cdc_manual_sync_request/out_toggle_d1_reg/C}] \
-to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins {i_up_tx/i_cdc_manual_sync_request/in_toggle_d1_reg/C}] \
-to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_out/cdc_sync_stage1_reg[0]/D}]
adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
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###############################################################################
## Copyright (C) 2016-2019, 2021-2022 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
package require qsys 14.0
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create axi_jesd204_tx "ADI JESD204 Transmit AXI Interface"
set_module_property INTERNAL true
# files
ad_ip_files axi_jesd204_tx [list \
axi_jesd204_tx.v \
axi_jesd204_tx_constr.sdc \
jesd204_up_tx.v \
../axi_jesd204_common/jesd204_up_common.v \
../axi_jesd204_common/jesd204_up_sysref.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/util_cdc/sync_bits.v \
$ad_hdl_dir/library/util_cdc/sync_data.v \
$ad_hdl_dir/library/util_cdc/sync_event.v \
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
]
# parameters
add_parameter ID NATURAL 0
set_parameter_property ID DISPLAY_NAME "Peripheral ID"
set_parameter_property ID HDL_PARAMETER true
add_parameter NUM_LANES INTEGER 1
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
set_parameter_property NUM_LANES ALLOWED_RANGES 1:32
set_parameter_property NUM_LANES HDL_PARAMETER true
add_parameter NUM_LINKS INTEGER 1
set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links"
set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8
set_parameter_property NUM_LINKS HDL_PARAMETER true
# axi4 slave interface
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 14
# interrupt
add_interface interrupt interrupt end
set_interface_property interrupt associatedClock s_axi_clock
set_interface_property interrupt associatedReset s_axi_reset
#set_interface_property interrupt associatedAddressablePoint s_axi
add_interface_port interrupt irq irq Output 1
# core clock
add_interface core_clock clock end
add_interface_port core_clock core_clk clk Input 1
# device clock
add_interface device_clock clock end
add_interface_port device_clock device_clk clk Input 1
# core reset ext
add_interface core_reset_ext reset end
set_interface_property core_reset_ext associatedClock core_clock
add_interface_port core_reset_ext core_reset_ext reset Input 1
# core reset
add_interface core_reset reset start
set_interface_property core_reset associatedClock core_clock
set_interface_property core_reset associatedResetSinks core_reset_ext
add_interface_port core_reset core_reset reset Output 1
# device reset
add_interface device_reset reset start
set_interface_property device_reset associatedClock device_clock
set_interface_property device_reset associatedResetSinks core_reset_ext
add_interface_port device_reset device_reset reset Output 1
# config interface
#
add_interface config conduit end
set_interface_property config associatedClock core_clock
set_interface_property config associatedReset core_reset
add_interface_port config core_cfg_octets_per_multiframe octets_per_multiframe Output 10
add_interface_port config core_cfg_continuous_cgs continuous_cgs Output 1
add_interface_port config core_cfg_continuous_ilas continuous_ilas Output 1
add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1
add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES
add_interface_port config core_cfg_links_disable links_disable Output NUM_LINKS
add_interface_port config core_cfg_mframes_per_ilas mframes_per_ilas Output 8
add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8
add_interface_port config core_cfg_skip_ilas skip_ilas Output 1
# device clock domain config interface
add_interface device_config conduit end
set_interface_property device_config associatedClock device_clock
set_interface_property device_config associatedReset device_reset
add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Output 10
add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Output 8
add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Output 8
add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Output 8
add_interface_port device_config device_cfg_sysref_disable sysref_disable Output 1
add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Output 1
# control interface
add_interface control conduit end
set_interface_property control associatedClock core_clock
set_interface_property control associatedReset core_reset
add_interface_port control core_ctrl_manual_sync_request manual_sync_request Output 1
# ilas config interface
add_interface ilas_config conduit end
set_interface_property ilas_config associatedClock core_clock
set_interface_property ilas_config associatedReset core_reset
add_interface_port ilas_config core_ilas_config_addr addr Input 2
add_interface_port ilas_config core_ilas_config_data data Output 32*NUM_LANES
add_interface_port ilas_config core_ilas_config_rd rd Input 1
# event interface
add_interface device_event conduit end
set_interface_property device_event associatedClock device_clock
set_interface_property device_event associatedReset device_reset
add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Input 1
add_interface_port device_event device_event_sysref_edge sysref_edge Input 1
# status interface
add_interface status conduit end
set_interface_property status associatedClock core_clock
set_interface_property status associatedReset core_reset
add_interface_port status core_status_state state Input 2
add_interface_port status core_status_sync sync Input 1
add_interface_port status status_synth_params0 synth_params0 Input 32
add_interface_port status status_synth_params1 synth_params1 Input 32
add_interface_port status status_synth_params2 synth_params2 Input 32
adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
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###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
global VIVADO_IP_LIBRARY
adi_ip_create axi_jesd204_tx
adi_ip_files axi_jesd204_tx [list \
"../../common/up_axi.v" \
"axi_jesd204_tx_constr.xdc" \
"axi_jesd204_tx_ooc.ttcl" \
"jesd204_up_tx.v" \
"axi_jesd204_tx.v" \
]
set_property source_mgmt_mode DisplayOnly [current_project]
adi_ip_properties axi_jesd204_tx
adi_ip_ttcl axi_jesd204_tx "axi_jesd204_tx_ooc.ttcl"
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx} [ipx::current_core]
set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_tx_constr.xdc \
-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
-filter {NAME =~ *synthesis*}]]
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:axi_jesd204_common:1.0 \
]
set_property display_name "ADI JESD204C Transmit AXI Interface" [ipx::current_core]
set_property description "ADI JESD204B Transmit AXI Interface" [ipx::current_core]
adi_add_bus "tx_cfg" "master" \
"analog.com:interface:jesd204_tx_cfg_rtl:1.0" \
"analog.com:interface:jesd204_tx_cfg:1.0" \
{ \
{ "core_cfg_lanes_disable" "lanes_disable" } \
{ "core_cfg_links_disable" "links_disable" } \
{ "core_cfg_octets_per_multiframe" "octets_per_multiframe" } \
{ "core_cfg_octets_per_frame" "octets_per_frame" } \
{ "core_cfg_continuous_cgs" "continuous_cgs" } \
{ "core_cfg_continuous_ilas" "continuous_ilas" } \
{ "core_cfg_skip_ilas" "skip_ilas" } \
{ "core_cfg_mframes_per_ilas" "mframes_per_ilas" } \
{ "core_cfg_disable_char_replacement" "disable_char_replacement" } \
{ "core_cfg_disable_scrambler" "disable_scrambler" } \
{ "device_cfg_octets_per_multiframe" "device_octets_per_multiframe" } \
{ "device_cfg_octets_per_frame" "device_octets_per_frame" } \
{ "device_cfg_beats_per_multiframe" "device_beats_per_multiframe" } \
{ "device_cfg_lmfc_offset" "device_lmfc_offset" } \
{ "device_cfg_sysref_oneshot" "device_sysref_oneshot" } \
{ "device_cfg_sysref_disable" "device_sysref_disable" } \
}
adi_add_bus "tx_ilas_config" "slave" \
"analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \
"analog.com:interface:jesd204_tx_ilas_config:1.0" \
{ \
{ "core_ilas_config_rd" "rd" } \
{ "core_ilas_config_addr" "addr" } \
{ "core_ilas_config_data" "data" } \
}
adi_add_bus "tx_event" "slave" \
"analog.com:interface:jesd204_tx_event_rtl:1.0" \
"analog.com:interface:jesd204_tx_event:1.0" \
{ \
{ "device_event_sysref_alignment_error" "sysref_alignment_error" } \
{ "device_event_sysref_edge" "sysref_edge" } \
}
adi_add_bus "tx_status" "slave" \
"analog.com:interface:jesd204_tx_status_rtl:1.0" \
"analog.com:interface:jesd204_tx_status:1.0" \
{ \
{ "core_status_state" "state" } \
{ "core_status_sync" "sync" } \
{ "status_synth_params0" "synth_params0" } \
{ "status_synth_params1" "synth_params1" } \
{ "status_synth_params2" "synth_params2" } \
}
adi_add_bus "tx_ctrl" "master" \
"analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \
"analog.com:interface:jesd204_tx_ctrl:1.0" \
{ \
{ "core_ctrl_manual_sync_request" "manual_sync_request" } \
}
ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
adi_add_bus_clock "core_clk" "tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl" \
"core_reset" "master"
set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
set cc [ipx::current_core]
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# Link layer mode
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $page0
set_property -dict [list \
"display_name" "Link Layer mode" \
"tooltip" "Link Layer mode" \
"widget" "comboBox" \
] $p
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {64B66B 2 8B10B 1} \
] [ipx::get_user_parameters $p -of_objects $cc]
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl
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###############################################################################
## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
<: setFileUsedIn { out_of_context synthesis implementation } :>
<: ;#Component and file information :>
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName $ComponentName :>
<: setFileExtension "_ooc.xdc" :>
# This XDC is used only for OOC mode of synthesis, implementation.
# These are default values for timing driven synthesis during OOC flow.
# These values will be overwritten during implementation with information
# from top level.
create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk]
create_clock -name core_clk -period 2.5 [get_ports core_clk]
create_clock -name device_clk -period 2.5 [get_ports device_clk]
################################################################################
adi_library/jesd204/axi_jesd204_tx/component.xml
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adi_library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
Executable
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module jesd204_up_tx #(
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter DATA_PATH_WIDTH = 4
) (
input up_clk,
input up_reset,
input [11:0] up_raddr,
output reg [31:0] up_rdata,
input up_wreq,
input [11:0] up_waddr,
input [31:0] up_wdata,
input up_cfg_is_writeable,
output reg up_cfg_skip_ilas,
output reg up_cfg_continuous_ilas,
output reg up_cfg_continuous_cgs,
output reg [7:0] up_cfg_mframes_per_ilas,
input core_clk,
input core_ilas_config_rd,
input [1:0] core_ilas_config_addr,
output reg [DATA_PATH_WIDTH*8*NUM_LANES-1:0] core_ilas_config_data,
output core_ctrl_manual_sync_request,
input [1:0] core_status_state,
input [NUM_LINKS-1:0] core_status_sync
);
reg [31:0] up_cfg_ilas_data[0:NUM_LANES-1][0:3];
reg up_ctrl_manual_sync_request = 1'b0;
wire [1:0] up_status_state;
wire [NUM_LINKS-1:0] up_status_sync;
sync_bits #(
.NUM_OF_BITS (NUM_LINKS)
) i_cdc_sync (
.in_bits(core_status_sync),
.out_clk(up_clk),
.out_resetn(1'b1),
.out_bits(up_status_sync));
sync_data #(
.NUM_OF_BITS(2)
) i_cdc_status (
.in_clk(core_clk),
.in_data(core_status_state),
.out_clk(up_clk),
.out_data(up_status_state));
sync_event #(
.NUM_OF_EVENTS(1),
.ASYNC_CLK(1)
) i_cdc_manual_sync_request (
.in_clk(up_clk),
.in_event(up_ctrl_manual_sync_request),
.out_clk(core_clk),
.out_event(core_ctrl_manual_sync_request));
integer i;
always @(*) begin
case (up_raddr)
/* JESD TX configuration */
12'h090: up_rdata = {
/* 03-31 */ 29'h00, /* Reserved for future additions */
/* 02 */ up_cfg_skip_ilas, /* Don't send ILAS, go directly from CGS to DATA */
/* 01 */ up_cfg_continuous_ilas, /* Continuously send ILAS sequence */
/* 00 */ up_cfg_continuous_cgs /* Continuously send CGS characters */
};
12'h091: up_rdata = {
/* 08-31 */ 24'h00, /* Reserved for future additions */
/* 00-07 */ up_cfg_mframes_per_ilas /* Number of multiframes send during the ILAS */
};
/* JESD TX status */
12'ha0: up_rdata = {
/* 12-31 */ 20'h00, /* Reserved for future additions */
/* 04-11 */ up_status_sync, /* Raw value of the SYNC pin */
/* 02-03 */ 2'b0, /* Reserved fo future extension of the status_state field */
/* 00-01 */ up_status_state /* State of the internal state machine (0=CGS, 1=ILAS, 2=DATA) */
};
default: begin
if (up_raddr[10:3] >= ('h300/32) &&
up_raddr[10:3] < (('h300/32) + NUM_LANES) &&
up_raddr[2] == 1'b1) begin
up_rdata = up_cfg_ilas_data[up_raddr[5:3]][up_raddr[1:0]];
end else begin
up_rdata = 32'h00000000;
end
end
endcase
end
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
up_cfg_skip_ilas <= 1'b0;
up_cfg_continuous_ilas <= 1'b0;
up_cfg_continuous_cgs <= 1'b0;
up_cfg_mframes_per_ilas <= 'h3;
end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
case (up_waddr)
/* JESD TX configuraton */
12'h090: begin
up_cfg_skip_ilas <= up_wdata[2];
up_cfg_continuous_ilas <= up_wdata[1];
up_cfg_continuous_cgs <= up_wdata[0];
end
12'h091: begin
// We'll enable this if we ever have a usecase
// cfg_mframes_per_ilas <= up_wdata[7:0];
end
endcase
end
end
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
up_ctrl_manual_sync_request <= 1'b0;
end else if (up_wreq == 1'b1 && up_waddr == 12'h092) begin
up_ctrl_manual_sync_request <= up_wdata[0];
end else begin
up_ctrl_manual_sync_request <= 1'b0;
end
end
/* Shared ILAS data can be access through any lane register map window */
/* Shared ILAS data */
reg [7:0] up_cfg_ilas_data_did = 'h00;
reg [3:0] up_cfg_ilas_data_bid = 'h00;
reg [4:0] up_cfg_ilas_data_l = 'h00;
reg up_cfg_ilas_data_scr = 'h00;
reg [7:0] up_cfg_ilas_data_f = 'h00;
reg [4:0] up_cfg_ilas_data_k = 'h00;
reg [7:0] up_cfg_ilas_data_m = 'h00;
reg [4:0] up_cfg_ilas_data_n = 'h00;
reg [1:0] up_cfg_ilas_data_cs = 'h00;
reg [4:0] up_cfg_ilas_data_np = 'h00;
reg [2:0] up_cfg_ilas_data_subclassv = 'h00;
reg [4:0] up_cfg_ilas_data_s = 'h00;
reg [2:0] up_cfg_ilas_data_jesdv = 'h00;
reg [4:0] up_cfg_ilas_data_cf = 'h00;
reg up_cfg_ilas_data_hd = 'h00;
/* Per lane ILAS data */
reg [4:0] up_cfg_ilas_data_lid[0:NUM_LANES-1];
reg [7:0] up_cfg_ilas_data_fchk[0:NUM_LANES-1];
always @(*) begin
for (i = 0; i < NUM_LANES; i = i + 1) begin
up_cfg_ilas_data[i][0] = {
4'b0000,
up_cfg_ilas_data_bid,
up_cfg_ilas_data_did,
16'h00
};
up_cfg_ilas_data[i][1] = {
3'b000,
up_cfg_ilas_data_k,
up_cfg_ilas_data_f,
up_cfg_ilas_data_scr,
2'b00,
up_cfg_ilas_data_l,
3'b000,
up_cfg_ilas_data_lid[i]
};
up_cfg_ilas_data[i][2] = {
up_cfg_ilas_data_jesdv,
up_cfg_ilas_data_s,
up_cfg_ilas_data_subclassv,
up_cfg_ilas_data_np,
up_cfg_ilas_data_cs,
1'b0,
up_cfg_ilas_data_n,
up_cfg_ilas_data_m
};
up_cfg_ilas_data[i][3] = {
up_cfg_ilas_data_fchk[i],
16'h0000,
up_cfg_ilas_data_hd,
2'b00,
up_cfg_ilas_data_cf
};
end
end
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
up_cfg_ilas_data_did <= 'h00;
up_cfg_ilas_data_bid <= 'h00;
up_cfg_ilas_data_scr <= 'h00;
up_cfg_ilas_data_f <= 'h00;
up_cfg_ilas_data_k <= 'h00;
up_cfg_ilas_data_m <= 'h00;
up_cfg_ilas_data_n <= 'h00;
up_cfg_ilas_data_cs <= 'h00;
up_cfg_ilas_data_np <= 'h00;
up_cfg_ilas_data_subclassv <= 'h00;
up_cfg_ilas_data_s <= 'h00;
up_cfg_ilas_data_jesdv <= 'h00;
up_cfg_ilas_data_cf <= 'h00;
up_cfg_ilas_data_hd <= 'h00;
up_cfg_ilas_data_l <= 'h00;
for (i = 0; i < NUM_LANES; i = i + 1) begin
up_cfg_ilas_data_lid[i] <= 'h00;
up_cfg_ilas_data_fchk[i] <= 'h00;
end
end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
for (i = 0; i < NUM_LANES; i = i + 1) begin
if (up_waddr[10:2] == ('h310 / 16) + i*2) begin
case (up_waddr[1:0])
2'h0: begin
up_cfg_ilas_data_bid <= up_wdata[27:24];
up_cfg_ilas_data_did <= up_wdata[23:16];
end
2'h1: begin
up_cfg_ilas_data_k <= up_wdata[28:24];
up_cfg_ilas_data_f <= up_wdata[23:16];
up_cfg_ilas_data_scr <= up_wdata[15];
up_cfg_ilas_data_l <= up_wdata[12:8];
up_cfg_ilas_data_lid[i] <= up_wdata[4:0];
end
2'h2: begin
up_cfg_ilas_data_jesdv <= up_wdata[31:29];
up_cfg_ilas_data_s <= up_wdata[28:24];
up_cfg_ilas_data_subclassv <= up_wdata[23:21];
up_cfg_ilas_data_np <= up_wdata[20:16];
up_cfg_ilas_data_cs <= up_wdata[15:14];
up_cfg_ilas_data_n <= up_wdata[12:8];
up_cfg_ilas_data_m <= up_wdata[7:0];
end
2'h3: begin
up_cfg_ilas_data_fchk[i] <= up_wdata[31:24];
up_cfg_ilas_data_hd <= up_wdata[7];
up_cfg_ilas_data_cf <= up_wdata[4:0];
end
endcase
end
end
end
end
generate
if(DATA_PATH_WIDTH == 4) begin : gen_dp_4
always @(posedge core_clk) begin
if (core_ilas_config_rd == 1'b1) begin
for (i = 0; i < NUM_LANES; i = i + 1) begin
core_ilas_config_data[i*32+:32] <= up_cfg_ilas_data[i][core_ilas_config_addr];
end
end
end
end else if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
always @(posedge core_clk) begin
if (core_ilas_config_rd == 1'b1) begin
for (i = 0; i < NUM_LANES; i = i + 1) begin
core_ilas_config_data[i*64+:64] <= {up_cfg_ilas_data[i][{core_ilas_config_addr[0], 1'b1}],up_cfg_ilas_data[i][{core_ilas_config_addr[0], 1'b0}]};
end
end
end
end
endgenerate
endmodule
adi_library/jesd204/axi_jesd204_tx/xgui/axi_jesd204_tx_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox
ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "ENABLE_LINK_STATS" -parent ${Page_0}
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0}
}
proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to validate DATA_PATH_WIDTH
return true
}
proc update_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
# Procedure called to update ENABLE_LINK_STATS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
# Procedure called to validate ENABLE_LINK_STATS
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
# Procedure called to validate LINK_MODE
return true
}
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to validate NUM_LANES
return true
}
proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
# Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
# Procedure called to validate NUM_LINKS
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
}
proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS}
}
proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
}
proc update_MODELPARAM_VALUE.ENABLE_LINK_STATS { MODELPARAM_VALUE.ENABLE_LINK_STATS PARAM_VALUE.ENABLE_LINK_STATS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ENABLE_LINK_STATS}] ${MODELPARAM_VALUE.ENABLE_LINK_STATS}
}
proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH}
}
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adi_library/jesd204/interfaces/Makefile
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####################################################################################
####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := interfaces_ip.tcl
M_DEPS += ../../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip_xilinx.tcl
M_VIVADO := vivado -mode batch -source
XML_FLIST := jesd204_tx_cfg.xml
XML_FLIST += jesd204_tx_cfg_rtl.xml
XML_FLIST += jesd204_tx_ilas_config.xml
XML_FLIST += jesd204_tx_ilas_config_rtl.xml
XML_FLIST += jesd204_tx_status.xml
XML_FLIST += jesd204_tx_status_rtl.xml
XML_FLIST += jesd204_tx_event.xml
XML_FLIST += jesd204_tx_event_rtl.xml
XML_FLIST += jesd204_tx_ctrl.xml
XML_FLIST += jesd204_tx_ctrl_rtl.xml
XML_FLIST += jesd204_rx_cfg.xml
XML_FLIST += jesd204_rx_cfg_rtl.xml
XML_FLIST += jesd204_rx_status.xml
XML_FLIST += jesd204_rx_status_rtl.xml
XML_FLIST += jesd204_rx_ilas_config.xml
XML_FLIST += jesd204_rx_ilas_config_rtl.xml
XML_FLIST += jesd204_rx_event.xml
XML_FLIST += jesd204_rx_event_rtl.xml
M_FLIST := *.log
M_FLIST += *.jou
M_FLIST += $(XML_FLIST)
.PHONY: all xilinx clean clean-all
all: xilinx
xilinx: $(XML_FLIST)
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
%.xml: $(M_DEPS)
$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
####################################################################################
####################################################################################
adi_library/jesd204/interfaces/interfaces_ip.tcl
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###############################################################################
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
# TX interfaces
adi_if_define "jesd204_tx_cfg"
adi_if_ports output -1 lanes_disable
adi_if_ports output -1 links_disable
adi_if_ports output 10 octets_per_multiframe
adi_if_ports output 8 octets_per_frame
adi_if_ports output 1 continuous_cgs
adi_if_ports output 1 continuous_ilas
adi_if_ports output 1 skip_ilas
adi_if_ports output 8 mframes_per_ilas
adi_if_ports output 1 disable_char_replacement
adi_if_ports output 1 disable_scrambler
adi_if_ports output 10 device_octets_per_multiframe
adi_if_ports output 8 device_octets_per_frame
adi_if_ports output 8 device_beats_per_multiframe
adi_if_ports output 8 device_lmfc_offset
adi_if_ports output 1 device_sysref_oneshot
adi_if_ports output 1 device_sysref_disable
adi_if_define "jesd204_tx_ilas_config"
adi_if_ports output 1 rd
adi_if_ports output 2 addr
adi_if_ports input 32 data
adi_if_define "jesd204_tx_status"
adi_if_ports output 1 state
adi_if_ports output 1 sync
adi_if_ports output -1 synth_params0
adi_if_ports output -1 synth_params1
adi_if_ports output -1 synth_params2
adi_if_define "jesd204_tx_event"
adi_if_ports output 1 sysref_alignment_error
adi_if_ports output 1 sysref_edge
adi_if_define "jesd204_tx_ctrl"
adi_if_ports output 1 manual_sync_request
# RX interfaces
adi_if_define "jesd204_rx_cfg"
adi_if_ports output -1 lanes_disable
adi_if_ports output -1 links_disable
adi_if_ports output 10 octets_per_multiframe
adi_if_ports output 8 octets_per_frame
adi_if_ports output 1 disable_char_replacement
adi_if_ports output 1 disable_scrambler
adi_if_ports output 8 frame_align_err_threshold
adi_if_ports output 10 device_octets_per_multiframe
adi_if_ports output 8 device_octets_per_frame
adi_if_ports output 8 device_beats_per_multiframe
adi_if_ports output 8 device_lmfc_offset
adi_if_ports output 1 device_sysref_oneshot
adi_if_ports output 1 device_sysref_disable
adi_if_ports output 1 device_buffer_early_release
adi_if_ports output 1 device_buffer_delay
adi_if_ports output 1 err_statistics_reset
adi_if_ports output 7 err_statistics_mask
adi_if_define "jesd204_rx_status"
adi_if_ports output 3 ctrl_state
adi_if_ports output -1 lane_cgs_state
adi_if_ports output -1 lane_emb_state
adi_if_ports output -1 lane_frame_align
adi_if_ports output -1 lane_ifs_ready
adi_if_ports output -1 lane_latency_ready
adi_if_ports output -1 lane_latency
adi_if_ports output -1 err_statistics_cnt
adi_if_ports output -1 synth_params0
adi_if_ports output -1 synth_params1
adi_if_ports output -1 synth_params2
adi_if_define "jesd204_rx_ilas_config"
adi_if_ports output -1 valid
adi_if_ports output -1 addr
adi_if_ports input -1 data
adi_if_define "jesd204_rx_event"
adi_if_ports output 1 sysref_alignment_error
adi_if_ports output 1 sysref_edge
adi_if_ports output 1 frame_alignment_error
adi_if_ports output 1 unexpected_lane_state_error
adi_library/jesd204/interfaces/jesd204_rx_cfg.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_rx_cfg</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>
adi_library/jesd204/interfaces/jesd204_rx_cfg_rtl.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_rx_cfg_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="jesd204_rx_cfg" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>lanes_disable</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>links_disable</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>octets_per_multiframe</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>10</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>10</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>octets_per_frame</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>disable_char_replacement</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>disable_scrambler</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>frame_align_err_threshold</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_octets_per_multiframe</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>10</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>10</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_octets_per_frame</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_beats_per_multiframe</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_lmfc_offset</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_sysref_oneshot</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_sysref_disable</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_buffer_early_release</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_buffer_delay</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>err_statistics_reset</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>err_statistics_mask</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>7</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>7</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/jesd204/interfaces/jesd204_rx_cfg_v1_0.sv
+103
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`ifndef jesd204_rx_cfg_v1_0
`define jesd204_rx_cfg_v1_0
package parameter_structs;
typedef struct packed {
bit portEnabled;
integer portWidth;
}portConfig;
typedef struct packed {
// <typeName> <LogicalName> = {<enablement>, <width>}
portConfig lanes_disable;
portConfig links_disable;
}jesd204_rx_cfg_v1_0_port_configuration;
parameter jesd204_rx_cfg_v1_0_port_configuration jesd204_rx_cfg_v1_0_default_port_configuration = '{lanes_disable:'{1, -1}, links_disable:'{1, -1}};
endpackage
interface jesd204_rx_cfg_v1_0 #(parameter_structs::jesd204_rx_cfg_v1_0_port_configuration port_configuration)();
logic [port_configuration.lanes_disable.portWidth-1:0] lanes_disable; //
logic [port_configuration.links_disable.portWidth-1:0] links_disable; //
logic [9:0] octets_per_multiframe; //
logic [7:0] octets_per_frame; //
logic disable_char_replacement; //
logic disable_scrambler; //
logic [7:0] frame_align_err_threshold; //
logic [9:0] device_octets_per_multiframe; //
logic [7:0] device_octets_per_frame; //
logic [7:0] device_beats_per_multiframe; //
logic [7:0] device_lmfc_offset; //
logic device_sysref_oneshot; //
logic device_sysref_disable; //
logic device_buffer_early_release; //
logic device_buffer_delay; //
logic err_statistics_reset; //
logic [6:0] err_statistics_mask; //
modport MASTER (
output lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, disable_char_replacement, disable_scrambler, frame_align_err_threshold, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable, device_buffer_early_release, device_buffer_delay, err_statistics_reset, err_statistics_mask
);
modport SLAVE (
input lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, disable_char_replacement, disable_scrambler, frame_align_err_threshold, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable, device_buffer_early_release, device_buffer_delay, err_statistics_reset, err_statistics_mask
);
modport MONITOR (
input lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, disable_char_replacement, disable_scrambler, frame_align_err_threshold, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable, device_buffer_early_release, device_buffer_delay, err_statistics_reset, err_statistics_mask
);
endinterface // jesd204_rx_cfg_v1_0
`endif
adi_library/jesd204/interfaces/jesd204_rx_event.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_rx_event</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>
adi_library/jesd204/interfaces/jesd204_rx_event_rtl.xml
+66
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_rx_event_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="jesd204_rx_event" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>sysref_alignment_error</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>sysref_edge</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>frame_alignment_error</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>unexpected_lane_state_error</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/jesd204/interfaces/jesd204_rx_event_v1_0.sv
+73
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@@ -0,0 +1,73 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`ifndef jesd204_rx_event_v1_0
`define jesd204_rx_event_v1_0
interface jesd204_rx_event_v1_0();
logic sysref_alignment_error; //
logic sysref_edge; //
logic frame_alignment_error; //
logic unexpected_lane_state_error; //
modport MASTER (
output sysref_alignment_error, sysref_edge, frame_alignment_error, unexpected_lane_state_error
);
modport SLAVE (
input sysref_alignment_error, sysref_edge, frame_alignment_error, unexpected_lane_state_error
);
modport MONITOR (
input sysref_alignment_error, sysref_edge, frame_alignment_error, unexpected_lane_state_error
);
endinterface // jesd204_rx_event_v1_0
`endif
adi_library/jesd204/interfaces/jesd204_rx_ilas_config.xml
+11
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@@ -0,0 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_rx_ilas_config</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>
adi_library/jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
+46
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@@ -0,0 +1,46 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_rx_ilas_config_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="jesd204_rx_ilas_config" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>valid</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>addr</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>data</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/jesd204/interfaces/jesd204_rx_ilas_config_v1_0.sv
+92
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@@ -0,0 +1,92 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`ifndef jesd204_rx_ilas_config_v1_0
`define jesd204_rx_ilas_config_v1_0
package parameter_structs;
typedef struct packed {
bit portEnabled;
integer portWidth;
}portConfig;
typedef struct packed {
// <typeName> <LogicalName> = {<enablement>, <width>}
portConfig valid;
portConfig addr;
portConfig data;
}jesd204_rx_ilas_config_v1_0_port_configuration;
parameter jesd204_rx_ilas_config_v1_0_port_configuration jesd204_rx_ilas_config_v1_0_default_port_configuration = '{valid:'{1, -1}, addr:'{1, -1}, data:'{1, -1}};
endpackage
interface jesd204_rx_ilas_config_v1_0 #(parameter_structs::jesd204_rx_ilas_config_v1_0_port_configuration port_configuration)();
logic [port_configuration.valid.portWidth-1:0] valid; //
logic [port_configuration.addr.portWidth-1:0] addr; //
logic [port_configuration.data.portWidth-1:0] data; //
modport MASTER (
input data,
output valid, addr
);
modport SLAVE (
input valid, addr,
output data
);
modport MONITOR (
input valid, addr, data
);
endinterface // jesd204_rx_ilas_config_v1_0
`endif
adi_library/jesd204/interfaces/jesd204_rx_status.xml
+11
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_rx_status</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>
adi_library/jesd204/interfaces/jesd204_rx_status_rtl.xml
+144
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@@ -0,0 +1,144 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_rx_status_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="jesd204_rx_status" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>ctrl_state</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>3</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>3</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>lane_cgs_state</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>lane_emb_state</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>lane_frame_align</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>lane_ifs_ready</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>lane_latency_ready</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>lane_latency</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>err_statistics_cnt</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>synth_params0</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>synth_params1</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>synth_params2</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/jesd204/interfaces/jesd204_rx_status_v1_0.sv
+105
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@@ -0,0 +1,105 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`ifndef jesd204_rx_status_v1_0
`define jesd204_rx_status_v1_0
package parameter_structs;
typedef struct packed {
bit portEnabled;
integer portWidth;
}portConfig;
typedef struct packed {
// <typeName> <LogicalName> = {<enablement>, <width>}
portConfig lane_cgs_state;
portConfig lane_emb_state;
portConfig lane_frame_align;
portConfig lane_ifs_ready;
portConfig lane_latency_ready;
portConfig lane_latency;
portConfig err_statistics_cnt;
portConfig synth_params0;
portConfig synth_params1;
portConfig synth_params2;
}jesd204_rx_status_v1_0_port_configuration;
parameter jesd204_rx_status_v1_0_port_configuration jesd204_rx_status_v1_0_default_port_configuration = '{lane_cgs_state:'{1, -1}, lane_emb_state:'{1, -1}, lane_frame_align:'{1, -1}, lane_ifs_ready:'{1, -1}, lane_latency_ready:'{1, -1}, lane_latency:'{1, -1}, err_statistics_cnt:'{1, -1}, synth_params0:'{1, -1}, synth_params1:'{1, -1}, synth_params2:'{1, -1}};
endpackage
interface jesd204_rx_status_v1_0 #(parameter_structs::jesd204_rx_status_v1_0_port_configuration port_configuration)();
logic [2:0] ctrl_state; //
logic [port_configuration.lane_cgs_state.portWidth-1:0] lane_cgs_state; //
logic [port_configuration.lane_emb_state.portWidth-1:0] lane_emb_state; //
logic [port_configuration.lane_frame_align.portWidth-1:0] lane_frame_align; //
logic [port_configuration.lane_ifs_ready.portWidth-1:0] lane_ifs_ready; //
logic [port_configuration.lane_latency_ready.portWidth-1:0] lane_latency_ready; //
logic [port_configuration.lane_latency.portWidth-1:0] lane_latency; //
logic [port_configuration.err_statistics_cnt.portWidth-1:0] err_statistics_cnt; //
logic [port_configuration.synth_params0.portWidth-1:0] synth_params0; //
logic [port_configuration.synth_params1.portWidth-1:0] synth_params1; //
logic [port_configuration.synth_params2.portWidth-1:0] synth_params2; //
modport MASTER (
output ctrl_state, lane_cgs_state, lane_emb_state, lane_frame_align, lane_ifs_ready, lane_latency_ready, lane_latency, err_statistics_cnt, synth_params0, synth_params1, synth_params2
);
modport SLAVE (
input ctrl_state, lane_cgs_state, lane_emb_state, lane_frame_align, lane_ifs_ready, lane_latency_ready, lane_latency, err_statistics_cnt, synth_params0, synth_params1, synth_params2
);
modport MONITOR (
input ctrl_state, lane_cgs_state, lane_emb_state, lane_frame_align, lane_ifs_ready, lane_latency_ready, lane_latency, err_statistics_cnt, synth_params0, synth_params1, synth_params2
);
endinterface // jesd204_rx_status_v1_0
`endif
adi_library/jesd204/interfaces/jesd204_tx_cfg.xml
+11
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@@ -0,0 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_tx_cfg</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>
adi_library/jesd204/interfaces/jesd204_tx_cfg_rtl.xml
+230
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@@ -0,0 +1,230 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_tx_cfg_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="jesd204_tx_cfg" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>lanes_disable</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>links_disable</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>octets_per_multiframe</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>10</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>10</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>octets_per_frame</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>continuous_cgs</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>continuous_ilas</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>skip_ilas</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>mframes_per_ilas</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>disable_char_replacement</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>disable_scrambler</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_octets_per_multiframe</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>10</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>10</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_octets_per_frame</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_beats_per_multiframe</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_lmfc_offset</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>8</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_sysref_oneshot</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>device_sysref_disable</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/jesd204/interfaces/jesd204_tx_cfg_v1_0.sv
+102
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`ifndef jesd204_tx_cfg_v1_0
`define jesd204_tx_cfg_v1_0
package parameter_structs;
typedef struct packed {
bit portEnabled;
integer portWidth;
}portConfig;
typedef struct packed {
// <typeName> <LogicalName> = {<enablement>, <width>}
portConfig lanes_disable;
portConfig links_disable;
}jesd204_tx_cfg_v1_0_port_configuration;
parameter jesd204_tx_cfg_v1_0_port_configuration jesd204_tx_cfg_v1_0_default_port_configuration = '{lanes_disable:'{1, -1}, links_disable:'{1, -1}};
endpackage
interface jesd204_tx_cfg_v1_0 #(parameter_structs::jesd204_tx_cfg_v1_0_port_configuration port_configuration)();
logic [port_configuration.lanes_disable.portWidth-1:0] lanes_disable; //
logic [port_configuration.links_disable.portWidth-1:0] links_disable; //
logic [9:0] octets_per_multiframe; //
logic [7:0] octets_per_frame; //
logic continuous_cgs; //
logic continuous_ilas; //
logic skip_ilas; //
logic [7:0] mframes_per_ilas; //
logic disable_char_replacement; //
logic disable_scrambler; //
logic [9:0] device_octets_per_multiframe; //
logic [7:0] device_octets_per_frame; //
logic [7:0] device_beats_per_multiframe; //
logic [7:0] device_lmfc_offset; //
logic device_sysref_oneshot; //
logic device_sysref_disable; //
modport MASTER (
output lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, continuous_cgs, continuous_ilas, skip_ilas, mframes_per_ilas, disable_char_replacement, disable_scrambler, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable
);
modport SLAVE (
input lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, continuous_cgs, continuous_ilas, skip_ilas, mframes_per_ilas, disable_char_replacement, disable_scrambler, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable
);
modport MONITOR (
input lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, continuous_cgs, continuous_ilas, skip_ilas, mframes_per_ilas, disable_char_replacement, disable_scrambler, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable
);
endinterface // jesd204_tx_cfg_v1_0
`endif
adi_library/jesd204/interfaces/jesd204_tx_ctrl.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_tx_ctrl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>false</spirit:directConnection>
<spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves>
</spirit:busDefinition>
adi_library/jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
+24
View File
@@ -0,0 +1,24 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>interface</spirit:library>
<spirit:name>jesd204_tx_ctrl_rtl</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="jesd204_tx_ctrl" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>manual_sync_request</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
</spirit:onMaster>
<spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
adi_library/jesd204/interfaces/jesd204_tx_ctrl_v1_0.sv
+70
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@@ -0,0 +1,70 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`ifndef jesd204_tx_ctrl_v1_0
`define jesd204_tx_ctrl_v1_0
interface jesd204_tx_ctrl_v1_0();
logic manual_sync_request; //
modport MASTER (
output manual_sync_request
);
modport SLAVE (
input manual_sync_request
);
modport MONITOR (
input manual_sync_request
);
endinterface // jesd204_tx_ctrl_v1_0
`endif

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