initial commit, add dds_par module

2024-01-15 09:36:08 +08:00
commit 315a673005
1374 changed files with 465956 additions and 0 deletions
@@ -0,0 +1,42 @@
+####################################################################################
+## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := ad_ip_jesd204_tpl_adc
+
+GENERIC_DEPS += ../../common/ad_datafmt.v
+GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
+GENERIC_DEPS += ../../common/ad_pnmon.v
+GENERIC_DEPS += ../../common/ad_rst.v
+GENERIC_DEPS += ../../common/ad_xcvr_rx_if.v
+GENERIC_DEPS += ../../common/up_adc_channel.v
+GENERIC_DEPS += ../../common/up_adc_common.v
+GENERIC_DEPS += ../../common/up_axi.v
+GENERIC_DEPS += ../../common/up_clock_mon.v
+GENERIC_DEPS += ../../common/up_xfer_cntrl.v
+GENERIC_DEPS += ../../common/up_xfer_status.v
+GENERIC_DEPS += ../../common/util_ext_sync.v
+GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v
+GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v
+GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v
+GENERIC_DEPS += ad_ip_jesd204_tpl_adc_deframer.v
+GENERIC_DEPS += ad_ip_jesd204_tpl_adc_pnmon.v
+GENERIC_DEPS += ad_ip_jesd204_tpl_adc_regmap.v
+
+XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
+XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
+XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc
+XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc
+XILINX_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v
+XILINX_DEPS += ad_ip_jesd204_tpl_adc_ip.tcl
+
+INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
+INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
+INTEL_DEPS += ../../intel/common/up_xfer_cntrl_constr.sdc
+INTEL_DEPS += ../../intel/common/up_xfer_status_constr.sdc
+INTEL_DEPS += ../../jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
+INTEL_DEPS += ad_ip_jesd204_tpl_adc_hw.tcl
+
+include ../../scripts/library.mk
@@ -0,0 +1,240 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_ip_jesd204_tpl_adc #(
+  parameter ID = 0,
+  parameter FPGA_TECHNOLOGY = 0,
+  parameter FPGA_FAMILY = 0,
+  parameter SPEED_GRADE = 0,
+  parameter DEV_PACKAGE = 0,
+  parameter NUM_LANES = 1,
+  parameter NUM_CHANNELS = 4,
+  parameter SAMPLES_PER_FRAME = 1,
+  parameter CONVERTER_RESOLUTION = 14,
+  parameter BITS_PER_SAMPLE = 16,
+  parameter DMA_BITS_PER_SAMPLE = 16,
+  parameter OCTETS_PER_BEAT = 4,
+  parameter EN_FRAME_ALIGN = 1,
+  parameter TWOS_COMPLEMENT = 1,
+  parameter EXT_SYNC = 0,
+  parameter PN7_ENABLE = 1,
+  parameter PN15_ENABLE = 1
+) (
+
+  // jesd interface
+  // link_clk is (line-rate/40)
+  input link_clk,
+
+  input [OCTETS_PER_BEAT-1:0] link_sof,
+  input link_valid,
+  input [NUM_LANES*8*OCTETS_PER_BEAT-1:0] link_data,
+  output link_ready,
+
+  // dma interface
+
+  output [NUM_CHANNELS-1:0] enable,
+
+  output [NUM_CHANNELS-1:0] adc_valid,
+  output [DMA_BITS_PER_SAMPLE * OCTETS_PER_BEAT * 8 * NUM_LANES / BITS_PER_SAMPLE-1:0] adc_data,
+  input adc_dovf,
+
+  input adc_sync_in,
+  output adc_sync_manual_req_out,
+  input adc_sync_manual_req_in,
+
+  output adc_rst,
+
+  // axi interface
+
+  input s_axi_aclk,
+  input s_axi_aresetn,
+
+  input s_axi_awvalid,
+  output s_axi_awready,
+  input [12:0] s_axi_awaddr,
+  input [2:0] s_axi_awprot,
+
+  input s_axi_wvalid,
+  output s_axi_wready,
+  input [31:0] s_axi_wdata,
+  input [3:0] s_axi_wstrb,
+
+  output s_axi_bvalid,
+  input s_axi_bready,
+  output [1:0] s_axi_bresp,
+
+  input s_axi_arvalid,
+  output s_axi_arready,
+  input [12:0] s_axi_araddr,
+  input [2:0] s_axi_arprot,
+
+  output s_axi_rvalid,
+  input s_axi_rready,
+  output [1:0] s_axi_rresp,
+  output [31:0] s_axi_rdata
+);
+
+  // Number of samples per channel that are processed in parallel.
+  localparam DATA_PATH_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES / NUM_CHANNELS / BITS_PER_SAMPLE;
+  localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8;
+  localparam DMA_DATA_WIDTH = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH * NUM_CHANNELS;
+
+  localparam BYTES_PER_FRAME = (NUM_CHANNELS * BITS_PER_SAMPLE * SAMPLES_PER_FRAME) / ( 8 * NUM_LANES);
+
+  wire [NUM_CHANNELS-1:0] dfmt_enable_s;
+  wire [NUM_CHANNELS-1:0] dfmt_sign_extend_s;
+  wire [NUM_CHANNELS-1:0] dfmt_type_s;
+
+  wire [NUM_CHANNELS*4-1:0] pn_seq_sel_s;
+  wire [NUM_CHANNELS-1:0] pn_err_s;
+  wire [NUM_CHANNELS-1:0] pn_oos_s;
+
+  wire adc_rst_sync_s;
+  wire adc_rst_s;
+  wire adc_sync;
+  wire adc_sync_status;
+
+  assign adc_rst = adc_rst_s | adc_rst_sync_s;
+
+  // regmap
+  ad_ip_jesd204_tpl_adc_regmap #(
+    .ID (ID),
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+    .FPGA_FAMILY (FPGA_FAMILY),
+    .SPEED_GRADE (SPEED_GRADE),
+    .DEV_PACKAGE (DEV_PACKAGE),
+    .NUM_CHANNELS (NUM_CHANNELS),
+    .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
+    .NUM_PROFILES(1),
+    .EXT_SYNC (EXT_SYNC)
+  ) i_regmap (
+    .s_axi_aclk (s_axi_aclk),
+    .s_axi_aresetn (s_axi_aresetn),
+    .s_axi_awvalid (s_axi_awvalid),
+    .s_axi_awready (s_axi_awready),
+    .s_axi_awaddr (s_axi_awaddr),
+    .s_axi_awprot (s_axi_awprot),
+    .s_axi_wvalid (s_axi_wvalid),
+    .s_axi_wready (s_axi_wready),
+    .s_axi_wdata (s_axi_wdata),
+    .s_axi_wstrb (s_axi_wstrb),
+    .s_axi_bvalid (s_axi_bvalid),
+    .s_axi_bresp (s_axi_bresp),
+    .s_axi_bready (s_axi_bready),
+    .s_axi_arvalid (s_axi_arvalid),
+    .s_axi_arready (s_axi_arready),
+    .s_axi_araddr (s_axi_araddr),
+    .s_axi_arprot (s_axi_arprot),
+    .s_axi_rvalid (s_axi_rvalid),
+    .s_axi_rready (s_axi_rready),
+    .s_axi_rresp (s_axi_rresp),
+    .s_axi_rdata (s_axi_rdata),
+
+    .link_clk (link_clk),
+
+    .dfmt_enable (dfmt_enable_s),
+    .dfmt_sign_extend (dfmt_sign_extend_s),
+    .dfmt_type (dfmt_type_s),
+
+    .pn_seq_sel (pn_seq_sel_s),
+    .pn_err (pn_err_s),
+    .pn_oos (pn_oos_s),
+
+    .enable (enable),
+
+    .adc_sync (adc_sync),
+    .adc_sync_status (adc_sync_status),
+    .adc_ext_sync_arm (adc_ext_sync_arm),
+    .adc_ext_sync_disarm (adc_ext_sync_disarm),
+    .adc_ext_sync_manual_req (adc_sync_manual_req_out),
+
+    .adc_rst (adc_rst_s),
+
+    .adc_dovf (adc_dovf),
+
+    .jesd_m (NUM_CHANNELS),
+    .jesd_l (NUM_LANES),
+    .jesd_s (SAMPLES_PER_FRAME),
+    .jesd_f (BYTES_PER_FRAME),
+    .jesd_n (CONVERTER_RESOLUTION),
+    .jesd_np (BITS_PER_SAMPLE),
+    .up_profile_sel ());
+
+  ad_ip_jesd204_tpl_adc_core #(
+    .NUM_LANES (NUM_LANES),
+    .NUM_CHANNELS (NUM_CHANNELS),
+    .BITS_PER_SAMPLE (BITS_PER_SAMPLE),
+    .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
+    .SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
+    .EN_FRAME_ALIGN (EN_FRAME_ALIGN),
+    .OCTETS_PER_BEAT (OCTETS_PER_BEAT),
+    .LINK_DATA_WIDTH (LINK_DATA_WIDTH),
+    .DMA_DATA_WIDTH (DMA_DATA_WIDTH),
+    .TWOS_COMPLEMENT (TWOS_COMPLEMENT),
+    .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
+    .DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
+    .EXT_SYNC (EXT_SYNC),
+    .PN7_ENABLE (PN7_ENABLE),
+    .PN15_ENABLE(PN15_ENABLE)
+  ) i_core (
+    .clk (link_clk),
+
+    .dfmt_enable (dfmt_enable_s),
+    .dfmt_sign_extend (dfmt_sign_extend_s),
+    .dfmt_type (dfmt_type_s),
+
+    .pn_seq_sel (pn_seq_sel_s),
+    .pn_err (pn_err_s),
+    .pn_oos (pn_oos_s),
+
+    .link_valid (link_valid),
+    .link_ready (link_ready),
+    .link_sof (link_sof),
+    .link_data (link_data),
+
+    .adc_sync (adc_sync),
+    .adc_sync_status (adc_sync_status),
+    .adc_sync_in (adc_sync_in),
+    .adc_ext_sync_arm (adc_ext_sync_arm),
+    .adc_ext_sync_disarm (adc_ext_sync_disarm),
+    .adc_sync_manual_req (adc_sync_manual_req_in),
+    .adc_rst_sync (adc_rst_sync_s),
+
+    .adc_valid (adc_valid),
+    .adc_data (adc_data));
+
+endmodule
@@ -0,0 +1,556 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
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+  <DefaultLaunch Dir="$PRUNDIR"/>
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+      </File>
+      <File Path="$PPRDIR/bd/bd.tcl">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ad_ip_jesd204_tpl_adc"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../../xilinx/common/up_xfer_cntrl_constr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../xilinx/common/ad_rst_constr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../xilinx/common/up_xfer_status_constr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../xilinx/common/up_clock_mon_constr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="21">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Vivado 12-1790"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="1"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="Evaluation"/>
+    <MsgAttr Name="StringsToMatch" Val="features"/>
+    <MsgAttr Name="StringsToMatch" Val="should"/>
+    <MsgAttr Name="StringsToMatch" Val="NOT"/>
+    <MsgAttr Name="StringsToMatch" Val="be"/>
+    <MsgAttr Name="StringsToMatch" Val="used"/>
+    <MsgAttr Name="StringsToMatch" Val="in"/>
+    <MsgAttr Name="StringsToMatch" Val="production"/>
+    <MsgAttr Name="StringsToMatch" Val="systems."/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="Designutils 20-3303"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="10"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Place 30-73"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="11"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="axi_spi"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val=""/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="12"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="BD 41-1343"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="2"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="BD 41-1306"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="3"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ERROR"/>
+    <MsgAttr Name="Id" Val="BD 41-1276"/>
+    <MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="4"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="5"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="6"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-459"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="7"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="Synth 8-3331"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="8"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Synth 8-2490"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="9"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
@@ -0,0 +1,98 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_ip_jesd204_tpl_adc_channel #(
+  parameter CONVERTER_RESOLUTION = 14,
+  parameter DATA_PATH_WIDTH = 2,
+  parameter TWOS_COMPLEMENT = 1,
+  parameter BITS_PER_SAMPLE = 16,
+  parameter PN7_ENABLE = 1,
+  parameter PN15_ENABLE = 1
+) (
+  input clk,
+
+  input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] raw_data,
+
+  output [BITS_PER_SAMPLE*DATA_PATH_WIDTH-1:0] fmt_data,
+
+  // Configuration and status
+  input dfmt_enable,
+  input dfmt_type,
+  input dfmt_sign_extend,
+
+  input [3:0] pn_seq_sel,
+  output pn_oos,
+  output pn_err
+);
+
+  // instantiations
+
+  ad_ip_jesd204_tpl_adc_pnmon #(
+    .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
+    .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
+    .TWOS_COMPLEMENT (TWOS_COMPLEMENT),
+    .PN7_ENABLE (PN7_ENABLE),
+    .PN15_ENABLE(PN15_ENABLE)
+  ) i_pnmon (
+    .clk (clk),
+    .data (raw_data),
+
+    .pn_seq_sel (pn_seq_sel),
+    .pn_oos (pn_oos),
+    .pn_err (pn_err));
+
+  generate
+  genvar n;
+  for (n = 0; n < DATA_PATH_WIDTH; n = n + 1) begin: g_datafmt
+    ad_datafmt #(
+      .DATA_WIDTH (CONVERTER_RESOLUTION),
+      .BITS_PER_SAMPLE (BITS_PER_SAMPLE)
+    ) i_ad_datafmt (
+      .clk (clk),
+
+      .valid (1'b1),
+      .data (raw_data[n*CONVERTER_RESOLUTION+:CONVERTER_RESOLUTION]),
+      .valid_out (),
+      .data_out (fmt_data[n*BITS_PER_SAMPLE+:BITS_PER_SAMPLE]),
+
+      .dfmt_enable (dfmt_enable),
+      .dfmt_type (dfmt_type),
+      .dfmt_se (dfmt_sign_extend));
+  end
+  endgenerate
+
+endmodule
@@ -0,0 +1,155 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_ip_jesd204_tpl_adc_core #(
+  parameter NUM_LANES = 1,
+  parameter NUM_CHANNELS = 1,
+  parameter SAMPLES_PER_FRAME = 1,
+  parameter CONVERTER_RESOLUTION = 14,
+  parameter BITS_PER_SAMPLE = 16,
+  parameter DMA_BITS_PER_SAMPLE = 16,
+  parameter OCTETS_PER_BEAT = 4,
+  parameter EN_FRAME_ALIGN = 0,
+  parameter DATA_PATH_WIDTH = 1,
+  parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
+  parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * DMA_BITS_PER_SAMPLE * NUM_CHANNELS,
+  parameter TWOS_COMPLEMENT = 1,
+  parameter EXT_SYNC = 0,
+  parameter PN7_ENABLE = 1,
+  parameter PN15_ENABLE = 1
+) (
+  input clk,
+
+  input [NUM_CHANNELS-1:0] dfmt_enable,
+  input [NUM_CHANNELS-1:0] dfmt_sign_extend,
+  input [NUM_CHANNELS-1:0] dfmt_type,
+
+  input [NUM_CHANNELS*4-1:0] pn_seq_sel,
+  output [NUM_CHANNELS-1:0] pn_err,
+  output [NUM_CHANNELS-1:0] pn_oos,
+
+  output [NUM_CHANNELS-1:0] adc_valid,
+  output [DMA_DATA_WIDTH-1:0] adc_data,
+
+  input adc_sync,
+  output adc_sync_status,
+  input adc_ext_sync_arm,
+  input adc_ext_sync_disarm,
+  input adc_sync_in,
+  input adc_sync_manual_req,
+  output adc_rst_sync,
+
+  input link_valid,
+  output link_ready,
+  input [OCTETS_PER_BEAT-1:0] link_sof,
+  input [LINK_DATA_WIDTH-1:0] link_data
+);
+  // Raw and formatted channel data widths
+  localparam CDW_RAW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH;
+  localparam ADC_DATA_WIDTH = CDW_RAW * NUM_CHANNELS;
+  localparam CDW_FMT = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH;
+
+  wire [ADC_DATA_WIDTH-1:0] raw_data_s;
+  wire link_valid_tmp;
+
+  reg link_valid_d = 1'b0;
+  reg link_valid_dd = 1'b0;
+
+  assign link_ready = 1'b1;
+  assign link_valid_tmp = EN_FRAME_ALIGN ? link_valid_dd : link_valid_d;
+  assign adc_valid = {NUM_CHANNELS{link_valid_tmp & ~adc_sync_armed}};
+  assign adc_sync_status = adc_sync_armed;
+  assign adc_rst_sync = adc_sync_armed;
+
+  always @(posedge clk) begin
+    link_valid_d <= link_valid;
+    link_valid_dd <= link_valid_d;
+  end
+
+  // synchronization logic
+  util_ext_sync #(
+    .ENABLED (EXT_SYNC)
+  ) i_util_ext_sync (
+    .clk (clk),
+    .ext_sync_arm (adc_ext_sync_arm),
+    .ext_sync_disarm (adc_ext_sync_disarm),
+    .sync_in (adc_sync_in | adc_sync_manual_req),
+    .sync_armed (adc_sync_armed));
+
+  ad_ip_jesd204_tpl_adc_deframer #(
+    .NUM_LANES (NUM_LANES),
+    .NUM_CHANNELS (NUM_CHANNELS),
+    .BITS_PER_SAMPLE (BITS_PER_SAMPLE),
+    .CONVERTER_RESOLUTION  (CONVERTER_RESOLUTION),
+    .SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
+    .OCTETS_PER_BEAT (OCTETS_PER_BEAT),
+    .EN_FRAME_ALIGN (EN_FRAME_ALIGN),
+    .LINK_DATA_WIDTH (LINK_DATA_WIDTH),
+    .ADC_DATA_WIDTH (ADC_DATA_WIDTH)
+  ) i_deframer (
+    .clk (clk),
+    .link_sof (link_sof),
+    .link_data (link_data),
+    .adc_data (raw_data_s));
+
+  generate
+  genvar i;
+  for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
+    ad_ip_jesd204_tpl_adc_channel #(
+      .DATA_PATH_WIDTH (DATA_PATH_WIDTH),
+      .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
+      .TWOS_COMPLEMENT (TWOS_COMPLEMENT),
+      .BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
+      .PN7_ENABLE (PN7_ENABLE),
+      .PN15_ENABLE(PN15_ENABLE)
+    ) i_channel (
+      .clk (clk),
+
+      .raw_data (raw_data_s[CDW_RAW*i+:CDW_RAW]),
+      .fmt_data (adc_data[CDW_FMT*i+:CDW_FMT]),
+
+      .dfmt_enable (dfmt_enable[i]),
+      .dfmt_sign_extend (dfmt_sign_extend[i]),
+      .dfmt_type (dfmt_type[i]),
+
+      .pn_seq_sel (pn_seq_sel[i*4+:4]),
+      .pn_err (pn_err[i]),
+      .pn_oos (pn_oos[i]));
+  end
+  endgenerate
+
+endmodule
@@ -0,0 +1,133 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_ip_jesd204_tpl_adc_deframer #(
+  parameter NUM_LANES = 1,
+  parameter NUM_CHANNELS = 4,
+  parameter BITS_PER_SAMPLE = 16,
+  parameter CONVERTER_RESOLUTION = 14,
+  parameter SAMPLES_PER_FRAME = 1,
+  parameter OCTETS_PER_BEAT = 8,
+  parameter EN_FRAME_ALIGN = 0,
+  parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
+  parameter ADC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
+) (
+
+  // jesd interface
+  // clk is (line-rate/40)
+
+  input clk,
+  input [OCTETS_PER_BEAT-1:0] link_sof,
+  input [LINK_DATA_WIDTH-1:0] link_data,
+
+   // adc data output
+
+   output [ADC_DATA_WIDTH-1:0] adc_data
+);
+
+  localparam SAMPLES_PER_BEAT = ADC_DATA_WIDTH / CONVERTER_RESOLUTION;
+  localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME;
+  localparam BITS_PER_LANE_PER_FRAME = BITS_PER_CHANNEL_PER_FRAME *
+                                       NUM_CHANNELS / NUM_LANES;
+  localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME;
+
+  wire [LINK_DATA_WIDTH-1:0] link_data_s;
+  wire [LINK_DATA_WIDTH-1:0] link_data_msb_s;
+  wire [LINK_DATA_WIDTH-1:0] frame_data_s;
+  wire [LINK_DATA_WIDTH-1:0] adc_data_msb;
+
+  // data multiplex
+
+  genvar i;
+  genvar j;
+  generate
+    /* Reorder octets MSB first */
+    for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_adc_data
+      assign link_data_msb_s[i+:8] = link_data_s[LINK_DATA_WIDTH-1-i-:8];
+    end
+
+    /* Slice lanes into frames */
+    ad_perfect_shuffle #(
+      .NUM_GROUPS (NUM_LANES),
+      .WORDS_PER_GROUP (FRAMES_PER_BEAT),
+      .WORD_WIDTH (BITS_PER_LANE_PER_FRAME)
+    ) i_lanes_to_frames (
+      .data_in (link_data_msb_s),
+      .data_out (frame_data_s));
+
+    /* Slice frames into channels */
+    ad_perfect_shuffle #(
+      .NUM_GROUPS (FRAMES_PER_BEAT),
+      .WORDS_PER_GROUP (NUM_CHANNELS),
+      .WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME)
+    ) i_frames_to_channels (
+      .data_in (frame_data_s),
+      .data_out (adc_data_msb));
+
+    /* Reorder samples LSB first and remove tail bits */
+    for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin: g_dac_data_msb
+      localparam src_w = BITS_PER_SAMPLE;
+      localparam dst_w = CONVERTER_RESOLUTION;
+      localparam src_msb = LINK_DATA_WIDTH - 1 - i * src_w ;
+      localparam dst_lsb = i * dst_w;
+
+      assign adc_data[dst_lsb+:dst_w] = adc_data_msb[src_msb-:dst_w];
+    end
+  endgenerate
+
+  // frame-alignment
+
+  generate
+  genvar n;
+  if (EN_FRAME_ALIGN) begin
+  for (n = 0; n < NUM_LANES; n = n + 1) begin: g_xcvr_if
+    localparam DW = OCTETS_PER_BEAT * 8;
+    ad_xcvr_rx_if #(
+      .OCTETS_PER_BEAT (OCTETS_PER_BEAT)
+    ) i_xcvr_if (
+      .rx_clk (clk),
+      .rx_ip_sof (link_sof),
+      .rx_ip_data (link_data[n*DW+:DW]),
+      .rx_sof (),
+      .rx_data (link_data_s[n*DW+:DW]));
+  end
+  end else begin
+    assign link_data_s = link_data;
+  end
+  endgenerate
+
+endmodule
@@ -0,0 +1,279 @@
+###############################################################################
+## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+package require qsys 14.0
+source ../../../scripts/adi_env.tcl
+source ../../scripts/adi_ip_intel.tcl
+
+ad_ip_create ad_ip_jesd204_tpl_adc "JESD204 Transport Layer for ADCs" p_ad_ip_jesd204_tpl_adc_elab
+set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_adc_validate
+ad_ip_files ad_ip_jesd204_tpl_adc [list \
+  $ad_hdl_dir/library/common/ad_rst.v \
+  $ad_hdl_dir/library/common/ad_perfect_shuffle.v \
+  $ad_hdl_dir/library/common/ad_pnmon.v \
+  $ad_hdl_dir/library/common/ad_datafmt.v \
+  $ad_hdl_dir/library/common/up_axi.v \
+  $ad_hdl_dir/library/common/up_xfer_cntrl.v \
+  $ad_hdl_dir/library/common/up_xfer_status.v \
+  $ad_hdl_dir/library/common/up_clock_mon.v \
+  $ad_hdl_dir/library/common/up_adc_common.v \
+  $ad_hdl_dir/library/common/up_adc_channel.v \
+  $ad_hdl_dir/library/common/util_ext_sync.v \
+  $ad_hdl_dir/library/common/ad_xcvr_rx_if.v \
+  $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v \
+  $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v \
+  $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v \
+  $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v \
+  $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v \
+  $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v \
+  $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v \
+  $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
+  $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
+  $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
+  $ad_hdl_dir/library/intel/common/up_rst_constr.sdc]
+
+# parameters
+
+set group "General Configuration"
+
+ad_ip_parameter ID INTEGER 0 true [list \
+  DISPLAY_NAME "Core ID" \
+  GROUP $group \
+]
+
+ad_ip_parameter OCTETS_PER_BEAT INTEGER 4 true [list \
+  DISPLAY_NAME "Datapath width" \
+  DISPLAY_UNITS "octets" \
+  ALLOWED_RANGES {4 6 8 12} \
+  GROUP $group \
+]
+
+set group "JESD204 Deframer Configuration"
+
+ad_ip_parameter NUM_LANES INTEGER 1 true [list \
+  DISPLAY_NAME "Number of Lanes (L)" \
+  DISPLAY_UNITS "lanes" \
+  ALLOWED_RANGES {1 2 3 4 8 16 24 32} \
+  GROUP $group \
+]
+
+ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \
+  DISPLAY_NAME "Number of Converters (M)" \
+  DISPLAY_UNITS "converters" \
+  ALLOWED_RANGES {1 2 4 6 8 16 32 64} \
+  GROUP $group \
+]
+
+ad_ip_parameter BITS_PER_SAMPLE INTEGER 16 true [list \
+  DISPLAY_NAME "Bits per Sample (N')" \
+  ALLOWED_RANGES {8 12 16} \
+  UNITS bits \
+  GROUP $group \
+]
+
+ad_ip_parameter DMA_BITS_PER_SAMPLE INTEGER 16 true [list \
+  DISPLAY_NAME "DMA Bits per Sample" \
+  ALLOWED_RANGES {8 16} \
+  UNITS bits \
+  GROUP $group \
+]
+
+ad_ip_parameter CONVERTER_RESOLUTION INTEGER 16 true [list \
+  DISPLAY_NAME "Converter Resolution (N)" \
+  ALLOWED_RANGES {8 11 12 14 16} \
+  UNITS bits \
+  GROUP $group \
+]
+
+ad_ip_parameter ENABLE_SAMPLES_PER_FRAME_MANUAL BOOLEAN 0 false [list \
+  DISPLAY_NAME "Manual Samples per Frame" \
+  GROUP $group \
+]
+
+ad_ip_parameter SAMPLES_PER_FRAME INTEGER 1 true [list \
+  DISPLAY_NAME "Samples per Frame (S)" \
+  DISPLAY_UNITS "samples" \
+  ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
+  DERIVED true \
+  GROUP $group \
+]
+
+ad_ip_parameter SAMPLES_PER_FRAME_MANUAL INTEGER 1 false [list \
+  DISPLAY_NAME "Samples per Frame (S)" \
+  DISPLAY_UNITS "samples" \
+  ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
+  VISIBLE false \
+  GROUP $group \
+]
+
+ad_ip_parameter OCTETS_PER_FRAME INTEGER 1 false [list \
+  DISPLAY_NAME "Octets per Frame (F)" \
+  DISPLAY_UNITS "octets" \
+  ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
+  DERIVED true \
+  GROUP $group \
+]
+
+set group "Deframer Output Information"
+
+# Parameters in this group are informative only and can be read back after the
+# core has been configured to find out the expected layout of the input data.
+# E.g.
+#  set NUM_OF_CHANNELS  [get_instance_parameter_value jesd204_transport NUM_CHANNELS]
+#  set CHANNEL_DATA_WIDTH [get_instance_parameter_value jesd204_transport CHANNEL_DATA_WIDTH]
+#
+#  add_instance util_adc_cpack util_cpack
+#  set_instance_parameter_values util_adc_cpack [list \
+#    CHANNEL_DATA_WIDTH $CHANNEL_DATA_WIDTH \
+#    NUM_OF_CHANNELS $NUM_OF_CHANNELS \
+#  ]
+
+ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 false [list \
+  DISPLAY_NAME "Samples per Channel per Beat" \
+  DERIVED true \
+  GROUP $group \
+]
+
+ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 1 false [list \
+  DISPLAY_NAME "Channel Data Width" \
+  UNITS bits \
+  DERIVED true \
+  GROUP $group \
+]
+
+set group "Datapath Configuration"
+
+ad_ip_parameter TWOS_COMPLEMENT boolean 1 true [list \
+  DISPLAY_NAME "Twos Complement" \
+  GROUP $group \
+]
+ad_ip_parameter PN7_ENABLE boolean 1 true [list \
+  DISPLAY_NAME "Enable PN7" \
+  GROUP $group \
+]
+ad_ip_parameter PN15_ENABLE boolean 1 true [list \
+  DISPLAY_NAME "Enable PN15" \
+  GROUP $group \
+]
+
+# axi4 slave
+
+ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
+
+# core clock and start of frame
+
+add_interface link_clk clock end
+add_interface_port link_clk link_clk clk Input 1
+ad_interface signal link_sof input 4 export
+
+# We don't expect too large values for a and b, trivial implementation will do
+proc gcd {a b} {
+  if {$a == $b} {
+    return $b
+  } elseif {$a > $b} {
+    return [gcd [expr $a - $b] $b]
+  } else {
+    return [gcd $a [expr $b - $a]]
+  }
+}
+
+# validate
+
+proc p_ad_ip_jesd204_tpl_adc_validate {} {
+  set L [get_parameter_value "NUM_LANES"]
+  set M [get_parameter_value "NUM_CHANNELS"]
+  set NP [get_parameter_value "BITS_PER_SAMPLE"]
+  set N [get_parameter_value "CONVERTER_RESOLUTION"]
+  set S_manual [get_parameter_value "SAMPLES_PER_FRAME_MANUAL"]
+  set enable_S_manual [get_parameter_value "ENABLE_SAMPLES_PER_FRAME_MANUAL"]
+
+  # With fixed values for M, L and N' all valid values for S and F have a
+  # constant ratio of S / F. Choose a ratio so that S and F are co-prime.
+  # Choosing values for F and S that have a common factor has higher latency
+  # and no added benefits.
+  #
+  # Since converters often support those higher latency modes still allow a
+  # manual override of the S parameter in case somebody wants to use those modes
+  # anyway.
+  #
+  # To be able to set samples per frame manually ENABLE_SAMPLES_PER_FRAME_MANUAL
+  # needs to be set to true and SAMPLES_PER_FRAME_MANUAL to the desired value.
+  #
+  # When manual sample per frame selection is enabled still verify that the
+  # selected value is valid.
+
+  set S_min [expr $L * 8]
+  set F_min [expr $M * $NP]
+  set common_factor [gcd $S_min $F_min]
+  set S_min [expr $S_min / $common_factor]
+  set F_min [expr $F_min / $common_factor]
+
+  if {$enable_S_manual} {
+    if {$S_manual % $S_min != 0} {
+      send_message ERROR "For framer configuration (L=$L, M=$M, NP=$NP) samples per frame (S) must be an integer multiple of $S_min"
+      set S $S_min
+      set F $F_min
+    } else {
+      set S $S_manual
+      set F [expr $S_manual * $M * $NP / $L / 8]
+    }
+  } else {
+    set S $S_min
+    set F $F_min
+  }
+
+  set_parameter_value OCTETS_PER_FRAME $F
+  set_parameter_value SAMPLES_PER_FRAME $S
+
+  set_parameter_property SAMPLES_PER_FRAME VISIBLE [expr !$enable_S_manual]
+  set_parameter_property SAMPLES_PER_FRAME_MANUAL VISIBLE $enable_S_manual
+
+  set_parameter_value SAMPLES_PER_CHANNEL [expr 4 * $S / $F]
+  set_parameter_value CHANNEL_DATA_WIDTH [expr 16 * (4 * $S / $F)]
+
+}
+
+# elaborate
+
+proc p_ad_ip_jesd204_tpl_adc_elab {} {
+
+  # read core parameters
+
+  set L [get_parameter_value "NUM_LANES"]
+  set M [get_parameter_value "NUM_CHANNELS"]
+  set NP [get_parameter_value "BITS_PER_SAMPLE"]
+  set OPB [get_parameter_value "OCTETS_PER_BEAT"]
+  set DMA_BPS [get_parameter_value "DMA_BITS_PER_SAMPLE"]
+
+  # The DMA interface is rounded to nearest power of two bytes per sample,
+  # e.g NP=12 is padded into 16 bits
+  set samples_per_beat_per_channel [expr ($OPB * 8 * $L / ($M * $NP))]
+  set channel_bus_width [expr $samples_per_beat_per_channel*$DMA_BPS]
+
+  # link layer interface
+
+  add_interface link_data avalon_streaming sink
+  add_interface_port link_data link_data  data  input  [expr $OPB*8*$L]
+  add_interface_port link_data link_valid valid input  1
+  add_interface_port link_data link_ready ready output 1
+  set_interface_property link_data associatedClock link_clk
+  set_interface_property link_data dataBitsPerSymbol [expr $OPB*8*$L]
+
+  # dma interface
+
+  for {set i 0} {$i < $M} {incr i} {
+    add_interface adc_ch_$i conduit end
+    add_interface_port adc_ch_$i adc_enable_$i enable output 1
+    set_port_property adc_enable_$i fragment_list [format "enable(%d:%d)" $i $i]
+    add_interface_port adc_ch_$i adc_valid_$i  valid  output 1
+    set_port_property adc_valid_$i fragment_list [format "adc_valid(%d:%d)" $i $i]
+    add_interface_port adc_ch_$i adc_data_$i   data   output $channel_bus_width
+    set_port_property adc_data_$i fragment_list \
+          [format "adc_data(%d:%d)" [expr $channel_bus_width*$i+$channel_bus_width-1] [expr $channel_bus_width*$i]]
+    set_interface_property adc_ch_$i associatedClock link_clk
+  }
+
+  ad_interface signal  adc_dovf  input  1 ovf
+}
@@ -0,0 +1,135 @@
+###############################################################################
+## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+adi_ip_create ad_ip_jesd204_tpl_adc
+
+adi_ip_files ad_ip_jesd204_tpl_adc [list \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
+  "$ad_hdl_dir/library/common/ad_pnmon.v" \
+  "$ad_hdl_dir/library/common/ad_datafmt.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_xfer_status.v" \
+  "$ad_hdl_dir/library/common/up_clock_mon.v" \
+  "$ad_hdl_dir/library/common/up_adc_common.v" \
+  "$ad_hdl_dir/library/common/up_adc_channel.v" \
+  "$ad_hdl_dir/library/common/util_ext_sync.v" \
+  "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
+  "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
+  "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \
+  "ad_ip_jesd204_tpl_adc_core.v" \
+  "ad_ip_jesd204_tpl_adc_channel.v" \
+  "ad_ip_jesd204_tpl_adc_deframer.v" \
+  "ad_ip_jesd204_tpl_adc_pnmon.v" \
+  "ad_ip_jesd204_tpl_adc_regmap.v" \
+  "ad_ip_jesd204_tpl_adc.v" \
+  ]
+
+adi_ip_properties ad_ip_jesd204_tpl_adc
+
+adi_init_bd_tcl
+adi_ip_bd ad_ip_jesd204_tpl_adc "bd/bd.tcl"
+
+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_adc} [ipx::current_core]
+
+set cc [ipx::current_core]
+
+set_property display_name "JESD204 Transport Layer for ADCs" $cc
+set_property description "JESD204 Transport Layer for ADCs" $cc
+
+adi_add_bus "link" "master" \
+  "xilinx.com:interface:axis_rtl:1.0" \
+  "xilinx.com:interface:axis:1.0" \
+  [list \
+    {"link_ready" "TREADY"} \
+    {"link_valid" "TVALID"} \
+    {"link_data" "TDATA"} \
+  ]
+adi_add_bus_clock "link_clk" "link"
+
+adi_set_ports_dependency "adc_sync_in"             "EXT_SYNC == 1"
+adi_set_ports_dependency "adc_sync_manual_req_out" "EXT_SYNC == 1"
+adi_set_ports_dependency "adc_sync_manual_req_in"  "EXT_SYNC == 1"
+
+foreach {p v} {
+  "NUM_LANES" "1 2 3 4 6 8 12 16 24 32" \
+  "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
+  "BITS_PER_SAMPLE" "8 12 16" \
+  "DMA_BITS_PER_SAMPLE" "8 12 16" \
+  "CONVERTER_RESOLUTION" "8 11 12 14 16" \
+  "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
+  "OCTETS_PER_BEAT" "4 6 8 12 16 32 64" \
+} { \
+  set_property -dict [list \
+    "value_validation_type" "list" \
+    "value_validation_list" $v \
+  ] [ipx::get_user_parameters $p -of_objects $cc]
+}
+
+set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
+
+set general_group [ipgui::add_group -name "General Configuration" -component $cc \
+    -parent $page0 -display_name "General Configuration"]
+
+set p [ipgui::get_guiparamspec -name "ID" -component $cc]
+ipgui::move_param -component $cc -order 0 $p -parent $general_group
+set_property -dict [list \
+  "display_name" "Core ID" \
+] $p
+
+set framer_group [ipgui::add_group -name "JESD204 Deframer Configuration" -component $cc \
+    -parent $page0 -display_name "JESD204 Deframer Cofiguration"]
+
+set i 0
+
+foreach {k v} { \
+  "NUM_LANES" "Number of Lanes (L)" \
+  "NUM_CHANNELS" "Number of Conveters (M)" \
+  "BITS_PER_SAMPLE" "Bits per Sample (N')" \
+  "DMA_BITS_PER_SAMPLE" "DMA Bits per Sample" \
+  "CONVERTER_RESOLUTION" "Converter Resolution (N)" \
+  "SAMPLES_PER_FRAME" "Samples per Frame (S)" \
+  "OCTETS_PER_BEAT" "Octets per Beat" \
+  } { \
+  set p [ipgui::get_guiparamspec -name $k -component $cc]
+  ipgui::move_param -component $cc -order $i $p -parent $framer_group
+  set_property -dict [list \
+    WIDGET "comboBox" \
+    DISPLAY_NAME $v \
+  ] $p
+  incr i
+}
+
+set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \
+    -parent $page0 -display_name "Datapath Cofiguration"]
+
+set i 0
+
+foreach {k v w} {
+  "TWOS_COMPLEMENT" "Use twos complement" "checkBox" \
+  "EXT_SYNC" "Enable external sync" "checkBox" \
+  "PN7_ENABLE" "Enable PN7" "checkBox" \
+  "PN15_ENABLE" "Enable PN15" "checkBox" \
+  } { \
+  set p [ipgui::get_guiparamspec -name $k -component $cc]
+  ipgui::move_param -component $cc -order $i $p -parent $datapath_group
+  set_property -dict [list \
+    WIDGET $w \
+    DISPLAY_NAME $v \
+  ] $p
+  incr i
+}
+
+adi_add_auto_fpga_spec_params
+
+ipx::create_xgui_files [ipx::current_core]
+ipx::save_core [ipx::current_core]
@@ -0,0 +1,162 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_ip_jesd204_tpl_adc_pnmon #(
+  parameter CONVERTER_RESOLUTION = 16,
+  parameter DATA_PATH_WIDTH = 1,
+  parameter TWOS_COMPLEMENT = 1,
+  parameter PN7_ENABLE = 1,
+  parameter PN15_ENABLE = 1
+) (
+  input clk,
+
+  // data interface
+  input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] data,
+
+  // pn out of sync and error
+  output pn_oos,
+  output pn_err,
+
+  // processor interface PN9 (0x0), PN23 (0x1), PN7 (0x4), PN15 (0x5)
+  input [3:0] pn_seq_sel
+);
+
+  localparam DW = DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1;
+
+  // Max width of largest PN and data width
+  localparam PN_W = DW > 22 ? DW : 22;
+
+  // internal registers
+  reg [PN_W:0] pn_data_pn = 'd0;
+
+  // internal signals
+  wire [PN_W:0] pn_data_pn_s;
+  wire [DW:0] pn_data_in_s;
+  wire [PN_W:0] pn_data_init;
+
+  wire [DW:0] pn23;
+  wire [DW+23:0] full_state_pn23;
+  wire [DW:0] pn9;
+  wire [DW+9:0] full_state_pn9;
+  wire [DW:0] pn7;
+  wire [DW+7:0] full_state_pn7;
+  wire [DW:0] pn15;
+  wire [DW+15:0] full_state_pn15;
+
+  // pn sequence select
+  generate if (PN_W > DW) begin
+    reg [PN_W-DW-1:0] pn_data_in_d = 'd0;
+    always @(posedge clk) begin
+      pn_data_in_d <= pn_data_in_s[PN_W-DW-1:0];
+    end
+    assign pn_data_init = {pn_data_in_d, pn_data_in_s};
+  end else begin
+    assign pn_data_init = pn_data_in_s;
+  end
+  endgenerate
+
+  assign pn_data_pn_s = (pn_oos == 1'b1) ? pn_data_init : pn_data_pn;
+
+  wire tc = TWOS_COMPLEMENT ? 1'b1 : 1'b0;
+
+  generate
+  genvar i;
+  for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_pn_swizzle
+    localparam src_lsb = i * CONVERTER_RESOLUTION;
+    localparam src_msb = src_lsb + CONVERTER_RESOLUTION - 1;
+    localparam dst_lsb = (DATA_PATH_WIDTH - i - 1) * CONVERTER_RESOLUTION;
+    localparam dst_msb = dst_lsb + CONVERTER_RESOLUTION - 1;
+
+    assign pn_data_in_s[dst_msb] = (~tc) ^ data[src_msb];
+    assign pn_data_in_s[dst_msb-1:dst_lsb] = data[src_msb-1:src_lsb];
+  end
+  endgenerate
+
+  // PN23 x^23 + x^18 + 1
+  assign pn23 = full_state_pn23[23+:DW+1] ^ full_state_pn23[18+:DW+1];
+  assign full_state_pn23 = {pn_data_pn_s[22:0],pn23};
+
+  // PN9 x^9 + x^5 + 1
+  assign pn9 = full_state_pn9[9+:DW+1] ^ full_state_pn9[5+:DW+1];
+  assign full_state_pn9 = {pn_data_pn_s[8:0],pn9};
+
+  always @(posedge clk) begin
+    if (pn_seq_sel == 4'd0) begin
+      pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn9}  : pn9;
+    end else if (pn_seq_sel == 4'd1) begin
+      pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn23} : pn23;
+    end else if (pn_seq_sel == 4'd4) begin
+      pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn7}  : pn7;
+    end else if (pn_seq_sel == 4'd5) begin
+      pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn15} : pn15;
+    end
+  end
+
+ // specific PN sequences
+
+  generate
+    if(PN7_ENABLE == 'b1) begin
+     // PN7  x^7 + x^6 + 1
+     assign pn7 = full_state_pn7[7+:DW+1] ^ full_state_pn7[6+:DW+1];
+     assign full_state_pn7 = {pn_data_pn_s[6:0],pn7};
+    end else begin
+     assign pn7 = 'd0;
+     assign full_state_pn7 = 'd0;
+    end
+    if(PN15_ENABLE == 'b1)  begin
+     // PN15 x^15 + x^14 + 1
+     assign pn15 = full_state_pn15[15+:DW+1] ^ full_state_pn15[14+:DW+1];
+     assign full_state_pn15 = {pn_data_pn_s[14:0],pn15};
+    end else begin
+     assign pn15 = 'd0;
+     assign full_state_pn15 = 'd0;
+    end
+  endgenerate
+
+  // pn oos & pn err
+
+  ad_pnmon #(
+    .DATA_WIDTH (DW+1)
+  ) i_pnmon (
+    .adc_clk (clk),
+    .adc_valid_in (1'b1),
+    .adc_data_in (pn_data_in_s),
+    .adc_data_pn (pn_data_pn[DW:0]),
+    .adc_pn_oos (pn_oos),
+    .adc_pn_err (pn_err));
+
+endmodule
@@ -0,0 +1,366 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_ip_jesd204_tpl_adc_regmap #(
+  parameter ID = 0,
+  parameter FPGA_TECHNOLOGY = 0,
+  parameter FPGA_FAMILY = 0,
+  parameter SPEED_GRADE = 0,
+  parameter DEV_PACKAGE = 0,
+  parameter NUM_CHANNELS = 1,
+  parameter DATA_PATH_WIDTH = 1,
+  parameter NUM_PROFILES = 1,    // Number of supported JESD profiles
+  parameter EXT_SYNC = 0
+) (
+
+  // axi interface
+  input s_axi_aclk,
+  input s_axi_aresetn,
+  input s_axi_awvalid,
+  input [12:0] s_axi_awaddr,
+  input [2:0] s_axi_awprot,
+  output s_axi_awready,
+  input s_axi_wvalid,
+  input [31:0] s_axi_wdata,
+  input [3:0] s_axi_wstrb,
+  output s_axi_wready,
+  output s_axi_bvalid,
+  output [ 1:0] s_axi_bresp,
+  input s_axi_bready,
+  input s_axi_arvalid,
+  input [12:0] s_axi_araddr,
+  input [2:0] s_axi_arprot,
+  output s_axi_arready,
+  output s_axi_rvalid,
+  output [1:0] s_axi_rresp,
+  output [31:0] s_axi_rdata,
+  input s_axi_rready,
+
+  // control interface
+  input link_clk,
+
+  // Data format conversion configuration
+  output [NUM_CHANNELS-1:0] dfmt_enable,
+  output [NUM_CHANNELS-1:0] dfmt_sign_extend,
+  output [NUM_CHANNELS-1:0] dfmt_type,
+
+  // PN sequence monitor
+  output [NUM_CHANNELS*4-1:0] pn_seq_sel,
+  input [NUM_CHANNELS-1:0] pn_err,
+  input [NUM_CHANNELS-1:0] pn_oos,
+
+  output [NUM_CHANNELS-1:0] enable,
+
+  input adc_sync_status,
+  output adc_sync,
+  output adc_ext_sync_arm,
+  output adc_ext_sync_disarm,
+  output adc_ext_sync_manual_req,
+  output adc_rst,
+
+  // Underflow
+  input adc_dovf,
+
+  // Deframer interface
+  input [NUM_PROFILES*8-1: 0] jesd_m,
+  input [NUM_PROFILES*8-1: 0] jesd_l,
+  input [NUM_PROFILES*8-1: 0] jesd_s,
+  input [NUM_PROFILES*8-1: 0] jesd_f,
+  input [NUM_PROFILES*8-1: 0] jesd_n,
+  input [NUM_PROFILES*8-1: 0] jesd_np,
+
+  output [$clog2(NUM_PROFILES):0] up_profile_sel
+);
+
+  localparam [31:0] CLK_RATIO = DATA_PATH_WIDTH;
+
+  reg up_rack = 1'b0;
+  reg up_wack = 1'b0;
+  reg [31:0] up_rdata = 32'h00;
+  reg [31:0] up_rdata_all;
+
+  reg up_status_pn_err = 1'b0;
+  reg up_status_pn_oos = 1'b0;
+
+  reg adc_status = 1'b0;
+
+  // internal clocks & resets
+  wire up_clk;
+  wire up_rstn;
+
+  wire up_wreq_s;
+  wire [10:0] up_waddr_s;
+  wire [31:0] up_wdata_s;
+  wire [NUM_CHANNELS+1:0] up_wack_s;
+  wire up_rreq_s;
+  wire [10:0] up_raddr_s;
+  wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
+  wire [NUM_CHANNELS+1:0] up_rack_s;
+
+  wire [NUM_CHANNELS-1:0] up_adc_pn_err_s;
+  wire [NUM_CHANNELS-1:0] up_adc_pn_oos_s;
+
+  // signal name changes
+
+  assign up_clk = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+
+  // status
+
+  always @(posedge link_clk) begin
+    if (adc_rst == 1'b1) begin
+      adc_status <= 1'b0;
+    end else begin
+      adc_status <= 1'b1;
+    end
+  end
+
+  // up bus interface
+
+  up_axi #(
+    .AXI_ADDRESS_WIDTH (13)
+  ) i_up_axi (
+    .up_clk (up_clk),
+    .up_rstn (up_rstn),
+
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr ({3'b0,s_axi_awaddr}),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr ({3'b0,s_axi_araddr}),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+  integer n;
+
+  always @(*) begin
+    up_rdata_all = 'h00;
+    for (n = 0; n <= NUM_CHANNELS+1; n = n + 1) begin
+      up_rdata_all = up_rdata_all | up_rdata_s[n];
+    end
+  end
+
+  always @(posedge up_clk) begin
+    if (up_rstn == 1'b0) begin
+      up_status_pn_err <= 'd0;
+      up_status_pn_oos <= 'd0;
+      up_rdata <= 'd0;
+      up_rack <= 'd0;
+      up_wack <= 'd0;
+    end else begin
+      up_status_pn_err <= |up_adc_pn_err_s;
+      up_status_pn_oos <= |up_adc_pn_oos_s;
+
+      up_rdata <= up_rdata_all;
+      up_rack <= |up_rack_s;
+      up_wack <= |up_wack_s;
+    end
+  end
+
+  // common processor control
+  //
+  localparam CONFIG = (EXT_SYNC << 12);
+
+  up_adc_common #(
+    .COMMON_ID (6'h0),
+    .ID (ID),
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+    .FPGA_FAMILY (FPGA_FAMILY),
+    .SPEED_GRADE (SPEED_GRADE),
+    .DEV_PACKAGE (DEV_PACKAGE),
+    .DRP_DISABLE (1),
+    .USERPORTS_DISABLE (1),
+    .GPIO_DISABLE (1),
+    .START_CODE_DISABLE (1),
+    .CONFIG (CONFIG)
+  ) i_up_adc_common (
+    .mmcm_rst (),
+    .adc_clk (link_clk),
+    .adc_rst (adc_rst),
+    .adc_r1_mode (),
+    .adc_ddr_edgesel (),
+    .adc_pin_mode (),
+    .adc_status (adc_status),
+    .adc_sync_status (adc_sync_status),
+    .adc_status_ovf (adc_dovf),
+    .adc_clk_ratio (CLK_RATIO),
+    .adc_start_code (),
+    .adc_sref_sync (),
+    .adc_sync (adc_sync),
+    .adc_ext_sync_arm (adc_ext_sync_arm),
+    .adc_ext_sync_disarm (adc_ext_sync_disarm),
+    .adc_ext_sync_manual_req (adc_ext_sync_manual_req),
+
+    .up_status_pn_err (up_status_pn_err),
+    .up_status_pn_oos (up_status_pn_oos),
+    .up_status_or (1'b0),
+    .up_drp_sel (),
+    .up_drp_wr (),
+    .up_drp_addr (),
+    .up_drp_wdata (),
+    .up_drp_rdata (32'd0),
+    .up_drp_ready (1'd0),
+    .up_drp_locked (1'd1),
+    .adc_config_wr (),
+    .adc_config_ctrl (),
+    .adc_config_rd ('d0),
+    .adc_ctrl_status ('d0),
+    .up_usr_chanmax_out (),
+    .up_usr_chanmax_in (NUM_CHANNELS),
+    .up_adc_gpio_in (32'd0),
+    .up_adc_gpio_out (),
+    .up_adc_ce (),
+    .up_pps_rcounter (32'd0),
+    .up_pps_status (1'b0),
+    .up_pps_irq_mask (),
+
+    .up_clk (up_clk),
+    .up_rstn (up_rstn),
+    .up_wreq (up_wreq_s),
+    .up_waddr ({3'b0,up_waddr_s}),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq_s),
+    .up_raddr ({3'b0,up_raddr_s}),
+    .up_rdata (up_rdata_s[0]),
+    .up_rack (up_rack_s[0]));
+
+  generate
+  genvar i;
+  for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
+    up_adc_channel #(
+      .COMMON_ID (6'h1 + i/16),
+      .CHANNEL_ID (i % 16),
+      .USERPORTS_DISABLE (1),
+      .DCFILTER_DISABLE (1),
+      .IQCORRECTION_DISABLE (1)
+    ) i_up_adc_channel (
+      .adc_clk (link_clk),
+      .adc_rst (adc_rst),
+      .adc_enable (enable[i]),
+      .adc_iqcor_enb (),
+      .adc_dcfilt_enb (),
+      .adc_dfmt_enable (dfmt_enable[i]),
+      .adc_dfmt_se (dfmt_sign_extend[i]),
+      .adc_dfmt_type (dfmt_type[i]),
+      .adc_dcfilt_offset (),
+      .adc_dcfilt_coeff (),
+      .adc_iqcor_coeff_1 (),
+      .adc_iqcor_coeff_2 (),
+      .adc_pnseq_sel (pn_seq_sel[i*4+:4]),
+      .adc_data_sel (),
+      .adc_pn_err (pn_err[i]),
+      .adc_pn_oos (pn_oos[i]),
+      .adc_or (1'b0),
+      .adc_usr_datatype_be (1'b0),
+      .adc_usr_datatype_signed (1'b1),
+      .adc_usr_datatype_shift (8'd0),
+      .adc_usr_datatype_total_bits (8'd16),
+      .adc_usr_datatype_bits (8'd16),
+      .adc_usr_decimation_m (16'd1),
+      .adc_usr_decimation_n (16'd1),
+
+      .up_adc_pn_err (up_adc_pn_err_s[i]),
+      .up_adc_pn_oos (up_adc_pn_oos_s[i]),
+      .up_adc_or (),
+      .up_usr_datatype_be (),
+      .up_usr_datatype_signed (),
+      .up_usr_datatype_shift (),
+      .up_usr_datatype_total_bits (),
+      .up_usr_datatype_bits (),
+      .up_usr_decimation_m (),
+      .up_usr_decimation_n (),
+
+      .up_clk (up_clk),
+      .up_rstn (up_rstn),
+      .up_wreq (up_wreq_s),
+      .up_waddr ({3'b0,up_waddr_s}),
+      .up_wdata (up_wdata_s),
+      .up_wack (up_wack_s[i+1]),
+      .up_rreq (up_rreq_s),
+      .up_raddr ({3'b0,up_raddr_s}),
+      .up_rdata (up_rdata_s[i+1]),
+      .up_rack (up_rack_s[i+1]));
+  end
+  endgenerate
+
+  up_tpl_common #(
+    .COMMON_ID(2'h0),            // Offset of regmap
+    .NUM_PROFILES(NUM_PROFILES)  // Number of JESD profiles
+  ) i_up_tpl_adc (
+    .jesd_m (jesd_m),
+    .jesd_l (jesd_l),
+    .jesd_s (jesd_s),
+    .jesd_f (jesd_f),
+    .jesd_n (jesd_n),
+    .jesd_np (jesd_np),
+
+    .up_profile_sel (up_profile_sel),
+
+    // bus interface
+    .up_clk (up_clk),
+    .up_rstn (up_rstn),
+
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[NUM_CHANNELS+1]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[NUM_CHANNELS+1]),
+    .up_rack (up_rack_s[NUM_CHANNELS+1]));
+
+endmodule
@@ -0,0 +1,47 @@
+# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
+proc init {cellpath otherInfo} {
+  set ip [get_bd_cells $cellpath]
+
+  bd::mark_propagate_only $ip " \
+    DEV_PACKAGE \
+    SPEED_GRADE \
+    FPGA_FAMILY \
+    FPGA_TECHNOLOGY"
+
+  adi_auto_assign_device_spec $cellpath
+}
+
+# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
+proc adi_auto_assign_device_spec {cellpath} {
+
+  set ip [get_bd_cells $cellpath]
+  set ip_param_list [list_property $ip]
+  set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
+
+  set parent_dir "../"
+  for {set x 1} {$x<=4} {incr x} {
+    set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
+    if { [file exists $linkname] } {
+      source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
+      break
+    }
+    append parent_dir "../"
+  }
+
+  # Find predefindes auto assignable parameters
+  foreach i $auto_set_param_list {
+    if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
+      set val [adi_device_spec $cellpath $i]
+      set_property CONFIG.$i $val $ip
+    }
+  }
+
+  # Find predefindes auto assignable/overwritable parameters
+  foreach i $auto_set_param_list_overwritable {
+    if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
+      set val [adi_device_spec $cellpath $i]
+      set_property CONFIG.$i $val $ip
+    }
+  }
+}
+
@@ -0,0 +1,2 @@
+CLEAN_TARGET += bd
+CLEAN_TARGET += temporary_case_dependencies.mk
@@ -0,0 +1,277 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "EN_FRAME_ALIGN" -parent ${Page_0}
+  #Adding Group
+  set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}]
+  ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}
+
+  #Adding Group
+  set JESD204_Deframer_Configuration [ipgui::add_group $IPINST -name "JESD204 Deframer Configuration" -parent ${Page_0} -display_name {JESD204 Deframer Cofiguration}]
+  ipgui::add_param $IPINST -name "NUM_LANES" -parent ${JESD204_Deframer_Configuration} -widget comboBox
+  ipgui::add_param $IPINST -name "NUM_CHANNELS" -parent ${JESD204_Deframer_Configuration} -widget comboBox
+  ipgui::add_param $IPINST -name "BITS_PER_SAMPLE" -parent ${JESD204_Deframer_Configuration} -widget comboBox
+  ipgui::add_param $IPINST -name "DMA_BITS_PER_SAMPLE" -parent ${JESD204_Deframer_Configuration} -widget comboBox
+  ipgui::add_param $IPINST -name "CONVERTER_RESOLUTION" -parent ${JESD204_Deframer_Configuration} -widget comboBox
+  ipgui::add_param $IPINST -name "SAMPLES_PER_FRAME" -parent ${JESD204_Deframer_Configuration} -widget comboBox
+  ipgui::add_param $IPINST -name "OCTETS_PER_BEAT" -parent ${JESD204_Deframer_Configuration} -widget comboBox
+
+  #Adding Group
+  set Datapath_Configuration [ipgui::add_group $IPINST -name "Datapath Configuration" -parent ${Page_0} -display_name {Datapath Cofiguration}]
+  ipgui::add_param $IPINST -name "TWOS_COMPLEMENT" -parent ${Datapath_Configuration} -widget checkBox
+  ipgui::add_param $IPINST -name "EXT_SYNC" -parent ${Datapath_Configuration} -widget checkBox
+  ipgui::add_param $IPINST -name "PN7_ENABLE" -parent ${Datapath_Configuration} -widget checkBox
+  ipgui::add_param $IPINST -name "PN15_ENABLE" -parent ${Datapath_Configuration} -widget checkBox
+
+  #Adding Group
+  set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
+  ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
+  ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
+  ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
+  ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
+
+
+
+}
+
+proc update_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
+	# Procedure called to update BITS_PER_SAMPLE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
+	# Procedure called to validate BITS_PER_SAMPLE
+	return true
+}
+
+proc update_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
+	# Procedure called to update CONVERTER_RESOLUTION when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
+	# Procedure called to validate CONVERTER_RESOLUTION
+	return true
+}
+
+proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
+	# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
+	# Procedure called to validate DEV_PACKAGE
+	return true
+}
+
+proc update_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } {
+	# Procedure called to update DMA_BITS_PER_SAMPLE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } {
+	# Procedure called to validate DMA_BITS_PER_SAMPLE
+	return true
+}
+
+proc update_PARAM_VALUE.EN_FRAME_ALIGN { PARAM_VALUE.EN_FRAME_ALIGN } {
+	# Procedure called to update EN_FRAME_ALIGN when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.EN_FRAME_ALIGN { PARAM_VALUE.EN_FRAME_ALIGN } {
+	# Procedure called to validate EN_FRAME_ALIGN
+	return true
+}
+
+proc update_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } {
+	# Procedure called to update EXT_SYNC when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } {
+	# Procedure called to validate EXT_SYNC
+	return true
+}
+
+proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
+	# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
+	# Procedure called to validate FPGA_FAMILY
+	return true
+}
+
+proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
+	# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
+	# Procedure called to validate FPGA_TECHNOLOGY
+	return true
+}
+
+proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to update ID when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to validate ID
+	return true
+}
+
+proc update_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
+	# Procedure called to update NUM_CHANNELS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
+	# Procedure called to validate NUM_CHANNELS
+	return true
+}
+
+proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
+	# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
+	# Procedure called to validate NUM_LANES
+	return true
+}
+
+proc update_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
+	# Procedure called to update OCTETS_PER_BEAT when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
+	# Procedure called to validate OCTETS_PER_BEAT
+	return true
+}
+
+proc update_PARAM_VALUE.PN15_ENABLE { PARAM_VALUE.PN15_ENABLE } {
+	# Procedure called to update PN15_ENABLE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.PN15_ENABLE { PARAM_VALUE.PN15_ENABLE } {
+	# Procedure called to validate PN15_ENABLE
+	return true
+}
+
+proc update_PARAM_VALUE.PN7_ENABLE { PARAM_VALUE.PN7_ENABLE } {
+	# Procedure called to update PN7_ENABLE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.PN7_ENABLE { PARAM_VALUE.PN7_ENABLE } {
+	# Procedure called to validate PN7_ENABLE
+	return true
+}
+
+proc update_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
+	# Procedure called to update SAMPLES_PER_FRAME when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
+	# Procedure called to validate SAMPLES_PER_FRAME
+	return true
+}
+
+proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
+	# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
+	# Procedure called to validate SPEED_GRADE
+	return true
+}
+
+proc update_PARAM_VALUE.TWOS_COMPLEMENT { PARAM_VALUE.TWOS_COMPLEMENT } {
+	# Procedure called to update TWOS_COMPLEMENT when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.TWOS_COMPLEMENT { PARAM_VALUE.TWOS_COMPLEMENT } {
+	# Procedure called to validate TWOS_COMPLEMENT
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
+}
+
+proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
+}
+
+proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
+}
+
+proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
+}
+
+proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
+}
+
+proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
+}
+
+proc update_MODELPARAM_VALUE.NUM_CHANNELS { MODELPARAM_VALUE.NUM_CHANNELS PARAM_VALUE.NUM_CHANNELS } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.NUM_CHANNELS}] ${MODELPARAM_VALUE.NUM_CHANNELS}
+}
+
+proc update_MODELPARAM_VALUE.SAMPLES_PER_FRAME { MODELPARAM_VALUE.SAMPLES_PER_FRAME PARAM_VALUE.SAMPLES_PER_FRAME } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_FRAME}] ${MODELPARAM_VALUE.SAMPLES_PER_FRAME}
+}
+
+proc update_MODELPARAM_VALUE.CONVERTER_RESOLUTION { MODELPARAM_VALUE.CONVERTER_RESOLUTION PARAM_VALUE.CONVERTER_RESOLUTION } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.CONVERTER_RESOLUTION}] ${MODELPARAM_VALUE.CONVERTER_RESOLUTION}
+}
+
+proc update_MODELPARAM_VALUE.BITS_PER_SAMPLE { MODELPARAM_VALUE.BITS_PER_SAMPLE PARAM_VALUE.BITS_PER_SAMPLE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.BITS_PER_SAMPLE}
+}
+
+proc update_MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE { MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE PARAM_VALUE.DMA_BITS_PER_SAMPLE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DMA_BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE}
+}
+
+proc update_MODELPARAM_VALUE.OCTETS_PER_BEAT { MODELPARAM_VALUE.OCTETS_PER_BEAT PARAM_VALUE.OCTETS_PER_BEAT } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_BEAT}] ${MODELPARAM_VALUE.OCTETS_PER_BEAT}
+}
+
+proc update_MODELPARAM_VALUE.EN_FRAME_ALIGN { MODELPARAM_VALUE.EN_FRAME_ALIGN PARAM_VALUE.EN_FRAME_ALIGN } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.EN_FRAME_ALIGN}] ${MODELPARAM_VALUE.EN_FRAME_ALIGN}
+}
+
+proc update_MODELPARAM_VALUE.TWOS_COMPLEMENT { MODELPARAM_VALUE.TWOS_COMPLEMENT PARAM_VALUE.TWOS_COMPLEMENT } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.TWOS_COMPLEMENT}] ${MODELPARAM_VALUE.TWOS_COMPLEMENT}
+}
+
+proc update_MODELPARAM_VALUE.EXT_SYNC { MODELPARAM_VALUE.EXT_SYNC PARAM_VALUE.EXT_SYNC } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.EXT_SYNC}] ${MODELPARAM_VALUE.EXT_SYNC}
+}
+
+proc update_MODELPARAM_VALUE.PN7_ENABLE { MODELPARAM_VALUE.PN7_ENABLE PARAM_VALUE.PN7_ENABLE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.PN7_ENABLE}] ${MODELPARAM_VALUE.PN7_ENABLE}
+}
+
+proc update_MODELPARAM_VALUE.PN15_ENABLE { MODELPARAM_VALUE.PN15_ENABLE PARAM_VALUE.PN15_ENABLE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.PN15_ENABLE}] ${MODELPARAM_VALUE.PN15_ENABLE}
+}
+