initial commit, add dds_par module
This commit is contained in:
@@ -0,0 +1,18 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_jesd204_common
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GENERIC_DEPS += jesd204_up_common.v
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GENERIC_DEPS += jesd204_up_sysref.v
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XILINX_DEPS += ../../common/up_clock_mon.v
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XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += axi_jesd204_common_ip.tcl
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XILINX_LIB_DEPS += util_cdc
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include ../../scripts/library.mk
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@@ -0,0 +1,420 @@
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<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,31 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2016, 2017, 2019, 2022, 2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create axi_jesd204_common
|
||||
|
||||
add_files -fileset [get_filesets sources_1] [list \
|
||||
"../../xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"../../common/up_clock_mon.v" \
|
||||
"jesd204_up_common.v" \
|
||||
"jesd204_up_sysref.v" \
|
||||
]
|
||||
|
||||
set_property source_mgmt_mode DisplayOnly [current_project]
|
||||
|
||||
adi_ip_properties_lite axi_jesd204_common
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
]
|
||||
set_property display_name "ADI AXI JESD204B Common Library" [ipx::current_core]
|
||||
set_property description "ADI AXI JESD204B Common Library" [ipx::current_core]
|
||||
set_property hide_in_gui {1} [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,388 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axi_jesd204_common</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>jesd204_up_sysref</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>c4c41562</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>jesd204_up_sysref</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>dd8aa7f3</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>f92e9879</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>up_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>core_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>device_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_raddr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">11</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_rdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_wreq</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_waddr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">11</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_wdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_cfg_is_writeable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_cfg_sysref_oneshot</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_cfg_lmfc_offset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>up_cfg_sysref_disable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>device_event_sysref_alignment_error</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>device_event_sysref_edge</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../xilinx/common/up_clock_mon_constr.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../common/up_clock_mon.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>jesd204_up_common.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>jesd204_up_sysref.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_682078ff</spirit:userFileType>
|
||||
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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<spirit:name>../../common/up_clock_mon.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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|
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<spirit:name>jesd204_up_common.v</spirit:name>
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<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0"/>
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|
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</spirit:vendorExtensions>
|
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</spirit:fileSet>
|
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</spirit:fileSets>
|
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<spirit:description>ADI AXI JESD204B Common Library</spirit:description>
|
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|
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<spirit:parameter>
|
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<spirit:name>Component_Name</spirit:name>
|
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">jesd204_up_sysref_v1_0</spirit:value>
|
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</spirit:parameter>
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<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>ADI AXI JESD204B Common Library</xilinx:displayName>
|
||||
<xilinx:hideInCatalogGUI>true</xilinx:hideInCatalogGUI>
|
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-14T03:50:49Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f09a8047"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="7105858c"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="5ef422d3"/>
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</xilinx:packagingInfo>
|
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</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+399
@@ -0,0 +1,399 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_up_common #(
|
||||
parameter PCORE_VERSION = 0,
|
||||
parameter PCORE_MAGIC = 0,
|
||||
parameter ID = 0,
|
||||
parameter NUM_LANES = 1,
|
||||
parameter NUM_LINKS = 1,
|
||||
parameter DATA_PATH_WIDTH_LOG2 = 2,
|
||||
parameter NUM_IRQS = 1,
|
||||
parameter EXTRA_CFG_WIDTH = 1,
|
||||
parameter DEV_EXTRA_CFG_WIDTH = 1,
|
||||
parameter ENABLE_LINK_STATS = 0
|
||||
) (
|
||||
input up_clk,
|
||||
input ext_resetn,
|
||||
|
||||
output up_reset,
|
||||
|
||||
output up_reset_synchronizer,
|
||||
|
||||
input core_clk,
|
||||
input core_reset_ext,
|
||||
output core_reset,
|
||||
|
||||
input device_clk,
|
||||
output device_reset,
|
||||
|
||||
input [11:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
|
||||
input up_wreq,
|
||||
input [11:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
|
||||
input [EXTRA_CFG_WIDTH-1:0] up_extra_cfg,
|
||||
input [DEV_EXTRA_CFG_WIDTH-1:0] up_dev_extra_cfg,
|
||||
|
||||
input [NUM_IRQS-1:0] up_irq_trigger,
|
||||
output reg irq,
|
||||
|
||||
output up_cfg_is_writeable,
|
||||
|
||||
output reg [NUM_LANES-1:0] core_cfg_lanes_disable = {NUM_LANES{1'b0}},
|
||||
output reg [NUM_LINKS-1:0] core_cfg_links_disable = {NUM_LINKS{1'b0}},
|
||||
output reg [9:0] core_cfg_octets_per_multiframe = 'h00,
|
||||
output reg [7:0] core_cfg_octets_per_frame = 'h00,
|
||||
output reg core_cfg_disable_scrambler = 'h00,
|
||||
output reg core_cfg_disable_char_replacement = 'h00,
|
||||
output reg [EXTRA_CFG_WIDTH-1:0] core_extra_cfg = 'h00,
|
||||
|
||||
output reg [DEV_EXTRA_CFG_WIDTH-1:0] device_extra_cfg = 'h00,
|
||||
|
||||
output reg [9:0] device_cfg_octets_per_multiframe = 'h00,
|
||||
output reg [7:0] device_cfg_octets_per_frame = 'h00,
|
||||
output reg [7:0] device_cfg_beats_per_multiframe = 'h00,
|
||||
|
||||
input [31:0] status_synth_params0,
|
||||
input [31:0] status_synth_params1,
|
||||
input [31:0] status_synth_params2
|
||||
);
|
||||
|
||||
reg [31:0] up_scratch = 32'h00000000;
|
||||
|
||||
reg [7:0] up_cfg_octets_per_frame = 'h00;
|
||||
reg [9:0] up_cfg_octets_per_multiframe = {DATA_PATH_WIDTH_LOG2{1'b1}};
|
||||
reg [7:0] up_cfg_beats_per_multiframe = 'h00;
|
||||
reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}};
|
||||
reg [NUM_LINKS-1:0] up_cfg_links_disable = {NUM_LINKS{1'b0}};
|
||||
reg up_cfg_disable_char_replacement = 1'b0;
|
||||
reg up_cfg_disable_scrambler = 1'b0;
|
||||
|
||||
/* Reset for the register map */
|
||||
reg [2:0] up_reset_vector = 3'b111;
|
||||
assign up_reset = up_reset_vector[0];
|
||||
|
||||
/* Reset signal generation for the JESD core */
|
||||
reg [4:0] core_reset_vector = 5'b11111;
|
||||
assign core_reset = core_reset_vector[0];
|
||||
|
||||
reg [4:0] device_reset_vector = 5'b11111;
|
||||
assign device_reset = device_reset_vector[0];
|
||||
|
||||
/* Transfer the reset signal back to the up domain, used to keep the
|
||||
* synchronizers in reset until the core is ready. This is done in order to
|
||||
* prevent bogus data to propagate to the register map. */
|
||||
reg [1:0] up_reset_synchronizer_vector = 2'b11;
|
||||
assign up_reset_synchronizer = up_reset_synchronizer_vector[0];
|
||||
|
||||
/*
|
||||
* Synchronize the external core reset to the register map domain so the status
|
||||
* can be shown in the register map. This is useful for debugging.
|
||||
*/
|
||||
reg [1:0] up_core_reset_ext_synchronizer_vector = 2'b11;
|
||||
wire up_core_reset_ext;
|
||||
|
||||
assign up_core_reset_ext = up_core_reset_ext_synchronizer_vector[0];
|
||||
|
||||
/* Transfer two cycles before the core comes out of reset */
|
||||
wire core_cfg_transfer_en;
|
||||
assign core_cfg_transfer_en = core_reset_vector[2] ^ core_reset_vector[1];
|
||||
|
||||
wire device_cfg_transfer_en;
|
||||
assign device_cfg_transfer_en = device_reset_vector[2] ^ device_reset_vector[1];
|
||||
|
||||
reg up_reset_core = 1'b1;
|
||||
|
||||
assign up_cfg_is_writeable = up_reset_core;
|
||||
|
||||
always @(posedge up_clk or negedge ext_resetn) begin
|
||||
if (ext_resetn == 1'b0) begin
|
||||
up_reset_vector <= 3'b111;
|
||||
end else begin
|
||||
up_reset_vector <= {1'b0,up_reset_vector[2:1]};
|
||||
end
|
||||
end
|
||||
|
||||
wire core_reset_all = up_reset_core | core_reset_ext;
|
||||
|
||||
always @(posedge core_clk or posedge core_reset_all) begin
|
||||
if (core_reset_all == 1'b1) begin
|
||||
core_reset_vector <= 5'b11111;
|
||||
end else begin
|
||||
core_reset_vector <= {1'b0,core_reset_vector[4:1]};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge device_clk or posedge core_reset_all) begin
|
||||
if (core_reset_all == 1'b1) begin
|
||||
device_reset_vector <= 5'b11111;
|
||||
end else begin
|
||||
device_reset_vector <= {1'b0,device_reset_vector[4:1]};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge up_clk or posedge core_reset) begin
|
||||
if (core_reset == 1'b1) begin
|
||||
up_reset_synchronizer_vector <= 2'b11;
|
||||
end else begin
|
||||
up_reset_synchronizer_vector <= {1'b0,up_reset_synchronizer_vector[1]};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge up_clk or posedge core_reset_ext) begin
|
||||
if (core_reset_ext == 1'b1) begin
|
||||
up_core_reset_ext_synchronizer_vector <= 2'b11;
|
||||
end else begin
|
||||
up_core_reset_ext_synchronizer_vector <= {1'b0,up_core_reset_ext_synchronizer_vector[1]};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge core_clk) begin
|
||||
if (core_cfg_transfer_en == 1'b1) begin
|
||||
core_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe;
|
||||
core_cfg_octets_per_frame <= up_cfg_octets_per_frame;
|
||||
core_cfg_lanes_disable <= up_cfg_lanes_disable;
|
||||
core_cfg_links_disable <= up_cfg_links_disable;
|
||||
core_cfg_disable_scrambler <= up_cfg_disable_scrambler;
|
||||
core_cfg_disable_char_replacement <= up_cfg_disable_char_replacement;
|
||||
core_extra_cfg <= up_extra_cfg;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge device_clk) begin
|
||||
if (device_cfg_transfer_en == 1'b1) begin
|
||||
device_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe;
|
||||
device_cfg_octets_per_frame <= up_cfg_octets_per_frame;
|
||||
device_cfg_beats_per_multiframe <= up_cfg_beats_per_multiframe;
|
||||
device_extra_cfg <= up_dev_extra_cfg;
|
||||
end
|
||||
end
|
||||
|
||||
/* Interupt handling */
|
||||
reg [NUM_IRQS-1:0] up_irq_enable = {NUM_IRQS{1'b0}};
|
||||
reg [NUM_IRQS-1:0] up_irq_source = 'h00;
|
||||
reg [NUM_IRQS-1:0] up_irq_clear;
|
||||
wire [NUM_IRQS-1:0] up_irq_pending;
|
||||
|
||||
assign up_irq_pending = up_irq_source & up_irq_enable;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_reset == 1'b1) begin
|
||||
irq <= 1'b0;
|
||||
end else begin
|
||||
irq <= |up_irq_pending;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_reset == 1'b1) begin
|
||||
up_irq_source <= 'h00;
|
||||
end else begin
|
||||
up_irq_source <= (up_irq_source & ~up_irq_clear) | up_irq_trigger;
|
||||
end
|
||||
end
|
||||
|
||||
/* Count link enable */
|
||||
wire [8*16-1:0] up_irq_event_cnt_bus;
|
||||
wire [15:0] up_link_enable_cnt_s;
|
||||
|
||||
genvar i;
|
||||
generate if (ENABLE_LINK_STATS == 1) begin : g_link_stats
|
||||
|
||||
reg [15:0] up_link_enable_cnt = 'h0;
|
||||
reg up_reset_core_d1 = 'b1;
|
||||
|
||||
wire up_stat_clear;
|
||||
|
||||
assign up_stat_clear = (up_waddr == 12'h0b0 && up_wreq && up_wdata[0]);
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
up_reset_core_d1 <= up_reset_core;
|
||||
if (up_stat_clear) begin
|
||||
up_link_enable_cnt <= 'h0;
|
||||
end else begin
|
||||
if (~up_reset_core & up_reset_core_d1) begin
|
||||
up_link_enable_cnt <= up_link_enable_cnt + 16'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_link_enable_cnt_s = up_link_enable_cnt;
|
||||
|
||||
/* Count IRQ events for max 8 interrupt sources */
|
||||
|
||||
for (i = 0; i < NUM_IRQS; i=i+1) begin : irq_cnt
|
||||
|
||||
reg [15:0] up_irq_event_cnt = 'h0;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_stat_clear) begin
|
||||
up_irq_event_cnt <= 'h0;
|
||||
end else if (up_irq_trigger[i]) begin
|
||||
up_irq_event_cnt <= up_irq_event_cnt + 16'd1;
|
||||
end
|
||||
end
|
||||
|
||||
assign up_irq_event_cnt_bus[i*16 +: 16] = up_irq_event_cnt;
|
||||
|
||||
end
|
||||
end else begin : g_no_link_stats
|
||||
assign up_irq_event_cnt_bus = 'h0;
|
||||
assign up_link_enable_cnt_s = 'h0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire [20:0] clk_mon_count;
|
||||
wire [20:0] device_clk_mon_count;
|
||||
|
||||
always @(*) begin
|
||||
case (up_raddr)
|
||||
/* Standard registers */
|
||||
12'h000: up_rdata = PCORE_VERSION;
|
||||
12'h001: up_rdata = ID;
|
||||
12'h002: up_rdata = up_scratch;
|
||||
12'h003: up_rdata = PCORE_MAGIC;
|
||||
|
||||
/* Core configuration */
|
||||
12'h004: up_rdata = status_synth_params0;
|
||||
12'h005: up_rdata = status_synth_params1;
|
||||
12'h006: up_rdata = status_synth_params2;
|
||||
/* 0x07-0x0f reserved for future use */
|
||||
/* 0x10-0x1f reserved for core specific HDL configuration information */
|
||||
|
||||
/* IRQ block */
|
||||
12'h020: up_rdata = up_irq_enable;
|
||||
12'h021: up_rdata = up_irq_pending;
|
||||
12'h022: up_rdata = up_irq_source;
|
||||
/* 0x23-0x30 reserved for future use */
|
||||
|
||||
/* JESD common control */
|
||||
12'h030: up_rdata = up_reset_core;
|
||||
12'h031: up_rdata = {up_core_reset_ext, up_reset_synchronizer}; /* core ready */
|
||||
12'h032: up_rdata = {11'h00, clk_mon_count}; /* Make it 16.16 */
|
||||
12'h033: up_rdata = {11'h00, device_clk_mon_count}; /* Make it 16.16 */
|
||||
/* 0x34-0x34 reserver for future use */
|
||||
|
||||
12'h080: up_rdata = up_cfg_lanes_disable;
|
||||
/* 0x82-0x83 reserved for future lane disable bits (max 128 lanes) */
|
||||
12'h084: up_rdata = {
|
||||
/* 24-31 */ 8'h00, /* Reserved for future extensions of octets_per_frame */
|
||||
/* 16-23 */ up_cfg_octets_per_frame,
|
||||
/* 10-15 */ 6'b000000, /* Reserved for future extensions of beats_per_multiframe */
|
||||
/* 00-09 */ up_cfg_octets_per_multiframe
|
||||
};
|
||||
12'h85: up_rdata = {
|
||||
/* 02-31 */ 30'h00, /* Reserved for future additions */
|
||||
/* 01 */ up_cfg_disable_char_replacement, /* Disable character replacement */
|
||||
/* 00 */ up_cfg_disable_scrambler /* Disable scrambler */
|
||||
};
|
||||
12'h086: up_rdata = up_cfg_links_disable;
|
||||
12'h087: up_rdata = up_cfg_beats_per_multiframe;
|
||||
/* 0x88-0x8f reserved for future use */
|
||||
|
||||
/* 0x90-0x9f reserved for core specific configuration options */
|
||||
|
||||
/* 0xb0 Stat control */
|
||||
12'h0b1: up_rdata = up_link_enable_cnt_s;
|
||||
/* 0xb4-0xb7 IRQ Stat, max 8 interrupt sources */
|
||||
12'h0b4: up_rdata = up_irq_event_cnt_bus[0*32 +: 32];
|
||||
12'h0b5: up_rdata = up_irq_event_cnt_bus[1*32 +: 32];
|
||||
12'h0b6: up_rdata = up_irq_event_cnt_bus[2*32 +: 32];
|
||||
12'h0b7: up_rdata = up_irq_event_cnt_bus[3*32 +: 32];
|
||||
|
||||
default: up_rdata = 'h00;
|
||||
endcase
|
||||
end
|
||||
|
||||
/* IRQ pending register is write-1-to-clear */
|
||||
always @(*) begin
|
||||
if (up_wreq == 1'b1 && up_waddr == 12'h21) begin
|
||||
up_irq_clear = up_wdata[NUM_IRQS-1:0];
|
||||
end else begin
|
||||
up_irq_clear = {NUM_IRQS{1'b0}};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_reset == 1'b1) begin
|
||||
up_scratch <= 'h00;
|
||||
up_irq_enable <= {NUM_IRQS{1'b0}};
|
||||
up_reset_core <= 1'b1;
|
||||
|
||||
up_cfg_octets_per_frame <= 'h00;
|
||||
up_cfg_octets_per_multiframe <= {DATA_PATH_WIDTH_LOG2{1'b1}};
|
||||
up_cfg_lanes_disable <= {NUM_LANES{1'b0}};
|
||||
up_cfg_links_disable <= {NUM_LINKS{1'b0}};
|
||||
up_cfg_beats_per_multiframe <= 'h00;
|
||||
|
||||
up_cfg_disable_char_replacement <= 1'b0;
|
||||
up_cfg_disable_scrambler <= 1'b0;
|
||||
end else if (up_wreq == 1'b1) begin
|
||||
case (up_waddr)
|
||||
/* Standard registers */
|
||||
12'h002: up_scratch <= up_wdata;
|
||||
|
||||
/* IRQ block */
|
||||
12'h020: up_irq_enable <= up_wdata[NUM_IRQS-1:0];
|
||||
|
||||
/* JESD common control */
|
||||
12'h030: up_reset_core <= up_wdata[0];
|
||||
endcase
|
||||
|
||||
/*
|
||||
* The configuration needs to be static while the core is
|
||||
* active. To enforce this writes to configuration registers
|
||||
* will be ignored while the core is out of reset.
|
||||
*/
|
||||
if (up_cfg_is_writeable == 1'b1) begin
|
||||
case (up_waddr)
|
||||
12'h080: begin
|
||||
up_cfg_lanes_disable <= up_wdata[NUM_LANES-1:0];
|
||||
end
|
||||
12'h084: begin
|
||||
up_cfg_octets_per_frame <= up_wdata[23:16];
|
||||
up_cfg_octets_per_multiframe <= {up_wdata[9:DATA_PATH_WIDTH_LOG2],
|
||||
{DATA_PATH_WIDTH_LOG2{1'b1}}};
|
||||
end
|
||||
12'h085: begin
|
||||
up_cfg_disable_char_replacement <= up_wdata[1];
|
||||
up_cfg_disable_scrambler <= up_wdata[0];
|
||||
end
|
||||
12'h086: begin
|
||||
up_cfg_links_disable <= up_wdata[NUM_LINKS-1:0];
|
||||
end
|
||||
12'h087: begin
|
||||
up_cfg_beats_per_multiframe <= up_wdata[7:0];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
up_clock_mon #(
|
||||
.TOTAL_WIDTH(21)
|
||||
) i_clock_mon (
|
||||
.up_rstn(~up_reset),
|
||||
.up_clk(up_clk),
|
||||
.up_d_count(clk_mon_count),
|
||||
.d_rst(1'b0),
|
||||
.d_clk(core_clk));
|
||||
|
||||
up_clock_mon #(
|
||||
.TOTAL_WIDTH(21)
|
||||
) i_dev_clock_mon (
|
||||
.up_rstn(~up_reset),
|
||||
.up_clk(up_clk),
|
||||
.up_d_count(device_clk_mon_count),
|
||||
.d_rst(1'b0),
|
||||
.d_clk(device_clk));
|
||||
|
||||
endmodule
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_up_sysref (
|
||||
input up_clk,
|
||||
input up_reset,
|
||||
|
||||
input core_clk,
|
||||
|
||||
input device_clk,
|
||||
|
||||
input [11:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
|
||||
input up_wreq,
|
||||
input [11:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
|
||||
input up_cfg_is_writeable,
|
||||
|
||||
output reg up_cfg_sysref_oneshot,
|
||||
output reg [7:0] up_cfg_lmfc_offset,
|
||||
output reg up_cfg_sysref_disable,
|
||||
|
||||
input device_event_sysref_alignment_error,
|
||||
input device_event_sysref_edge
|
||||
);
|
||||
|
||||
reg [1:0] up_sysref_status;
|
||||
reg [1:0] up_sysref_status_clear;
|
||||
wire [1:0] up_sysref_event;
|
||||
|
||||
sync_event #(
|
||||
.NUM_OF_EVENTS(2)
|
||||
) i_cdc_sysref_event (
|
||||
.in_clk(device_clk),
|
||||
.in_event({
|
||||
device_event_sysref_alignment_error,
|
||||
device_event_sysref_edge
|
||||
}),
|
||||
.out_clk(up_clk),
|
||||
.out_event(up_sysref_event));
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_reset == 1'b1) begin
|
||||
up_sysref_status <= 2'b00;
|
||||
end else begin
|
||||
up_sysref_status <= (up_sysref_status & ~up_sysref_status_clear) | up_sysref_event;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case (up_raddr)
|
||||
/* JESD SYSREF configuraton */
|
||||
12'h040: up_rdata = {
|
||||
/* 02-31 */ 30'h00, /* Reserved for future use */
|
||||
/* 01 */ up_cfg_sysref_oneshot,
|
||||
/* 00 */ up_cfg_sysref_disable
|
||||
};
|
||||
12'h041: up_rdata = {
|
||||
/* 10-31 */ 22'h00, /* Reserved for future use */
|
||||
/* 02-09 */ up_cfg_lmfc_offset,
|
||||
/* 00-01 */ 2'b00 /* data path alignment for cfg_lmfc_offset */
|
||||
};
|
||||
12'h042: up_rdata = {
|
||||
/* 02-31 */ 30'h00,
|
||||
/* 00-01 */ up_sysref_status
|
||||
};
|
||||
default: up_rdata = 32'h00000000;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_reset == 1'b1) begin
|
||||
up_cfg_sysref_oneshot <= 1'b0;
|
||||
up_cfg_lmfc_offset <= 'h00;
|
||||
up_cfg_sysref_disable <= 1'b0;
|
||||
end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
|
||||
case (up_waddr)
|
||||
/* JESD SYSREF configuraton */
|
||||
12'h040: begin
|
||||
up_cfg_sysref_oneshot <= up_wdata[1];
|
||||
up_cfg_sysref_disable <= up_wdata[0];
|
||||
end
|
||||
12'h041: begin
|
||||
/* Must be aligned to data path width */
|
||||
up_cfg_lmfc_offset <= up_wdata;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if (up_wreq == 1'b1 && up_waddr == 12'h042) begin
|
||||
up_sysref_status_clear = up_wdata[1:0];
|
||||
end else begin
|
||||
up_sysref_status_clear = 2'b00;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user