initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := jesd204_common
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GENERIC_DEPS += jesd204_crc12.v
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GENERIC_DEPS += jesd204_eof_generator.v
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GENERIC_DEPS += jesd204_frame_align_replace.v
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GENERIC_DEPS += jesd204_frame_mark.v
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GENERIC_DEPS += jesd204_lmfc.v
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GENERIC_DEPS += jesd204_scrambler.v
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GENERIC_DEPS += jesd204_scrambler_64b.v
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GENERIC_DEPS += pipeline_stage.v
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XILINX_DEPS += jesd204_common_ip.tcl
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include ../../scripts/library.mk
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@@ -0,0 +1,266 @@
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@@ -0,0 +1,449 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/jesd204_lmfc.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_scrambler.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_scrambler_64b.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_crc12.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_eof_generator.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_frame_mark.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_frame_align_replace.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/pipeline_stage.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,30 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create jesd204_common
|
||||
|
||||
add_files -fileset [get_filesets sources_1] [list \
|
||||
"jesd204_lmfc.v" \
|
||||
"jesd204_scrambler.v" \
|
||||
"jesd204_scrambler_64b.v" \
|
||||
"jesd204_crc12.v" \
|
||||
"jesd204_eof_generator.v" \
|
||||
"jesd204_frame_mark.v" \
|
||||
"jesd204_frame_align_replace.v" \
|
||||
"pipeline_stage.v" \
|
||||
]
|
||||
|
||||
set_property source_mgmt_mode DisplayOnly [current_project]
|
||||
|
||||
adi_ip_properties_lite jesd204_common
|
||||
|
||||
set_property display_name "ADI JESD204C Common Library" [ipx::current_core]
|
||||
set_property description "ADI JESD204C Common Library" [ipx::current_core]
|
||||
set_property hide_in_gui {1} [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,51 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_crc12 #(
|
||||
parameter WIDTH = 64
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input init,
|
||||
|
||||
input [WIDTH-1:0] data_in,
|
||||
output [11:0] crc12
|
||||
);
|
||||
|
||||
reg [11:0] state = 12'b0;
|
||||
|
||||
wire [WIDTH-1:0] feedback;
|
||||
wire [WIDTH-1+12:0] full_state;
|
||||
|
||||
assign full_state = {init ? 12'h0 : state, feedback};
|
||||
assign feedback = full_state[WIDTH-1+12:12] ^
|
||||
full_state[WIDTH-1:11] ^
|
||||
full_state[WIDTH-1:10] ^
|
||||
full_state[WIDTH-1:9] ^
|
||||
full_state[WIDTH-1:4] ^
|
||||
full_state[WIDTH-1:3] ^
|
||||
data_in;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
state <= 12'b0;
|
||||
end else begin
|
||||
state <= full_state[11:0] ^
|
||||
{full_state[10:0],1'b0} ^
|
||||
{full_state[9:0],2'b0} ^
|
||||
{full_state[8:0],3'b0} ^
|
||||
{full_state[3:0],8'b0} ^
|
||||
{full_state[2:0],9'b0};
|
||||
end
|
||||
end
|
||||
|
||||
assign crc12 = state;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,117 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_eof_generator #(
|
||||
parameter DATA_PATH_WIDTH = 4,
|
||||
parameter MAX_OCTETS_PER_FRAME = 256
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input lmfc_edge,
|
||||
|
||||
input [7:0] cfg_octets_per_frame,
|
||||
input cfg_generate_eomf,
|
||||
|
||||
output reg [DATA_PATH_WIDTH-1:0] sof,
|
||||
output reg [DATA_PATH_WIDTH-1:0] eof,
|
||||
output reg eomf
|
||||
);
|
||||
|
||||
localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 :
|
||||
MAX_OCTETS_PER_FRAME > 64 ? 7 :
|
||||
MAX_OCTETS_PER_FRAME > 32 ? 6 :
|
||||
MAX_OCTETS_PER_FRAME > 16 ? 5 :
|
||||
MAX_OCTETS_PER_FRAME > 8 ? 4 :
|
||||
MAX_OCTETS_PER_FRAME > 4 ? 3 :
|
||||
MAX_OCTETS_PER_FRAME > 2 ? 2 : 1;
|
||||
localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 :
|
||||
DATA_PATH_WIDTH == 4 ? 2 : 1;
|
||||
|
||||
reg lmfc_edge_d1 = 1'b0;
|
||||
|
||||
wire beat_counter_sof;
|
||||
wire beat_counter_eof;
|
||||
wire small_octets_per_frame;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cfg_generate_eomf == 1'b1) begin
|
||||
lmfc_edge_d1 <= lmfc_edge;
|
||||
end else begin
|
||||
lmfc_edge_d1 <= 1'b0;
|
||||
end
|
||||
eomf <= lmfc_edge_d1;
|
||||
end
|
||||
|
||||
generate
|
||||
if (CW > DPW_LOG2) begin
|
||||
reg [CW-DPW_LOG2-1:0] beat_counter = 'h00;
|
||||
wire [CW-DPW_LOG2-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2];
|
||||
|
||||
assign beat_counter_sof = beat_counter == 'h00;
|
||||
assign beat_counter_eof = beat_counter == cfg_beats_per_frame;
|
||||
assign small_octets_per_frame = cfg_beats_per_frame == 'h00;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
beat_counter <= 'h00;
|
||||
end else if (beat_counter_eof == 1'b1) begin
|
||||
beat_counter <= 'h00;
|
||||
end else begin
|
||||
beat_counter <= beat_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
assign beat_counter_sof = 1'b1;
|
||||
assign beat_counter_eof = 1'b1;
|
||||
assign small_octets_per_frame = 1'b1;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
function [1:0] ffs;
|
||||
input [2:0] x;
|
||||
begin
|
||||
case (x)
|
||||
1: ffs = 0;
|
||||
2: ffs = 1;
|
||||
3: ffs = 0;
|
||||
4: ffs = 2;
|
||||
5: ffs = 0;
|
||||
6: ffs = 1;
|
||||
7: ffs = 0;
|
||||
default: ffs = 0;
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
integer i;
|
||||
|
||||
/* Only 1, 2 and multiples of 4 are supported atm */
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
sof <= {DATA_PATH_WIDTH{1'b0}};
|
||||
eof <= {DATA_PATH_WIDTH{1'b0}};
|
||||
end else begin
|
||||
sof <= {{DATA_PATH_WIDTH-1{1'b0}},beat_counter_sof};
|
||||
eof <= {beat_counter_eof,{DATA_PATH_WIDTH-1{1'b0}}};
|
||||
|
||||
if (small_octets_per_frame == 1'b1) begin
|
||||
for (i = 1; i < DATA_PATH_WIDTH; i = i + 1) begin
|
||||
if (cfg_octets_per_frame[ffs(i)] != 1'b1) begin
|
||||
sof[i] <= 1'b1;
|
||||
eof[DATA_PATH_WIDTH-1-i] <= 1'b1;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,209 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
// Limitations:
|
||||
// DATA_PATH_WIDTH = 4, 8
|
||||
// F=1,2,3,4,6, and multiples of DATA_PATH_WIDTH
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_frame_align_replace #(
|
||||
parameter DATA_PATH_WIDTH = 4,
|
||||
parameter IS_RX = 1'b1,
|
||||
parameter ENABLED = 1'b1
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input [7:0] cfg_octets_per_frame,
|
||||
input cfg_disable_char_replacement,
|
||||
input cfg_disable_scrambler,
|
||||
|
||||
input [DATA_PATH_WIDTH*8-1:0] data,
|
||||
input [DATA_PATH_WIDTH-1:0] eof,
|
||||
input [DATA_PATH_WIDTH-1:0] rx_char_is_a,
|
||||
input [DATA_PATH_WIDTH-1:0] rx_char_is_f,
|
||||
input [DATA_PATH_WIDTH-1:0] tx_eomf,
|
||||
|
||||
output [DATA_PATH_WIDTH*8-1:0] data_out,
|
||||
output [DATA_PATH_WIDTH-1:0] charisk_out
|
||||
);
|
||||
|
||||
localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
|
||||
|
||||
wire single_eof = cfg_octets_per_frame >= (DATA_PATH_WIDTH-1);
|
||||
reg [DATA_PATH_WIDTH*8-1:0] data_d1;
|
||||
reg [DATA_PATH_WIDTH*8-1:0] data_d2;
|
||||
wire [DATA_PATH_WIDTH-1:0] char_is_align;
|
||||
reg [DATA_PATH_WIDTH-1:0] char_is_align_d1;
|
||||
reg [DATA_PATH_WIDTH-1:0] char_is_align_d2;
|
||||
wire [((DATA_PATH_WIDTH*2)+4)*8-1:0] saved_data;
|
||||
wire [((DATA_PATH_WIDTH*2)+4)-1:0] saved_char_is_align;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] data_replaced;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] data_prev_eof;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] data_prev_prev_eof;
|
||||
reg [7:0] data_prev_eof_single;
|
||||
reg [7:0] data_prev_eof_single_int;
|
||||
reg char_is_align_prev_single;
|
||||
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_data_1;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_1;
|
||||
wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_1;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_data_2;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_2;
|
||||
wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_2;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_data_3;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_3;
|
||||
wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_3;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_data_4;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_4;
|
||||
wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_4;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_data_6;
|
||||
wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_6;
|
||||
wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_6;
|
||||
reg [DATA_PATH_WIDTH*8-1:0] prev_data;
|
||||
reg [DATA_PATH_WIDTH*8-1:0] prev_prev_data;
|
||||
reg [DATA_PATH_WIDTH-1:0] prev_char_is_align;
|
||||
reg [DPW_LOG2:0] jj;
|
||||
reg [DPW_LOG2:0] ll;
|
||||
|
||||
always @(posedge clk) begin
|
||||
data_d1 <= data;
|
||||
data_d2 <= data_d1;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(reset) begin
|
||||
char_is_align_d1 <= 'b0;
|
||||
char_is_align_d2 <= 'b0;
|
||||
end else begin
|
||||
char_is_align_d1 <= char_is_align;
|
||||
char_is_align_d2 <= char_is_align_d1;
|
||||
end
|
||||
end
|
||||
|
||||
// Capture single EOF in current cycle
|
||||
|
||||
always @(eof, data) begin
|
||||
data_prev_eof_single_int = 'b0;
|
||||
for(ll = 0; ll < DATA_PATH_WIDTH; ll=ll+1) begin
|
||||
data_prev_eof_single_int = data_prev_eof_single_int | (data[ll*8 +: 8] & {8{eof[ll]}});
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(reset) begin
|
||||
data_prev_eof_single <= 'b0;
|
||||
end else begin
|
||||
if(|eof && (!IS_RX || !(|char_is_align))) begin
|
||||
data_prev_eof_single <= data_prev_eof_single_int;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(reset) begin
|
||||
char_is_align_prev_single <= 'b0;
|
||||
end else begin
|
||||
if(|eof) begin
|
||||
char_is_align_prev_single <= |char_is_align;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign saved_data = {data, data_d1, data_d2[(DATA_PATH_WIDTH*8)-1:(DATA_PATH_WIDTH-4)*8]};
|
||||
assign saved_char_is_align = {char_is_align, char_is_align_d1, char_is_align_d2[DATA_PATH_WIDTH-1:DATA_PATH_WIDTH-4]};
|
||||
|
||||
genvar ii;
|
||||
generate
|
||||
for (ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin: gen_replace_byte
|
||||
assign prev_data_1[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+3+ii)*8 +: 8];
|
||||
assign prev_data_2[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+2+ii)*8 +: 8];
|
||||
assign prev_data_3[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+1+ii)*8 +: 8];
|
||||
assign prev_prev_data_1[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+2+ii)*8 +: 8];
|
||||
assign prev_prev_data_2[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+ii)*8 +: 8];
|
||||
assign prev_prev_data_3[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-2+ii)*8 +: 8];
|
||||
assign prev_char_is_align_1[ii] = saved_char_is_align[(DATA_PATH_WIDTH+3+ii)];
|
||||
assign prev_char_is_align_2[ii] = saved_char_is_align[(DATA_PATH_WIDTH+2+ii)];
|
||||
assign prev_char_is_align_3[ii] = saved_char_is_align[(DATA_PATH_WIDTH+1+ii)];
|
||||
|
||||
if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
|
||||
assign prev_data_4[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+ii)*8 +: 8];
|
||||
assign prev_data_6[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-2+ii)*8 +: 8];
|
||||
assign prev_prev_data_4[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-4+ii)*8 +: 8];
|
||||
assign prev_prev_data_6[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-8+ii)*8 +: 8];
|
||||
assign prev_char_is_align_4[ii] = saved_char_is_align[(DATA_PATH_WIDTH+ii)];
|
||||
assign prev_char_is_align_6[ii] = saved_char_is_align[(DATA_PATH_WIDTH-2+ii)];
|
||||
end else begin
|
||||
assign prev_data_4[ii*8 +:8] = 'bX;
|
||||
assign prev_data_6[ii*8 +:8] = 'bX;
|
||||
assign prev_prev_data_4[ii*8 +:8] = 'bX;
|
||||
assign prev_prev_data_6[ii*8 +:8] = 'bX;
|
||||
assign prev_char_is_align_4[ii] = 'bX;
|
||||
assign prev_char_is_align_6[ii] = 'bX;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case(cfg_octets_per_frame)
|
||||
0:
|
||||
begin
|
||||
prev_data[ii*8 +:8] = prev_data_1[ii*8 +:8];
|
||||
prev_prev_data[ii*8 +:8] = prev_prev_data_1[ii*8 +:8];
|
||||
prev_char_is_align[ii] = prev_char_is_align_1[ii];
|
||||
end
|
||||
1:
|
||||
begin
|
||||
prev_data[ii*8 +:8] = prev_data_2[ii*8 +:8];
|
||||
prev_prev_data[ii*8 +:8] = prev_prev_data_2[ii*8 +:8];
|
||||
prev_char_is_align[ii] = prev_char_is_align_2[ii];
|
||||
end
|
||||
2:
|
||||
begin
|
||||
prev_data[ii*8 +:8] = prev_data_3[ii*8 +:8];
|
||||
prev_prev_data[ii*8 +:8] = prev_prev_data_3[ii*8 +:8];
|
||||
prev_char_is_align[ii] = prev_char_is_align_3[ii];
|
||||
end
|
||||
3:
|
||||
begin
|
||||
prev_data[ii*8 +:8] = prev_data_4[ii*8 +:8];
|
||||
prev_prev_data[ii*8 +:8] = prev_prev_data_4[ii*8 +:8];
|
||||
prev_char_is_align[ii] = prev_char_is_align_4[ii];
|
||||
end
|
||||
5:
|
||||
begin
|
||||
prev_data[ii*8 +:8] = prev_data_6[ii*8 +:8];
|
||||
prev_prev_data[ii*8 +:8] = prev_prev_data_6[ii*8 +:8];
|
||||
prev_char_is_align[ii] = prev_char_is_align_6[ii];
|
||||
end
|
||||
default:
|
||||
begin
|
||||
prev_data[ii*8 +:8] = 'bX;
|
||||
prev_prev_data[ii*8 +:8] = 'bX;
|
||||
prev_char_is_align[ii] = 1'bX;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
if(IS_RX) begin : gen_rx
|
||||
// RX
|
||||
assign char_is_align[ii] = !reset && (rx_char_is_a[ii] | rx_char_is_f[ii]);
|
||||
assign data_replaced[ii*8 +: 8] = char_is_align[ii] ? data_prev_eof[ii*8 +: 8] : data[ii*8 +: 8];
|
||||
assign data_prev_eof[ii*8 +: 8] = single_eof ? data_prev_eof_single : prev_char_is_align[ii] ? data_prev_prev_eof[ii*8 +: 8] : prev_data[ii*8 +: 8];
|
||||
assign data_prev_prev_eof[ii*8 +: 8] = prev_prev_data[ii*8 +: 8];
|
||||
end else begin : gen_tx
|
||||
// TX
|
||||
assign data_prev_eof[ii*8 +: 8] = single_eof ? data_prev_eof_single : prev_data[ii*8 +: 8];
|
||||
assign char_is_align[ii] = !reset && (tx_eomf[ii] || (eof[ii] && !(single_eof ? char_is_align_prev_single : prev_char_is_align[ii]))) && (data[ii*8 +: 8] == data_prev_eof[ii*8 +: 8]);
|
||||
assign data_replaced[ii*8 +: 8] = char_is_align[ii] ? (tx_eomf[ii] ? 8'h7c : 8'hfc) : data[ii*8 +: 8];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign data_out = (cfg_disable_char_replacement || !cfg_disable_scrambler || ENABLED==0) ? data : data_replaced;
|
||||
assign charisk_out = (IS_RX || !cfg_disable_scrambler || cfg_disable_char_replacement || ENABLED==0) ? 'b0 : char_is_align;
|
||||
|
||||
endmodule
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
// Limitations:
|
||||
// for DATA_PATH_WIDTH = 4, 8
|
||||
// F*K=4, multiples of DATA_PATH_WIDTH
|
||||
// F=1,2,3,4,6, and multiples of DATA_PATH_WIDTH
|
||||
// for DATA_PATH_WIDTH = 6
|
||||
// F=3,6
|
||||
// for DATA_PATH_WIDTH = 12
|
||||
// F=3,6,12
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_frame_mark #(
|
||||
parameter DATA_PATH_WIDTH = 4
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
input [9:0] cfg_octets_per_multiframe,
|
||||
input [7:0] cfg_beats_per_multiframe,
|
||||
input [7:0] cfg_octets_per_frame,
|
||||
|
||||
output reg [DATA_PATH_WIDTH-1:0] sof,
|
||||
output reg [DATA_PATH_WIDTH-1:0] eof,
|
||||
output reg [DATA_PATH_WIDTH-1:0] somf,
|
||||
output reg [DATA_PATH_WIDTH-1:0] eomf
|
||||
);
|
||||
|
||||
localparam MAX_OCTETS_PER_FRAME = 32;
|
||||
localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
|
||||
localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 :
|
||||
MAX_OCTETS_PER_FRAME > 64 ? 7 :
|
||||
MAX_OCTETS_PER_FRAME > 32 ? 6 :
|
||||
MAX_OCTETS_PER_FRAME > 16 ? 5 :
|
||||
MAX_OCTETS_PER_FRAME > 8 ? 4 :
|
||||
MAX_OCTETS_PER_FRAME > 4 ? 3 :
|
||||
MAX_OCTETS_PER_FRAME > 2 ? 2 : 1;
|
||||
localparam BEATS_PER_FRAME_WIDTH = CW-DPW_LOG2;
|
||||
localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2;
|
||||
|
||||
// For DATA_PATH_WIDTH = 8, special case if F*K%8=4
|
||||
wire octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2];
|
||||
reg [BEATS_PER_MF_WIDTH-1:0] cur_beats_per_multiframe;
|
||||
reg mf_phase;
|
||||
reg [1:0] beat_cnt_mod_3;
|
||||
reg [BEATS_PER_FRAME_WIDTH-1:0] beat_cnt_frame;
|
||||
wire cur_sof;
|
||||
wire cur_eof;
|
||||
reg [BEATS_PER_MF_WIDTH-1:0] beat_cnt_mf;
|
||||
wire cur_somf;
|
||||
wire cur_eomf;
|
||||
wire [DATA_PATH_WIDTH-1:0] default_sof;
|
||||
wire [DATA_PATH_WIDTH-1:0] default_eof;
|
||||
|
||||
wire [BEATS_PER_FRAME_WIDTH-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2];
|
||||
reg [DATA_PATH_WIDTH-1:0] sof_f_3[2:0];
|
||||
reg [DATA_PATH_WIDTH-1:0] eof_f_3[2:0];
|
||||
reg [DATA_PATH_WIDTH-1:0] sof_f_6[2:0];
|
||||
reg [DATA_PATH_WIDTH-1:0] eof_f_6[2:0];
|
||||
reg [DATA_PATH_WIDTH-1:0] sof_f_12[2:0];
|
||||
reg [DATA_PATH_WIDTH-1:0] eof_f_12[2:0];
|
||||
|
||||
generate
|
||||
if(DATA_PATH_WIDTH == 4) begin : gen_dp_4
|
||||
initial begin
|
||||
sof_f_3[0] = {4'b1001};
|
||||
sof_f_3[1] = {4'b0100};
|
||||
sof_f_3[2] = {4'b0010};
|
||||
eof_f_3[0] = {4'b0100};
|
||||
eof_f_3[1] = {4'b0010};
|
||||
eof_f_3[2] = {4'b1001};
|
||||
sof_f_6[0] = {4'b0001};
|
||||
sof_f_6[1] = {4'b0100};
|
||||
sof_f_6[2] = {4'b0000};
|
||||
eof_f_6[0] = {4'b0000};
|
||||
eof_f_6[1] = {4'b0010};
|
||||
eof_f_6[2] = {4'b1000};
|
||||
end
|
||||
end else if(DATA_PATH_WIDTH == 6) begin : gen_dp_6
|
||||
initial begin
|
||||
sof_f_3[0] = {6'b001001};
|
||||
sof_f_3[1] = {6'b001001};
|
||||
sof_f_3[2] = {6'b001001};
|
||||
eof_f_3[0] = {6'b100100};
|
||||
eof_f_3[1] = {6'b100100};
|
||||
eof_f_3[2] = {6'b100100};
|
||||
sof_f_6[0] = {6'b000001};
|
||||
sof_f_6[1] = {6'b000001};
|
||||
sof_f_6[2] = {6'b000001};
|
||||
eof_f_6[0] = {6'b100000};
|
||||
eof_f_6[1] = {6'b100000};
|
||||
eof_f_6[2] = {6'b100000};
|
||||
end
|
||||
end else if(DATA_PATH_WIDTH == 8) begin : gen_dp_8
|
||||
initial begin
|
||||
sof_f_3[0] = {8'b01001001};
|
||||
sof_f_3[1] = {8'b10010010};
|
||||
sof_f_3[2] = {8'b00100100};
|
||||
eof_f_3[0] = {8'b00100100};
|
||||
eof_f_3[1] = {8'b01001001};
|
||||
eof_f_3[2] = {8'b10010010};
|
||||
sof_f_6[0] = {8'b01000001};
|
||||
sof_f_6[1] = {8'b00010000};
|
||||
sof_f_6[2] = {8'b00000100};
|
||||
eof_f_6[0] = {8'b00100000};
|
||||
eof_f_6[1] = {8'b00001000};
|
||||
eof_f_6[2] = {8'b10000010};
|
||||
sof_f_12[0] = {8'b00000001};
|
||||
sof_f_12[1] = {8'b00010000};
|
||||
sof_f_12[2] = {8'b00000000};
|
||||
eof_f_12[0] = {8'b00000000};
|
||||
eof_f_12[1] = {8'b00001000};
|
||||
eof_f_12[2] = {8'b10000000};
|
||||
end
|
||||
end
|
||||
// Beat count % 3, to support F=3, 6, 12
|
||||
always @(posedge clk) begin
|
||||
if(reset) begin
|
||||
beat_cnt_mod_3 <= 2'd0;
|
||||
end else begin
|
||||
if(beat_cnt_mod_3 == 2'd2) begin
|
||||
beat_cnt_mod_3 <= 2'd0;
|
||||
end else begin
|
||||
beat_cnt_mod_3 <= beat_cnt_mod_3 + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Beat count per frame
|
||||
always @(posedge clk) begin
|
||||
if(reset) begin
|
||||
beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}};
|
||||
end else begin
|
||||
if(beat_cnt_frame == cfg_beats_per_frame) begin
|
||||
beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}};
|
||||
end else begin
|
||||
beat_cnt_frame <= beat_cnt_frame + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cur_sof = beat_cnt_frame == 0;
|
||||
assign cur_eof = beat_cnt_frame == cfg_beats_per_frame;
|
||||
|
||||
assign default_sof = {{DATA_PATH_WIDTH-1{1'b0}}, cur_sof};
|
||||
assign default_eof = {cur_eof, {DATA_PATH_WIDTH-1{1'b0}}};
|
||||
|
||||
// cfg_octets_per_frame must be a multiple of DATA_PATH_WIDTH
|
||||
// except for the following supported special cases
|
||||
always @(*) begin
|
||||
case(cfg_octets_per_frame)
|
||||
8'd0:
|
||||
begin
|
||||
sof = {DATA_PATH_WIDTH{1'b1}};
|
||||
eof = {DATA_PATH_WIDTH{1'b1}};
|
||||
end
|
||||
8'd1:
|
||||
begin
|
||||
sof = {DATA_PATH_WIDTH/2{2'b01}};
|
||||
eof = {DATA_PATH_WIDTH/2{2'b10}};
|
||||
end
|
||||
8'd2:
|
||||
begin
|
||||
sof = sof_f_3[beat_cnt_mod_3];
|
||||
eof = eof_f_3[beat_cnt_mod_3];
|
||||
end
|
||||
8'd3:
|
||||
begin
|
||||
sof = {DATA_PATH_WIDTH/4{4'b0001}};
|
||||
eof = {DATA_PATH_WIDTH/4{4'b1000}};
|
||||
end
|
||||
8'd5:
|
||||
begin
|
||||
sof = sof_f_6[beat_cnt_mod_3];
|
||||
eof = eof_f_6[beat_cnt_mod_3];
|
||||
end
|
||||
8'd11:
|
||||
begin
|
||||
sof = (DATA_PATH_WIDTH == 4) ? default_sof : sof_f_12[beat_cnt_mod_3];
|
||||
eof = (DATA_PATH_WIDTH == 4) ? default_eof : eof_f_12[beat_cnt_mod_3];
|
||||
end
|
||||
default:
|
||||
begin
|
||||
sof = default_sof;
|
||||
eof = default_eof;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// Beat count per multiframe
|
||||
// Only support F*K%4=0
|
||||
// If DATA_PATH_WIDTH == 4, or if DATA_PATH_WIDTH == 8 and F*K%8=0,
|
||||
// then multiframes always start/end at the first/last octet in the data bus
|
||||
// Otherwise, start/end of multiframe have more complicated patterns
|
||||
always @(posedge clk) begin
|
||||
if(reset) begin
|
||||
beat_cnt_mf <= 8'b0;
|
||||
mf_phase <= 1'b0;
|
||||
end else begin
|
||||
if(beat_cnt_mf == cur_beats_per_multiframe) begin
|
||||
beat_cnt_mf <= 8'b0;
|
||||
mf_phase <= ~mf_phase;
|
||||
end else begin
|
||||
beat_cnt_mf <= beat_cnt_mf + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cur_somf = beat_cnt_mf == 0;
|
||||
assign cur_eomf = beat_cnt_mf == cur_beats_per_multiframe;
|
||||
|
||||
if(DATA_PATH_WIDTH == 4 || DATA_PATH_WIDTH == 6) begin : gen_mf_dp_4_6
|
||||
always @(*) begin
|
||||
cur_beats_per_multiframe = cfg_beats_per_multiframe;
|
||||
somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf};
|
||||
eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}};
|
||||
end
|
||||
end else if(DATA_PATH_WIDTH == 8) begin : gen_mf_dp_8
|
||||
always @(*) begin
|
||||
// cfg_octets_per_multiframe = 4
|
||||
if(cfg_octets_per_multiframe[9:2] == 0) begin
|
||||
cur_beats_per_multiframe = 8'hXX;
|
||||
somf = 8'h11;
|
||||
eomf = 8'h88;
|
||||
end else if(~octets_per_mf_4_mod_8) begin
|
||||
cur_beats_per_multiframe = cfg_beats_per_multiframe;
|
||||
somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf};
|
||||
eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}};
|
||||
end else begin
|
||||
cur_beats_per_multiframe = cfg_beats_per_multiframe - mf_phase;
|
||||
if((mf_phase == 0) && (beat_cnt_mf == 0)) begin
|
||||
somf = 8'h01;
|
||||
end else if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
|
||||
somf = 8'h10;
|
||||
end else begin
|
||||
somf = 8'b0;
|
||||
end
|
||||
|
||||
if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
|
||||
eomf = 8'h08;
|
||||
end else if((mf_phase == 1) && (beat_cnt_mf == cur_beats_per_multiframe)) begin
|
||||
eomf = 8'h80;
|
||||
end else begin
|
||||
eomf = 8'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
+202
@@ -0,0 +1,202 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_lmfc #(
|
||||
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
|
||||
parameter DATA_PATH_WIDTH = 4
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input sysref,
|
||||
|
||||
input [9:0] cfg_octets_per_multiframe,
|
||||
input [7:0] cfg_beats_per_multiframe,
|
||||
input [7:0] cfg_lmfc_offset,
|
||||
input cfg_sysref_oneshot,
|
||||
input cfg_sysref_disable,
|
||||
|
||||
output reg lmfc_edge,
|
||||
output reg lmfc_clk,
|
||||
output reg [7:0] lmfc_counter,
|
||||
|
||||
// Local MultiBlock clock edge
|
||||
output reg lmc_edge,
|
||||
output reg lmc_quarter_edge,
|
||||
// End of Extended MultiBlock
|
||||
output reg eoemb,
|
||||
|
||||
output reg sysref_edge,
|
||||
output reg sysref_alignment_error
|
||||
);
|
||||
|
||||
localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
|
||||
localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2;
|
||||
|
||||
//wire [BEATS_PER_MF_WIDTH-1:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe[9:DPW_LOG2];
|
||||
reg [BEATS_PER_MF_WIDTH:0] cfg_whole_beats_per_multiframe;
|
||||
|
||||
reg sysref_r = 1'b0;
|
||||
reg sysref_d1 = 1'b0;
|
||||
reg sysref_d2 = 1'b0;
|
||||
reg sysref_d3 = 1'b0;
|
||||
|
||||
reg sysref_captured;
|
||||
|
||||
/* lmfc_octet_counter = lmfc_counter * (char_clock_rate / device_clock_rate) */
|
||||
reg [7:0] lmfc_counter_next = 'h00;
|
||||
|
||||
reg lmfc_clk_p1 = 1'b1;
|
||||
|
||||
reg lmfc_active = 1'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sysref_r <= sysref;
|
||||
end
|
||||
|
||||
/*
|
||||
* Unfortunately setup and hold are often ignored on the sysref signal relative
|
||||
* to the device clock. The device will often still work fine, just not
|
||||
* deterministic. Reduce the probability that the meta-stability creeps into the
|
||||
* reset of the system and causes non-reproducible issues.
|
||||
*/
|
||||
always @(posedge clk) begin
|
||||
sysref_d1 <= sysref_r;
|
||||
sysref_d2 <= sysref_d1;
|
||||
sysref_d3 <= sysref_d2;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sysref_d3 == 1'b0 && sysref_d2 == 1'b1 && cfg_sysref_disable == 1'b0) begin
|
||||
sysref_edge <= 1'b1;
|
||||
end else begin
|
||||
sysref_edge <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
sysref_captured <= 1'b0;
|
||||
end else if (sysref_edge == 1'b1) begin
|
||||
sysref_captured <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* The configuration must be static when the core is out of reset. Otherwise
|
||||
* undefined behaviour might occur.
|
||||
* E.g. lmfc_counter > beats_per_multiframe
|
||||
*
|
||||
* To change the configuration first assert reset, then update the configuration
|
||||
* setting, finally deassert reset.
|
||||
*/
|
||||
|
||||
/*
|
||||
* For DATA_PATH_WIDTH == 8, F*K%8=4, set
|
||||
* cfg_beats_per_multiframe = cfg_beats_per_multiframe*2
|
||||
* LMFC will be twice the actual length
|
||||
*/
|
||||
always @(*) begin
|
||||
if((LINK_MODE == 1) && (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2]) begin
|
||||
cfg_whole_beats_per_multiframe = cfg_beats_per_multiframe*2;
|
||||
end else begin
|
||||
cfg_whole_beats_per_multiframe = cfg_beats_per_multiframe;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if (lmfc_counter == cfg_whole_beats_per_multiframe) begin
|
||||
lmfc_counter_next = 'h00;
|
||||
end else begin
|
||||
lmfc_counter_next = lmfc_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
lmfc_counter <= 'h01;
|
||||
lmfc_active <= cfg_sysref_disable;
|
||||
end else begin
|
||||
/*
|
||||
* In oneshot mode only the first occurence of the
|
||||
* SYSREF signal is used for alignment.
|
||||
*/
|
||||
if (sysref_edge == 1'b1 &&
|
||||
(cfg_sysref_oneshot == 1'b0 || sysref_captured == 1'b0)) begin
|
||||
lmfc_counter <= cfg_lmfc_offset;
|
||||
lmfc_active <= 1'b1;
|
||||
end else begin
|
||||
lmfc_counter <= lmfc_counter_next;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
sysref_alignment_error <= 1'b0;
|
||||
end else begin
|
||||
/*
|
||||
* Alignement error is reported regardless of oneshot mode
|
||||
* setting.
|
||||
*/
|
||||
sysref_alignment_error <= 1'b0;
|
||||
if (sysref_edge == 1'b1 && lmfc_active == 1'b1 &&
|
||||
lmfc_counter_next != cfg_lmfc_offset) begin
|
||||
sysref_alignment_error <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (lmfc_counter == 'h00 && lmfc_active == 1'b1) begin
|
||||
lmfc_edge <= 1'b1;
|
||||
end else begin
|
||||
lmfc_edge <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// 1 MultiBlock = 32 blocks
|
||||
always @(posedge clk) begin
|
||||
if (lmfc_counter[4:0] == 'h00 && lmfc_active == 1'b1) begin
|
||||
lmc_edge <= 1'b1;
|
||||
end else begin
|
||||
lmc_edge <= 1'b0;
|
||||
end
|
||||
end
|
||||
always @(posedge clk) begin
|
||||
if (lmfc_counter[2:0] == 'h00 && lmfc_active == 1'b1) begin
|
||||
lmc_quarter_edge <= 1'b1;
|
||||
end else begin
|
||||
lmc_quarter_edge <= 1'b0;
|
||||
end
|
||||
end
|
||||
// End of Extended MultiBlock
|
||||
always @(posedge clk) begin
|
||||
if (lmfc_active == 1'b1) begin
|
||||
eoemb <= lmfc_counter[7:5] == cfg_whole_beats_per_multiframe[7:5];
|
||||
end else begin
|
||||
eoemb <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
lmfc_clk_p1 <= 1'b0;
|
||||
end else if (lmfc_active == 1'b1) begin
|
||||
if (lmfc_counter == cfg_whole_beats_per_multiframe) begin
|
||||
lmfc_clk_p1 <= 1'b1;
|
||||
end else if (lmfc_counter == cfg_whole_beats_per_multiframe[7:1]) begin
|
||||
lmfc_clk_p1 <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
lmfc_clk <= lmfc_clk_p1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,56 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_scrambler #(
|
||||
parameter WIDTH = 32,
|
||||
parameter DESCRAMBLE = 0
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input enable,
|
||||
|
||||
input [WIDTH-1:0] data_in,
|
||||
output [WIDTH-1:0] data_out
|
||||
);
|
||||
|
||||
reg [14:0] state = 'h7f80;
|
||||
reg [WIDTH-1:0] swizzle_out;
|
||||
wire [WIDTH-1:0] swizzle_in;
|
||||
wire [WIDTH-1:0] feedback;
|
||||
wire [WIDTH-1+15:0] full_state;
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < WIDTH / 8; i = i + 1) begin: gen_swizzle
|
||||
assign swizzle_in[WIDTH-1-i*8:WIDTH-i*8-8] = data_in[i*8+7:i*8];
|
||||
assign data_out[WIDTH-1-i*8:WIDTH-i*8-8] = swizzle_out[i*8+7:i*8];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign full_state = {state,DESCRAMBLE ? swizzle_in : feedback};
|
||||
assign feedback = full_state[WIDTH-1+15:15] ^ full_state[WIDTH-1+14:14] ^ swizzle_in;
|
||||
|
||||
always @(*) begin
|
||||
if (enable == 1'b0) begin
|
||||
swizzle_out = swizzle_in;
|
||||
end else begin
|
||||
swizzle_out = feedback;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
state <= 'h7f80;
|
||||
end else begin
|
||||
state <= full_state[14:0];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,46 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_scrambler_64b #(
|
||||
parameter WIDTH = 64,
|
||||
parameter DESCRAMBLE = 0
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input enable,
|
||||
|
||||
input [WIDTH-1:0] data_in,
|
||||
output reg [WIDTH-1:0] data_out
|
||||
);
|
||||
|
||||
reg [57:0] state = {1'b1,57'b0};
|
||||
wire [WIDTH-1:0] feedback;
|
||||
wire [WIDTH-1+58:0] full_state;
|
||||
|
||||
assign full_state = {state,DESCRAMBLE ? data_in : feedback};
|
||||
assign feedback = full_state[WIDTH-1+58:58] ^ full_state[WIDTH-1:39] ^ data_in;
|
||||
|
||||
always @(*) begin
|
||||
if (enable == 1'b0) begin
|
||||
data_out = data_in;
|
||||
end else begin
|
||||
data_out = feedback;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
state <= {1'b1,57'b0};
|
||||
end else begin
|
||||
state <= full_state[57:0] ^ {full_state[38:0],19'b0};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,27 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module pipeline_stage #(
|
||||
parameter REGISTERED = 1,
|
||||
parameter WIDTH = 1
|
||||
) (
|
||||
input clk,
|
||||
input [WIDTH-1:0] in,
|
||||
output [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
generate if (REGISTERED == 0) begin
|
||||
assign out = in;
|
||||
end else begin
|
||||
(* shreg_extract = "no" *) reg [REGISTERED*WIDTH-1:0] in_dly = {REGISTERED*WIDTH{1'b0}};
|
||||
always @(posedge clk) in_dly <= {in_dly,in};
|
||||
assign out = in_dly[REGISTERED*WIDTH-1 -: WIDTH];
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,97 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module sync_header_align (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input [65:0] i_data,
|
||||
output i_slip,
|
||||
input i_slip_done,
|
||||
|
||||
output [63:0] o_data,
|
||||
output [1:0] o_header,
|
||||
output o_block_sync
|
||||
);
|
||||
|
||||
assign {o_header,o_data} = i_data;
|
||||
|
||||
// TODO : Add alignment FSM
|
||||
localparam STATE_SH_HUNT = 3'b001;
|
||||
localparam STATE_SH_SLIP = 3'b010;
|
||||
localparam STATE_SH_LOCK = 3'b100;
|
||||
|
||||
localparam BIT_SH_HUNT = 0;
|
||||
localparam BIT_SH_SLIP = 1;
|
||||
localparam BIT_SH_LOCK = 2;
|
||||
|
||||
localparam RX_THRESH_SH_ERR = 16;
|
||||
localparam LOG2_RX_THRESH_SH_ERR = $clog2(RX_THRESH_SH_ERR);
|
||||
|
||||
reg [2:0] state = STATE_SH_HUNT;
|
||||
reg [2:0] next_state;
|
||||
|
||||
reg [7:0] header_vcnt = 8'h0;
|
||||
reg [LOG2_RX_THRESH_SH_ERR:0] header_icnt = 'h0;
|
||||
|
||||
wire valid_header;
|
||||
assign valid_header = ^o_header;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset | ~valid_header) begin
|
||||
header_vcnt <= 'b0;
|
||||
end else if (state[BIT_SH_HUNT] & ~header_vcnt[7]) begin
|
||||
header_vcnt <= header_vcnt + 'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset | valid_header) begin
|
||||
header_icnt <= 'b0;
|
||||
end else if (state[BIT_SH_LOCK] & ~header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
|
||||
header_icnt <= header_icnt + 'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
next_state = state;
|
||||
case (state)
|
||||
STATE_SH_HUNT:
|
||||
if (valid_header) begin
|
||||
if (header_vcnt[7]) begin
|
||||
next_state = STATE_SH_LOCK;
|
||||
end
|
||||
end else begin
|
||||
next_state = STATE_SH_SLIP;
|
||||
end
|
||||
STATE_SH_SLIP:
|
||||
if (i_slip_done) begin
|
||||
next_state = STATE_SH_HUNT;
|
||||
end
|
||||
STATE_SH_LOCK:
|
||||
if (~valid_header) begin
|
||||
if (header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
|
||||
next_state = STATE_SH_HUNT;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
state <= STATE_SH_HUNT;
|
||||
end else begin
|
||||
state <= next_state;
|
||||
end
|
||||
end
|
||||
|
||||
assign o_block_sync = state[BIT_SH_LOCK];
|
||||
assign i_slip = state[BIT_SH_SLIP];
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "REGISTERED" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.REGISTERED { PARAM_VALUE.REGISTERED } {
|
||||
# Procedure called to update REGISTERED when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.REGISTERED { PARAM_VALUE.REGISTERED } {
|
||||
# Procedure called to validate REGISTERED
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
|
||||
# Procedure called to update WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
|
||||
# Procedure called to validate WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.REGISTERED { MODELPARAM_VALUE.REGISTERED PARAM_VALUE.REGISTERED } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.REGISTERED}] ${MODELPARAM_VALUE.REGISTERED}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user