initial commit, add dds_par module

2024-01-15 09:36:08 +08:00
commit 315a673005
1374 changed files with 465956 additions and 0 deletions
@@ -0,0 +1,93 @@
+###############################################################################
+## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :>
+<: set async_clk [getBooleanValue "ASYNC_CLK"] :>
+<: set link_mode [getBooleanValue "LINK_MODE"] :>
+
+set_property ASYNC_REG TRUE \
+  [get_cells {i_lmfc/sysref_d1_reg}] \
+  [get_cells {i_lmfc/sysref_d2_reg}]
+
+# Make sure that the device clock to sysref skew is at least somewhat
+# predictable
+set_property IOB <=: $sysref_iob :> \
+  [get_cells {i_lmfc/sysref_r_reg}]
+
+<: if {$async_clk} { :>
+
+set link_clk [get_clocks -of_objects [get_ports -quiet {clk}]]
+set device_clk [get_clocks -of_objects [get_ports -quiet {device_clk}]]
+
+# sync bits
+set_false_path \
+  -from $link_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
+
+# sync event i_sync_lmfc
+set_false_path -quiet \
+  -from $device_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
+
+set_false_path -quiet \
+  -from $link_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
+
+# elastic buffer distributed RAM
+set_false_path -quiet \
+  -from $link_clk \
+  -to [get_cells -quiet -hier *rd_data_reg* \
+    -filter {NAME =~ *i_elastic_buffer* && IS_SEQUENTIAL}]
+
+<: if {$link_mode == 2} { :>
+# sync bits i_buffer_release_cdc 64b66b
+set_false_path \
+  -from $device_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
+<: } :>
+
+<: } :>
+