initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := jesd204_soft_pcs_tx
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GENERIC_DEPS += jesd204_8b10b_encoder.v
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GENERIC_DEPS += jesd204_soft_pcs_tx.v
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INTEL_DEPS += jesd204_soft_pcs_tx_hw.tcl
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include ../../scripts/library.mk
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_8b10b_encoder (
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input in_disparity,
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input [7:0] in_char,
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input in_charisk,
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output [9:0] out_char,
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output out_disparity
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);
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/*
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* Only supports the subset of 8b10b that is used by JESD204.
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* If non-supported control characters are supplied the output is undefined.
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*/
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reg [5:0] data6b;
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reg [5:0] out6b;
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reg may_invert6b;
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reg disparity6b;
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reg [3:0] data4b;
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reg [3:0] out4b;
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reg may_invert4b;
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reg disparity4b;
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wire disparity4b_in;
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reg alt7;
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always @(*) begin
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if (in_charisk == 1'b1) begin
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// Assume K28.x
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data6b = 6'b000011;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end else begin
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case (in_char[4:0])
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5'd00: begin
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data6b = 6'b000110;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd01: begin
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data6b = 6'b010001;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd02: begin
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data6b = 6'b010010;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd03: begin
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data6b = 6'b100011;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd04: begin
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data6b = 6'b010100;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd05: begin
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data6b = 6'b100101;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd06: begin
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data6b = 6'b100110;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd07: begin
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data6b = 6'b111000;
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may_invert6b = 1'b1;
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disparity6b = 1'b0;
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end
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5'd08: begin
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data6b = 6'b011000;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd09: begin
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data6b = 6'b101001;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd10: begin
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data6b = 6'b101010;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd11: begin
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data6b = 6'b001011;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd12: begin
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data6b = 6'b101100;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd13: begin
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data6b = 6'b001101;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd14: begin
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data6b = 6'b001110;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd15: begin
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data6b = 6'b000101;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd16: begin
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data6b = 6'b001001;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd17: begin
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data6b = 6'b110001;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd18: begin
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data6b = 6'b110010;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd19: begin
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data6b = 6'b010011;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd20: begin
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data6b = 6'b110100;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd21: begin
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data6b = 6'b010101;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd22: begin
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data6b = 6'b010110;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd23: begin
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data6b = 6'b101000;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd24: begin
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data6b = 6'b001100;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd25: begin
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data6b = 6'b011001;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd26: begin
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data6b = 6'b011010;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd27: begin
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data6b = 6'b100100;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd28: begin
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data6b = 6'b011100;
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may_invert6b = 1'b0;
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disparity6b = 1'b0;
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end
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5'd29: begin
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data6b = 6'b100010;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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5'd30: begin
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data6b = 6'b100001;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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default: begin
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data6b = 6'b001010;
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may_invert6b = 1'b1;
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disparity6b = 1'b1;
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end
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endcase
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end
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end
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always @(*) begin
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if (in_charisk == 1'b1) begin
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alt7 = 1'b1;
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end else begin
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// case (in_char[4:0])
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// 5'd11, 5'd13, 5'd14: alt7 = in_disparity;
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// 5'd17, 5'd18, 5'd20: alt7 = ~in_disparity;
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// default: alt7 = 1'b0;
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// endcase
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// Slightly better packing
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case ({may_invert6b,data6b[5:4]})
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3'b000: alt7 = in_disparity;
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3'b011: alt7 = ~in_disparity;
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default: alt7 = 1'b0;
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endcase
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end
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end
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always @(*) begin
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case (in_char[7:5])
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3'd0: begin
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data4b = 4'b0010;
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may_invert4b = 1'b1;
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disparity4b = 1'b1;
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end
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3'd1: begin
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data4b = 4'b1001;
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may_invert4b = in_charisk;
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disparity4b = 1'b0;
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end
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3'd2: begin
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data4b = 4'b1010;
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may_invert4b = in_charisk;
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disparity4b = 1'b0;
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end
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3'd3: begin
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data4b = 4'b1100;
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may_invert4b = 1'b1;
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disparity4b = 1'b0;
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end
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3'd4: begin
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data4b = 4'b0100;
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may_invert4b = 1'b1;
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disparity4b = 1'b1;
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end
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3'd5: begin
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data4b = 4'b0101;
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may_invert4b = in_charisk;
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disparity4b = 1'b0;
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end
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3'd6: begin
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data4b = 4'b0110;
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may_invert4b = in_charisk;
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disparity4b = 1'b0;
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end
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default: begin
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if (alt7 == 1'b1) begin
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data4b = 4'b0001;
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end else begin
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data4b = 4'b1000;
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end
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may_invert4b = 1'b1;
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disparity4b = 1'b1;
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end
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endcase
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end
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assign disparity4b_in = in_disparity ^ disparity6b;
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assign out_disparity = disparity4b_in ^ disparity4b;
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always @(*) begin
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if (in_disparity == 1'b0 && may_invert6b == 1'b1) begin
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out6b = ~data6b;
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end else begin
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out6b = data6b;
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end
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if (disparity4b_in == 1'b0 && may_invert4b == 1'b1) begin
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out4b = ~data4b;
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end else begin
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out4b = data4b;
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end
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end
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assign out_char = {out4b,out6b};
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endmodule
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@@ -0,0 +1,61 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_soft_pcs_tx #(
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parameter NUM_LANES = 1,
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parameter DATA_PATH_WIDTH = 4,
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parameter INVERT_OUTPUTS = 0
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) (
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input clk,
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input reset,
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input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char,
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input [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk,
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output reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data
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);
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reg [NUM_LANES-1:0] disparity = 'h00;
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wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
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wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s;
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always @(posedge clk) begin
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data <= INVERT_OUTPUTS ? ~data_s : data_s;
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end
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generate
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genvar lane;
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genvar i;
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for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
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assign disparity_chain[lane][0] = disparity[lane];
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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disparity[lane] <= 1'b0;
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end else begin
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disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH];
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end
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end
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for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
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localparam j = DATA_PATH_WIDTH * lane + i;
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jesd204_8b10b_encoder i_enc (
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.in_char(char[j*8+:8]),
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.in_charisk(charisk[j]),
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.out_char(data_s[j*10+:10]),
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.in_disparity(disparity_chain[lane][i]),
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.out_disparity(disparity_chain[lane][i+1]));
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end
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end
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endgenerate
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endmodule
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@@ -0,0 +1,48 @@
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###############################################################################
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## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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package require qsys 14.0
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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ad_ip_create jesd204_soft_pcs_tx "ADI JESD204 Transmit Soft PCS"
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set_module_property INTERNAL true
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ad_ip_parameter INVERT_OUTPUTS INTEGER 0
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# files
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ad_ip_files jesd204_soft_pcs_tx [list \
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jesd204_soft_pcs_tx.v \
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jesd204_8b10b_encoder.v \
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]
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# clock
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add_interface clock clock end
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add_interface_port clock clk clk Input 1
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# reset
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add_interface reset reset end
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set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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add_interface_port reset reset reset Input 1
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# interfaces
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add_interface tx_phy conduit start
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#set_interface_property tx_phy associatedClock clock
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#set_interface_property tx_phy associatedReset reset
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add_interface_port tx_phy char char Input 32
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add_interface_port tx_phy charisk charisk Input 4
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add_interface tx_raw_data conduit end
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#set_interface_property data associatedClock clock
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#set_interface_property data associatedReset reset
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add_interface_port tx_raw_data data raw_data Output 40
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Block a user