initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_spi_engine
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GENERIC_DEPS += ../../common/ad_rst.v
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GENERIC_DEPS += ../../common/up_axi.v
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GENERIC_DEPS += axi_spi_engine.v
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XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += axi_spi_engine_constr.ttcl
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XILINX_DEPS += axi_spi_engine_ip.tcl
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
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XILINX_LIB_DEPS += util_axis_fifo
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XILINX_LIB_DEPS += util_cdc
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INTEL_DEPS += ../../common/ad_mem.v
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INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
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INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo_address_generator.v
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INTEL_DEPS += ../../util_cdc/sync_bits.v
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INTEL_DEPS += ../../util_cdc/sync_gray.v
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INTEL_DEPS += axi_spi_engine_constr.sdc
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INTEL_DEPS += axi_spi_engine_hw.tcl
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include ../../scripts/library.mk
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@@ -0,0 +1,653 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_spi_engine #(
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parameter CMD_FIFO_ADDRESS_WIDTH = 4,
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parameter SYNC_FIFO_ADDRESS_WIDTH = 4,
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parameter SDO_FIFO_ADDRESS_WIDTH = 5,
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parameter SDI_FIFO_ADDRESS_WIDTH = 5,
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parameter MM_IF_TYPE = 0,
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parameter ASYNC_SPI_CLK = 0,
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parameter NUM_OFFLOAD = 0,
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parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,
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parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
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parameter ID = 0,
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parameter [15:0] DATA_WIDTH = 8,
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parameter [ 7:0] NUM_OF_SDI = 1,
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parameter CFG_INFO_0 = 0,
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parameter CFG_INFO_1 = 0,
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parameter CFG_INFO_2 = 0,
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parameter CFG_INFO_3 = 0
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) (
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// Slave AXI interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// up interface
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input up_clk,
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input up_rstn,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack,
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output reg irq,
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// SPI signals
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input spi_clk,
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output spi_resetn,
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input cmd_ready,
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output cmd_valid,
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output [15:0] cmd_data,
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input sdo_data_ready,
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output sdo_data_valid,
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output [(DATA_WIDTH-1):0] sdo_data,
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output sdi_data_ready,
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input sdi_data_valid,
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input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
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output sync_ready,
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input sync_valid,
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input [7:0] sync_data,
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// Offload ctrl signals
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output offload0_cmd_wr_en,
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output [15:0] offload0_cmd_wr_data,
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output offload0_sdo_wr_en,
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output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
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output offload0_mem_reset,
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output offload0_enable,
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input offload0_enabled,
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output offload_sync_ready,
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input offload_sync_valid,
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input [7:0] offload_sync_data
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);
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localparam PCORE_VERSION = 'h010071;
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localparam S_AXI = 0;
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localparam UP_FIFO = 1;
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wire clk;
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wire rstn;
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wire [CMD_FIFO_ADDRESS_WIDTH-1:0] cmd_fifo_room;
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wire cmd_fifo_almost_empty;
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wire up_cmd_fifo_almost_empty;
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wire [15:0] cmd_fifo_in_data;
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wire cmd_fifo_in_ready;
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wire cmd_fifo_in_valid;
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wire [SDO_FIFO_ADDRESS_WIDTH-1:0] sdo_fifo_room;
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wire sdo_fifo_almost_empty;
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wire up_sdo_fifo_almost_empty;
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wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
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wire sdo_fifo_in_ready;
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wire sdo_fifo_in_valid;
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wire sdi_fifo_out_data_msb_s;
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wire [SDI_FIFO_ADDRESS_WIDTH-1:0] sdi_fifo_level;
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wire sdi_fifo_almost_full;
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wire up_sdi_fifo_almost_full;
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wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
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wire sdi_fifo_out_ready;
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wire sdi_fifo_out_valid;
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wire [7:0] sync_fifo_data;
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wire sync_fifo_valid;
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wire [7:0] offload_sync_fifo_data;
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wire offload_sync_fifo_valid;
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reg up_sw_reset = 1'b1;
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wire up_sw_resetn = ~up_sw_reset;
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reg [31:0] up_rdata_ff = 'd0;
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reg up_wack_ff = 1'b0;
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reg up_rack_ff = 1'b0;
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wire up_wreq_s;
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wire up_rreq_s;
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wire [31:0] up_wdata_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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// Scratch register
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reg [31:0] up_scratch = 'h00;
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reg [7:0] sync_id = 'h00;
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reg sync_id_pending = 1'b0;
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reg [7:0] offload_sync_id = 'h00;
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reg offload_sync_id_pending = 1'b0;
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generate if (MM_IF_TYPE == S_AXI) begin
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// assign clock and reset
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assign clk = s_axi_aclk;
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assign rstn = s_axi_aresetn;
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// interface wrapper
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up_axi #(
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.AXI_ADDRESS_WIDTH (16)
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) i_up_axi (
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.up_rstn(rstn),
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.up_clk(clk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq(up_wreq_s),
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.up_waddr(up_waddr_s),
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.up_wdata(up_wdata_s),
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.up_wack(up_wack_ff),
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.up_rreq(up_rreq_s),
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.up_raddr(up_raddr_s),
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.up_rdata(up_rdata_ff),
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.up_rack(up_rack_ff));
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assign up_rdata = 32'b0;
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assign up_rack = 1'b0;
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assign up_wack = 1'b0;
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end
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endgenerate
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generate if (MM_IF_TYPE == UP_FIFO) begin
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// assign clock and reset
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assign clk = up_clk;
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assign rstn = up_rstn;
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assign up_wreq_s = up_wreq;
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assign up_waddr_s = up_waddr;
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assign up_wdata_s = up_wdata;
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assign up_wack = up_wack_ff;
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assign up_rreq_s = up_rreq;
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assign up_raddr_s = up_raddr;
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assign up_rdata = up_rdata_ff;
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assign up_rack = up_rack_ff;
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end
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endgenerate
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// IRQ handling
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reg [4:0] up_irq_mask = 5'h0;
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wire [4:0] up_irq_source;
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wire [4:0] up_irq_pending;
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assign up_irq_source = {
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offload_sync_id_pending,
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sync_id_pending,
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up_sdi_fifo_almost_full,
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up_sdo_fifo_almost_empty,
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up_cmd_fifo_almost_empty
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};
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assign up_irq_pending = up_irq_mask & up_irq_source;
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always @(posedge clk) begin
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if (rstn == 1'b0)
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irq <= 1'b0;
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else
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irq <= |up_irq_pending;
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end
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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up_wack_ff <= 1'b0;
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up_scratch <= 'h00;
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up_sw_reset <= 1'b1;
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end else begin
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up_wack_ff <= up_wreq_s;
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h02: up_scratch <= up_wdata_s;
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8'h10: up_sw_reset <= up_wdata_s;
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endcase
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end
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end
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end
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reg offload0_enable_reg;
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reg offload0_mem_reset_reg;
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wire offload0_enabled_s;
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// the software reset should reset all the registers
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always @(posedge clk) begin
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if (up_sw_resetn == 1'b0) begin
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up_irq_mask <= 'h00;
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offload0_enable_reg <= 1'b0;
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offload0_mem_reset_reg <= 1'b0;
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end else begin
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h20: up_irq_mask <= up_wdata_s;
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8'h40: offload0_enable_reg <= up_wdata_s[0];
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8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
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endcase
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end
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end
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end
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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up_rack_ff <= 'd0;
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end else begin
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up_rack_ff <= up_rreq_s;
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end
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end
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generate
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if (NUM_OF_SDI > 1) begin
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// Only the first two SDI data can be recovered through AXI regmap
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
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end else begin
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
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end
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endgenerate
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always @(posedge clk) begin
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case (up_raddr_s)
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8'h00: up_rdata_ff <= PCORE_VERSION;
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8'h01: up_rdata_ff <= ID;
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8'h02: up_rdata_ff <= up_scratch;
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8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
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8'h10: up_rdata_ff <= up_sw_reset;
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8'h20: up_rdata_ff <= up_irq_mask;
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8'h21: up_rdata_ff <= up_irq_pending;
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8'h22: up_rdata_ff <= up_irq_source;
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8'h30: up_rdata_ff <= sync_id;
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8'h31: up_rdata_ff <= offload_sync_id;
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8'h34: up_rdata_ff <= cmd_fifo_room;
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8'h35: up_rdata_ff <= sdo_fifo_room;
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8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* beacuse of first-word-fall-through */
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8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
|
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8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
|
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8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
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8'h40: up_rdata_ff <= {offload0_enable_reg};
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8'h41: up_rdata_ff <= {offload0_enabled_s};
|
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8'h80: up_rdata_ff <= CFG_INFO_0;
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8'h81: up_rdata_ff <= CFG_INFO_1;
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8'h82: up_rdata_ff <= CFG_INFO_2;
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8'h83: up_rdata_ff <= CFG_INFO_3;
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default: up_rdata_ff <= 'h00;
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endcase
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end
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always @(posedge clk) begin
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if (up_sw_resetn == 1'b0) begin
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sync_id <= 'h00;
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sync_id_pending <= 1'b0;
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end else begin
|
||||
if (sync_fifo_valid == 1'b1) begin
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||||
sync_id <= sync_fifo_data;
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sync_id_pending <= 1'b1;
|
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end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
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sync_id_pending <= 1'b0;
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end
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||||
end
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||||
end
|
||||
|
||||
always @(posedge clk) begin
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||||
if (up_sw_resetn == 1'b0) begin
|
||||
offload_sync_id <= 'h00;
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end else begin
|
||||
if (offload_sync_fifo_valid == 1'b1) begin
|
||||
offload_sync_id <= offload_sync_fifo_data;
|
||||
offload_sync_id_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[4] == 1'b1) begin
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
wire spi_reset;
|
||||
ad_rst i_spi_resetn (
|
||||
.rst_async(up_sw_reset),
|
||||
.clk(spi_clk),
|
||||
.rst(spi_reset),
|
||||
.rstn());
|
||||
assign spi_resetn = ~spi_reset;
|
||||
end else begin
|
||||
assign spi_resetn = ~up_sw_reset;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38;
|
||||
assign cmd_fifo_in_data = up_wdata_s[15:0];
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(1)
|
||||
) i_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(cmd_fifo_in_ready),
|
||||
.s_axis_valid(cmd_fifo_in_valid),
|
||||
.s_axis_data(cmd_fifo_in_data),
|
||||
.s_axis_room(cmd_fifo_room),
|
||||
.s_axis_tlast(1'b0),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(cmd_ready),
|
||||
.m_axis_valid(cmd_valid),
|
||||
.m_axis_data(cmd_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty(cmd_fifo_almost_empty),
|
||||
.m_axis_level());
|
||||
|
||||
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
|
||||
assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(1)
|
||||
) i_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(sdo_fifo_in_ready),
|
||||
.s_axis_valid(sdo_fifo_in_valid),
|
||||
.s_axis_data(sdo_fifo_in_data),
|
||||
.s_axis_room(sdo_fifo_room),
|
||||
.s_axis_tlast(1'b0),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(sdo_data_ready),
|
||||
.m_axis_valid(sdo_data_valid),
|
||||
.m_axis_data(sdo_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty(sdo_fifo_almost_empty));
|
||||
|
||||
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(31)
|
||||
) i_sdi_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sdi_data_ready),
|
||||
.s_axis_valid(sdi_data_valid),
|
||||
.s_axis_data(sdi_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_tlast(),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(sdi_fifo_almost_full),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(sdi_fifo_out_ready),
|
||||
.m_axis_valid(sdi_fifo_out_valid),
|
||||
.m_axis_data(sdi_fifo_out_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(sdi_fifo_level),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty());
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
// synchronization FIFO for the SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sync_ready),
|
||||
.s_axis_valid(sync_valid),
|
||||
.s_axis_data(sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(sync_fifo_valid),
|
||||
.m_axis_data(sync_fifo_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
// synchronization FIFO for the offload command interface
|
||||
wire up_offload0_cmd_wr_en_s;
|
||||
wire [15:0] up_offload0_cmd_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_offload_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_cmd_wr_en_s),
|
||||
.s_axis_data(up_offload0_cmd_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_cmd_wr_en),
|
||||
.m_axis_data(offload0_cmd_wr_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
|
||||
|
||||
// synchronization FIFO for the offload SDO interface
|
||||
wire up_offload0_sdo_wr_en_s;
|
||||
wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_offload_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_sdo_wr_en_s),
|
||||
.s_axis_data(up_offload0_sdo_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_sdo_wr_en),
|
||||
.m_axis_data(offload0_sdo_wr_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
// synchronization FIFO for the Offload SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_offload_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(offload_sync_ready),
|
||||
.s_axis_valid(offload_sync_valid),
|
||||
.s_axis_data(offload_sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload_sync_fifo_valid),
|
||||
.m_axis_data(offload_sync_fifo_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
end else begin /* ASYNC_SPI_CLK == 0 */
|
||||
|
||||
assign sync_fifo_valid = sync_valid;
|
||||
assign sync_fifo_data = sync_data;
|
||||
assign sync_ready = 1'b1;
|
||||
|
||||
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign offload0_cmd_wr_data = up_wdata_s[15:0];
|
||||
|
||||
assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
assign offload_sync_fifo_valid = offload_sync_valid;
|
||||
assign offload_sync_fifo_data = offload_sync_data;
|
||||
assign offload_sync_ready = 1'b1;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enable_sync (
|
||||
.in_bits (offload0_enable_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enabled_sync (
|
||||
.in_bits (offload0_enabled),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (clk),
|
||||
.out_bits (offload0_enabled_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_mem_reset_sync (
|
||||
.in_bits (offload0_mem_reset_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_mem_reset));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (3),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_fifo_status (
|
||||
.in_bits ({cmd_fifo_almost_empty, sdi_fifo_almost_full, sdo_fifo_almost_empty}),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (clk),
|
||||
.out_bits ({up_cmd_fifo_almost_empty, up_sdi_fifo_almost_full, up_sdo_fifo_almost_empty}));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,420 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="7614137f133e45a3b5014a3375bb1862"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_spi_engine.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_spi_engine_constr.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_spi_engine"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../xilinx/common/ad_rst_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,8 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
set_false_path \
|
||||
-to [get_registers *cdc_sync_stage1*]
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
# SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
|
||||
|
||||
<: if { $async_spi_clk } { :>
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
|
||||
|
||||
set_false_path -quiet \
|
||||
-from [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enable_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enabled_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_mem_reset_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_fifo_status/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
<: } :>
|
||||
@@ -0,0 +1,188 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create axi_spi_engine {AXI SPI Engine} p_elaboration
|
||||
ad_ip_files axi_spi_engine [list\
|
||||
$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v \
|
||||
$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo_address_generator.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_gray.v \
|
||||
$ad_hdl_dir/library/common/ad_mem.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/ad_rst.v \
|
||||
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
|
||||
axi_spi_engine_constr.sdc \
|
||||
axi_spi_engine.v]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter CMD_FIFO_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter SYNC_FIFO_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter SDO_FIFO_ADDRESS_WIDTH INTEGER 5
|
||||
ad_ip_parameter SDI_FIFO_ADDRESS_WIDTH INTEGER 5
|
||||
ad_ip_parameter MM_IF_TYPE INTEGER 1
|
||||
ad_ip_parameter ASYNC_SPI_CLK INTEGER 0
|
||||
ad_ip_parameter NUM_OFFLOAD INTEGER 1
|
||||
ad_ip_parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter ID INTEGER 0
|
||||
ad_ip_parameter DATA_WIDTH INTEGER 8
|
||||
ad_ip_parameter NUM_OF_SDI INTEGER 1
|
||||
|
||||
proc p_elaboration {} {
|
||||
|
||||
# read parameters
|
||||
|
||||
set mm_if_type [get_parameter_value "MM_IF_TYPE"]
|
||||
|
||||
set num_of_sdi [get_parameter_value NUM_OF_SDI]
|
||||
set data_width [get_parameter_value DATA_WIDTH]
|
||||
|
||||
# interrupt
|
||||
|
||||
add_interface interrupt_sender interrupt end
|
||||
add_interface_port interrupt_sender irq irq Output 1
|
||||
|
||||
# Microprocessor interface
|
||||
|
||||
ad_interface clock up_clk input 1
|
||||
ad_interface reset up_rstn input 1 if_up_clk
|
||||
ad_interface signal up_wreq input 1
|
||||
ad_interface signal up_wack output 1
|
||||
ad_interface signal up_waddr input 14
|
||||
ad_interface signal up_wdata input 32
|
||||
ad_interface signal up_rreq input 1
|
||||
ad_interface signal up_rack output 1
|
||||
ad_interface signal up_raddr output 14
|
||||
ad_interface signal up_rdata output 32
|
||||
|
||||
# AXI Memory Mapped interface
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16
|
||||
|
||||
set disabled_intfs {}
|
||||
if {$mm_if_type} {
|
||||
|
||||
# uProcessor interface active for regmap, deactivate S_AXI
|
||||
lappend disabled_intfs s_axi
|
||||
|
||||
set_port_property s_axi_aclk termination true
|
||||
set_port_property s_axi_aresetn termination true
|
||||
set_port_property s_axi_aresetn termination_value 1
|
||||
set_port_property s_axi_awvalid termination true
|
||||
set_port_property s_axi_awaddr termination true
|
||||
set_port_property s_axi_awprot termination true
|
||||
set_port_property s_axi_wvalid termination true
|
||||
set_port_property s_axi_wdata termination true
|
||||
set_port_property s_axi_wstrb termination true
|
||||
set_port_property s_axi_bready termination true
|
||||
set_port_property s_axi_arvalid termination true
|
||||
set_port_property s_axi_araddr termination true
|
||||
set_port_property s_axi_arprot termination true
|
||||
set_port_property s_axi_rready termination true
|
||||
|
||||
} else {
|
||||
|
||||
set_interface_property interrupt_sender associatedAddressablePoint s_axi
|
||||
set_interface_property interrupt_sender associatedClock s_axi_clock
|
||||
set_interface_property interrupt_sender associatedReset s_axi_reset
|
||||
set_interface_property interrupt_sender ENABLED true
|
||||
|
||||
# AXI4 Slave is active for regmap, deactivate uP
|
||||
lappend disabled_intfs if_up_clk if_up_rstn if_up_wreq if_up_wack if_up_waddr \
|
||||
if_up_wdata if_up_rreq if_up_rack if_up_raddr if_up_rdata
|
||||
|
||||
set_port_property up_clk termination true
|
||||
set_port_property up_rstn termination true
|
||||
set_port_property up_rstn termination_value 1
|
||||
set_port_property up_wreq termination true
|
||||
set_port_property up_waddr termination true
|
||||
set_port_property up_wdata termination true
|
||||
set_port_property up_rreq termination true
|
||||
set_port_property up_raddr termination true
|
||||
|
||||
}
|
||||
|
||||
ad_interface signal pulse_gen_period output 32
|
||||
ad_interface signal pulse_gen_width output 32
|
||||
ad_interface signal pulse_gen_load output 1
|
||||
|
||||
lappend disabled_intfs if_pulse_gen_period if_pulse_gen_width if_pulse_gen_load
|
||||
|
||||
foreach interface $disabled_intfs {
|
||||
set_interface_property $interface ENABLED false
|
||||
}
|
||||
|
||||
# SPI Engine interfaces
|
||||
|
||||
ad_interface clock spi_clk input 1
|
||||
ad_interface reset spi_resetn output 1 if_spi_clk
|
||||
|
||||
add_interface cmd axi4stream start
|
||||
add_interface_port cmd cmd_ready tready input 1
|
||||
add_interface_port cmd cmd_valid tvalid output 1
|
||||
add_interface_port cmd cmd_data tdata output 16
|
||||
|
||||
set_interface_property cmd associatedClock if_spi_clk
|
||||
set_interface_property cmd associatedReset if_spi_resetn
|
||||
|
||||
add_interface sdo_data axi4stream start
|
||||
add_interface_port sdo_data sdo_data_ready tready input 1
|
||||
add_interface_port sdo_data sdo_data_valid tvalid output 1
|
||||
add_interface_port sdo_data sdo_data tdata output $data_width
|
||||
|
||||
set_interface_property sdo_data associatedClock if_spi_clk
|
||||
set_interface_property sdo_data associatedReset if_spi_resetn
|
||||
|
||||
add_interface sdi_data axi4stream end
|
||||
add_interface_port sdi_data sdi_data_ready tready output 1
|
||||
add_interface_port sdi_data sdi_data_valid tvalid input 1
|
||||
add_interface_port sdi_data sdi_data tdata input [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property sdi_data associatedClock if_spi_clk
|
||||
set_interface_property sdi_data associatedReset if_spi_resetn
|
||||
|
||||
add_interface sync axi4stream end
|
||||
add_interface_port sync sync_valid tvalid input 1
|
||||
add_interface_port sync sync_ready tready output 1
|
||||
add_interface_port sync sync_data tdata input 8
|
||||
|
||||
set_interface_property sync associatedClock if_spi_clk
|
||||
set_interface_property sync associatedReset if_spi_resetn
|
||||
|
||||
# Offload interfaces
|
||||
|
||||
add_interface offload0_cmd conduit end
|
||||
add_interface_port offload0_cmd offload0_cmd_wr_en wre output 1
|
||||
add_interface_port offload0_cmd offload0_cmd_wr_data data output 16
|
||||
|
||||
set_interface_property offload0_cmd associatedClock if_spi_clk
|
||||
set_interface_property offload0_cmd associatedReset none
|
||||
|
||||
add_interface offload0_sdo conduit end
|
||||
add_interface_port offload0_sdo offload0_sdo_wr_en wre output 1
|
||||
add_interface_port offload0_sdo offload0_sdo_wr_data data output $data_width
|
||||
|
||||
set_interface_property offload0_sdo associatedClock if_spi_clk
|
||||
set_interface_property offload0_sdo associatedReset none
|
||||
|
||||
ad_interface signal offload0_mem_reset output 1 reset
|
||||
ad_interface signal offload0_enable output 1 enable
|
||||
ad_interface signal offload0_enabled input 1 enabled
|
||||
|
||||
add_interface offload_sync axi4stream end
|
||||
add_interface_port offload_sync offload_sync_valid tvalid input 1
|
||||
add_interface_port offload_sync offload_sync_ready tready output 1
|
||||
add_interface_port offload_sync offload_sync_data tdata input 8
|
||||
|
||||
set_interface_property offload_sync associatedClock if_spi_clk
|
||||
set_interface_property offload_sync associatedReset if_spi_resetn
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,304 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ip
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create axi_spi_engine
|
||||
adi_ip_files axi_spi_engine [list \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"axi_spi_engine_constr.ttcl" \
|
||||
"axi_spi_engine.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties axi_spi_engine
|
||||
adi_ip_ttcl axi_spi_engine "axi_spi_engine_constr.ttcl"
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
]
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi} [ipx::current_core]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "spi_engine_ctrl" "master" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{
|
||||
{"cmd_ready" "CMD_READY"} \
|
||||
{"cmd_valid" "CMD_VALID"} \
|
||||
{"cmd_data" "CMD_DATA"} \
|
||||
{"sdo_data_ready" "SDO_READY"} \
|
||||
{"sdo_data_valid" "SDO_VALID"} \
|
||||
{"sdo_data" "SDO_DATA"} \
|
||||
{"sdi_data_ready" "SDI_READY"} \
|
||||
{"sdi_data_valid" "SDI_VALID"} \
|
||||
{"sdi_data" "SDI_DATA"} \
|
||||
{"sync_ready" "SYNC_READY"} \
|
||||
{"sync_valid" "SYNC_VALID"} \
|
||||
{"sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master"
|
||||
|
||||
adi_add_bus "spi_engine_offload_ctrl0" "master" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
|
||||
{ \
|
||||
{ "offload0_cmd_wr_en" "CMD_WR_EN"} \
|
||||
{ "offload0_cmd_wr_data" "CMD_WR_DATA"} \
|
||||
{ "offload0_sdo_wr_en" "SDO_WR_EN"} \
|
||||
{ "offload0_sdo_wr_data" "SDO_WR_DATA"} \
|
||||
{ "offload0_enable" "ENABLE"} \
|
||||
{ "offload0_enabled" "ENABLED"} \
|
||||
{ "offload0_mem_reset" "MEM_RESET"} \
|
||||
{ "offload_sync_ready" "SYNC_READY"} \
|
||||
{ "offload_sync_valid" "SYNC_VALID"} \
|
||||
{ "offload_sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn"
|
||||
|
||||
foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} {
|
||||
set_property DRIVER_VALUE "0" [ipx::get_ports $port]
|
||||
}
|
||||
adi_set_bus_dependency "spi_engine_offload_ctrl0" "spi_engine_offload_ctrl0" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OFFLOAD')) > 0)"
|
||||
|
||||
adi_set_bus_dependency "s_axi" "s_axi" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 0)"
|
||||
|
||||
adi_set_ports_dependency "up_clk" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_rstn" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_wreq" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_waddr" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_wdata" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_rreq" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_raddr" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_wack" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_rdata" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_rack" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
|
||||
## Parameter validations
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
## ID
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "255" \
|
||||
] \
|
||||
[ipx::get_user_parameters ID -of_objects $cc]
|
||||
|
||||
## CMD_FIFO_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters CMD_FIFO_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## SYNC_FIFO_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters SYNC_FIFO_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## SDO_FIFO_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDO_FIFO_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## SDI_FIFO_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDI_FIFO_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## MM_IF_TYPE
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "pairs" \
|
||||
"value_validation_pairs" { \
|
||||
"AXI4 Memory Mapped" "0" \
|
||||
"ADI uP FIFO" "1" \
|
||||
} \
|
||||
] \
|
||||
[ipx::get_user_parameters MM_IF_TYPE -of_objects $cc]
|
||||
|
||||
## ASYNC_SPI_CLK
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc]
|
||||
|
||||
## NUM_OFFLOAD
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OFFLOAD -of_objects $cc]
|
||||
|
||||
## OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## DATA_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "8" \
|
||||
"value_validation_range_maximum" "256" \
|
||||
] \
|
||||
[ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
|
||||
## NUM_OF_SDI
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
|
||||
## Customize IP Layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create general configuration page
|
||||
ipgui::add_page -name {AXI SPI Engine soft-controller} -component [ipx::current_core] -display_name {AXI SPI Engine soft-controller}
|
||||
set page0 [ipgui::get_pagespec -name "AXI SPI Engine soft-controller" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration" ]
|
||||
|
||||
ipgui::add_param -name "ID" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Core ID" \
|
||||
"tooltip" "\[ID\] Core instance ID" \
|
||||
] [ipgui::get_guiparamspec -name "ID" -component $cc]
|
||||
|
||||
ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Parallel data width" \
|
||||
"tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO lines" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
ipgui::add_param -name "MM_IF_TYPE" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Memory Mapped Interface Type" \
|
||||
"tooltip" "\[MM_IF_TYPE\] Define the memory mapped interface type" \
|
||||
] [ipgui::get_guiparamspec -name "MM_IF_TYPE" -component $cc]
|
||||
|
||||
ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Asynchronous core clock" \
|
||||
"tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \
|
||||
] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc]
|
||||
|
||||
## Command stream FIFO depth configuration
|
||||
set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \
|
||||
-parent $page0 -display_name "Command stream FIFO configuration" ]
|
||||
|
||||
ipgui::add_param -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Command FIFO address width" \
|
||||
"tooltip" "\[CMD_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "SYNC FIFO address width" \
|
||||
"tooltip" "\[SYNC_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "MOSI FIFO address width" \
|
||||
"tooltip" "\[SDO_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "MISO FIFO address width" \
|
||||
"tooltip" "\[SDI_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
## Offload module(s) configuration
|
||||
set offload_group [ipgui::add_group -name "Offload module configuration" -component $cc \
|
||||
-parent $page0 -display_name "Offload module configuration" ]
|
||||
|
||||
ipgui::add_param -name "NUM_OFFLOAD" -component $cc -parent $offload_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of offloads" \
|
||||
"tooltip" "\[NUM_OFFLOAD\] Number of offloads" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OFFLOAD" -component $cc]
|
||||
|
||||
ipgui::add_param -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Offload command FIFO address width" \
|
||||
"tooltip" "\[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc]
|
||||
set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
ipgui::add_param -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Offload MOSI FIFO address width" \
|
||||
"tooltip" "\[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc]
|
||||
set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files $cc
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,3 @@
|
||||
# This file is automatically written. Do not modify.
|
||||
proc gen_USERPARAMETER_OFFLOAD0_CMD_MEM_ADDRESS_WIDTH_ENABLEMENT {NUM_OFFLOAD } {expr $NUM_OFFLOAD > 0}
|
||||
proc gen_USERPARAMETER_OFFLOAD0_SDO_MEM_ADDRESS_WIDTH_ENABLEMENT {NUM_OFFLOAD } {expr $NUM_OFFLOAD > 0}
|
||||
@@ -0,0 +1,289 @@
|
||||
|
||||
# Loading additional proc with user specified bodies to compute parameter values.
|
||||
source [file join [file dirname [file dirname [info script]]] gui/axi_spi_engine_v1_0.gtcl]
|
||||
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set AXI_SPI_Engine_soft-controller [ipgui::add_page $IPINST -name "AXI SPI Engine soft-controller"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${AXI_SPI_Engine_soft-controller}]
|
||||
set ID [ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ID] Core instance ID} ${ID}
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
set MM_IF_TYPE [ipgui::add_param $IPINST -name "MM_IF_TYPE" -parent ${General_Configuration}]
|
||||
set_property tooltip {[MM_IF_TYPE] Define the memory mapped interface type} ${MM_IF_TYPE}
|
||||
set ASYNC_SPI_CLK [ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_SPI_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_SPI_CLK}
|
||||
|
||||
#Adding Group
|
||||
set Command_stream_FIFO_configuration [ipgui::add_group $IPINST -name "Command stream FIFO configuration" -parent ${AXI_SPI_Engine_soft-controller}]
|
||||
set CMD_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "CMD_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[CMD_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${CMD_FIFO_ADDRESS_WIDTH}
|
||||
set SYNC_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SYNC_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SYNC_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SYNC_FIFO_ADDRESS_WIDTH}
|
||||
set SDO_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDO_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDO_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDO_FIFO_ADDRESS_WIDTH}
|
||||
set SDI_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDI_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDI_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDI_FIFO_ADDRESS_WIDTH}
|
||||
|
||||
#Adding Group
|
||||
set Offload_module_configuration [ipgui::add_group $IPINST -name "Offload module configuration" -parent ${AXI_SPI_Engine_soft-controller}]
|
||||
set NUM_OFFLOAD [ipgui::add_param $IPINST -name "NUM_OFFLOAD" -parent ${Offload_module_configuration}]
|
||||
set_property tooltip {[NUM_OFFLOAD] Number of offloads} ${NUM_OFFLOAD}
|
||||
set OFFLOAD0_CMD_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -parent ${Offload_module_configuration}]
|
||||
set_property tooltip {[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}
|
||||
set OFFLOAD0_SDO_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -parent ${Offload_module_configuration}]
|
||||
set_property tooltip {[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to update OFFLOAD0_CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
|
||||
set OFFLOAD0_CMD_MEM_ADDRESS_WIDTH ${PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}
|
||||
set NUM_OFFLOAD ${PARAM_VALUE.NUM_OFFLOAD}
|
||||
set values(NUM_OFFLOAD) [get_property value $NUM_OFFLOAD]
|
||||
if { [gen_USERPARAMETER_OFFLOAD0_CMD_MEM_ADDRESS_WIDTH_ENABLEMENT $values(NUM_OFFLOAD)] } {
|
||||
set_property enabled true $OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
} else {
|
||||
set_property enabled false $OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to update OFFLOAD0_SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
|
||||
set OFFLOAD0_SDO_MEM_ADDRESS_WIDTH ${PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}
|
||||
set NUM_OFFLOAD ${PARAM_VALUE.NUM_OFFLOAD}
|
||||
set values(NUM_OFFLOAD) [get_property value $NUM_OFFLOAD]
|
||||
if { [gen_USERPARAMETER_OFFLOAD0_SDO_MEM_ADDRESS_WIDTH_ENABLEMENT $values(NUM_OFFLOAD)] } {
|
||||
set_property enabled true $OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
} else {
|
||||
set_property enabled false $OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to validate ASYNC_SPI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_0 { PARAM_VALUE.CFG_INFO_0 } {
|
||||
# Procedure called to update CFG_INFO_0 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_0 { PARAM_VALUE.CFG_INFO_0 } {
|
||||
# Procedure called to validate CFG_INFO_0
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_1 { PARAM_VALUE.CFG_INFO_1 } {
|
||||
# Procedure called to update CFG_INFO_1 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_1 { PARAM_VALUE.CFG_INFO_1 } {
|
||||
# Procedure called to validate CFG_INFO_1
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_2 { PARAM_VALUE.CFG_INFO_2 } {
|
||||
# Procedure called to update CFG_INFO_2 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_2 { PARAM_VALUE.CFG_INFO_2 } {
|
||||
# Procedure called to validate CFG_INFO_2
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_3 { PARAM_VALUE.CFG_INFO_3 } {
|
||||
# Procedure called to update CFG_INFO_3 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_3 { PARAM_VALUE.CFG_INFO_3 } {
|
||||
# Procedure called to validate CFG_INFO_3
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update CMD_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate CMD_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MM_IF_TYPE { PARAM_VALUE.MM_IF_TYPE } {
|
||||
# Procedure called to update MM_IF_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MM_IF_TYPE { PARAM_VALUE.MM_IF_TYPE } {
|
||||
# Procedure called to validate MM_IF_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OFFLOAD { PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to update NUM_OFFLOAD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OFFLOAD { PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to validate NUM_OFFLOAD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDI_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDI_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDO_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDO_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SYNC_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SYNC_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MM_IF_TYPE { MODELPARAM_VALUE.MM_IF_TYPE PARAM_VALUE.MM_IF_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MM_IF_TYPE}] ${MODELPARAM_VALUE.MM_IF_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OFFLOAD { MODELPARAM_VALUE.NUM_OFFLOAD PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OFFLOAD}] ${MODELPARAM_VALUE.NUM_OFFLOAD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_0 { MODELPARAM_VALUE.CFG_INFO_0 PARAM_VALUE.CFG_INFO_0 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_0}] ${MODELPARAM_VALUE.CFG_INFO_0}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_1 { MODELPARAM_VALUE.CFG_INFO_1 PARAM_VALUE.CFG_INFO_1 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_1}] ${MODELPARAM_VALUE.CFG_INFO_1}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_2 { MODELPARAM_VALUE.CFG_INFO_2 PARAM_VALUE.CFG_INFO_2 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_2}] ${MODELPARAM_VALUE.CFG_INFO_2}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_3 { MODELPARAM_VALUE.CFG_INFO_3 PARAM_VALUE.CFG_INFO_3 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_3}] ${MODELPARAM_VALUE.CFG_INFO_3}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
|
||||
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine_ctrl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:directConnection>false</spirit:directConnection>
|
||||
<spirit:isAddressable>false</spirit:isAddressable>
|
||||
<spirit:maxMasters>1</spirit:maxMasters>
|
||||
<spirit:maxSlaves>1</spirit:maxSlaves>
|
||||
</spirit:busDefinition>
|
||||
@@ -0,0 +1,189 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
|
||||
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine_ctrl_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="analog.com"
|
||||
spirit:library="interface"
|
||||
spirit:name="spi_engine_ctrl"
|
||||
spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>CMD_READY</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>CMD_VALID</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>CMD_DATA</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>16</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>16</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDO_READY</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDO_VALID</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDO_DATA</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDI_READY</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDI_VALID</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDI_DATA</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SYNC_READY</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SYNC_VALID</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SYNC_DATA</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
|
||||
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine_offload_ctrl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:directConnection>false</spirit:directConnection>
|
||||
<spirit:isAddressable>false</spirit:isAddressable>
|
||||
<spirit:maxMasters>1</spirit:maxMasters>
|
||||
<spirit:maxSlaves>1</spirit:maxSlaves>
|
||||
</spirit:busDefinition>
|
||||
@@ -0,0 +1,158 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
|
||||
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_engine_offload_ctrl_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="analog.com"
|
||||
spirit:library="interface"
|
||||
spirit:name="spi_engine_offload_ctrl"
|
||||
spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>CMD_WR_EN</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>CMD_WR_DATA</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>16</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>16</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDO_WR_EN</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDO_WR_DATA</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>ENABLE</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>MEM_RESET</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>ENABLED</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SYNC_READY</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SYNC_VALID</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SYNC_DATA</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
@@ -0,0 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
|
||||
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_master</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:directConnection>false</spirit:directConnection>
|
||||
<spirit:isAddressable>false</spirit:isAddressable>
|
||||
<spirit:maxMasters>1</spirit:maxMasters>
|
||||
<spirit:maxSlaves>1</spirit:maxSlaves>
|
||||
<spirit:description>SPI Engine physical interface</spirit:description>
|
||||
</spirit:busDefinition>
|
||||
@@ -0,0 +1,112 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
|
||||
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>spi_master_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="analog.com"
|
||||
spirit:library="interface"
|
||||
spirit:name="spi_master"
|
||||
spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SCLK</spirit:logicalName>
|
||||
<spirit:description>SPI clock</spirit:description>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDI</spirit:logicalName>
|
||||
<spirit:description>Serial data in</spirit:description>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
<spirit:defaultValue>0</spirit:defaultValue>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDO</spirit:logicalName>
|
||||
<spirit:description>Serial data out</spirit:description>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
<spirit:defaultValue>0</spirit:defaultValue>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDO_T</spirit:logicalName>
|
||||
<spirit:description>Serial data out three state controle line</spirit:description>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
<spirit:defaultValue>0</spirit:defaultValue>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>THREE_WIRE</spirit:logicalName>
|
||||
<spirit:description>Three wire mode</spirit:description>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>optional</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
<spirit:defaultValue>0</spirit:defaultValue>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>CS</spirit:logicalName>
|
||||
<spirit:description>Chip select</spirit:description>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
<spirit:defaultValue>0</spirit:defaultValue>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
@@ -0,0 +1,90 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0}} {
|
||||
puts "echo_sclk: $echo_sclk"
|
||||
|
||||
create_bd_cell -type hier $name
|
||||
current_bd_instance /$name
|
||||
|
||||
if {$async_spi_clk == 1} {
|
||||
create_bd_pin -dir I -type clk spi_clk
|
||||
}
|
||||
if {$echo_sclk == 1} {
|
||||
create_bd_pin -dir I -type clk echo_sclk
|
||||
}
|
||||
create_bd_pin -dir I -type clk clk
|
||||
create_bd_pin -dir I -type rst resetn
|
||||
create_bd_pin -dir I trigger
|
||||
create_bd_pin -dir O irq
|
||||
create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
|
||||
|
||||
set execution "${name}_execution"
|
||||
set axi_regmap "${name}_axi_regmap"
|
||||
set offload "${name}_offload"
|
||||
set interconnect "${name}_interconnect"
|
||||
|
||||
ad_ip_instance spi_engine_execution $execution
|
||||
ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width
|
||||
ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs
|
||||
ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi
|
||||
ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1
|
||||
ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay
|
||||
ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk
|
||||
|
||||
ad_ip_instance axi_spi_engine $axi_regmap
|
||||
ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width
|
||||
ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
|
||||
ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi
|
||||
ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk
|
||||
|
||||
ad_ip_instance spi_engine_offload $offload
|
||||
ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width
|
||||
ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK $async_spi_clk
|
||||
ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi
|
||||
|
||||
ad_ip_instance spi_engine_interconnect $interconnect
|
||||
ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
|
||||
ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi
|
||||
|
||||
ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
|
||||
ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
|
||||
ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
|
||||
ad_connect $interconnect/m_ctrl $execution/ctrl
|
||||
ad_connect $offload/offload_sdi m_axis_sample
|
||||
ad_connect $offload/trigger trigger
|
||||
|
||||
ad_connect $execution/spi m_spi
|
||||
|
||||
ad_connect clk $axi_regmap/s_axi_aclk
|
||||
|
||||
if {$async_spi_clk == 1} {
|
||||
ad_connect spi_clk $offload/spi_clk
|
||||
ad_connect spi_clk $offload/ctrl_clk
|
||||
ad_connect spi_clk $execution/clk
|
||||
ad_connect spi_clk $axi_regmap/spi_clk
|
||||
ad_connect spi_clk $interconnect/clk
|
||||
} else {
|
||||
ad_connect clk $offload/spi_clk
|
||||
ad_connect clk $offload/ctrl_clk
|
||||
ad_connect clk $execution/clk
|
||||
ad_connect clk $axi_regmap/spi_clk
|
||||
ad_connect clk $interconnect/clk
|
||||
}
|
||||
|
||||
if {$echo_sclk == 1} {
|
||||
ad_connect echo_sclk $execution/echo_sclk
|
||||
}
|
||||
|
||||
ad_connect $axi_regmap/spi_resetn $offload/spi_resetn
|
||||
ad_connect $axi_regmap/spi_resetn $execution/resetn
|
||||
ad_connect $axi_regmap/spi_resetn $interconnect/resetn
|
||||
|
||||
ad_connect resetn $axi_regmap/s_axi_aresetn
|
||||
ad_connect irq $axi_regmap/irq
|
||||
|
||||
current_bd_instance /
|
||||
}
|
||||
@@ -0,0 +1,13 @@
|
||||
####################################################################################
|
||||
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
|
||||
### SPDX short identifier: BSD-1-Clause
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := spi_axis_reorder
|
||||
|
||||
GENERIC_DEPS += spi_axis_reorder.v
|
||||
|
||||
XILINX_DEPS += spi_axis_reorder_ip.tcl
|
||||
|
||||
include ../../scripts/library.mk
|
||||
@@ -0,0 +1,383 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>spi_axis_reorder</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis_m_axis_signal_clock</spirit:name>
|
||||
<spirit:displayName>s_axis_m_axis_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>axis_aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_M_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">s_axis:m_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_M_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">axis_aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis_m_axis_signal_reset</spirit:name>
|
||||
<spirit:displayName>s_axis_m_axis_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>axis_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_M_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_axis_reorder</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>6f89b3dc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_axis_reorder</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>6f89b3dc</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>130431ad</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>axis_aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>axis_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_data</spirit:name>
|
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<spirit:name>m_axis_valid</spirit:name>
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</spirit:port>
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<spirit:port>
|
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<spirit:name>m_axis_ready</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:left spirit:format="long">63</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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</spirit:ports>
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<spirit:modelParameters>
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<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
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<spirit:name>NUM_OF_LANES</spirit:name>
|
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<spirit:displayName>Num Of Lanes</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_LANES">2</spirit:value>
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</spirit:modelParameter>
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</spirit:modelParameters>
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</spirit:model>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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</spirit:fileSet>
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<spirit:description>spi_axis_reorder_v1_0</spirit:description>
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<spirit:parameter>
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<spirit:name>NUM_OF_LANES</spirit:name>
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<spirit:displayName>Num Of Lanes</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_LANES">2</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">spi_axis_reorder_v1_0</spirit:value>
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</spirit:parameter>
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|
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
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// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
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// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
// Re-ordering module for Flexi-SPI
|
||||
//
|
||||
module spi_axis_reorder #(
|
||||
|
||||
parameter [3:0] NUM_OF_LANES = 2
|
||||
) (
|
||||
input axis_aclk,
|
||||
input axis_aresetn,
|
||||
|
||||
input s_axis_valid,
|
||||
output s_axis_ready,
|
||||
input [(NUM_OF_LANES * 32)-1:0] s_axis_data,
|
||||
|
||||
output m_axis_valid,
|
||||
input m_axis_ready,
|
||||
output [63:0] m_axis_data
|
||||
);
|
||||
|
||||
// re-packager is always ready
|
||||
assign s_axis_ready = 1'b1;
|
||||
|
||||
genvar i, j;
|
||||
generate
|
||||
if (NUM_OF_LANES == 1) begin : g_reorder_1_lane_interleaved
|
||||
|
||||
reg wr_addr = 0;
|
||||
reg [63:0] axis_data_int;
|
||||
reg mem_is_full;
|
||||
|
||||
// address control
|
||||
// NOTE: ready is ignored, taking the fact that the module is always ready
|
||||
always @(posedge axis_aclk) begin
|
||||
if (axis_aresetn == 1'b0) begin
|
||||
wr_addr <= 1'b0;
|
||||
axis_data_int <= 64'b0;
|
||||
end else begin
|
||||
if ((s_axis_valid == 1'b1) && (s_axis_ready == 1'b1)) begin
|
||||
wr_addr <= wr_addr + 1'b1;
|
||||
axis_data_int <= (wr_addr) ? {s_axis_data, axis_data_int[31:0]} :
|
||||
{axis_data_int[63:32], s_axis_data};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// latch the state of the memory
|
||||
always @(posedge axis_aclk) begin
|
||||
if (axis_aresetn == 1'b0) begin
|
||||
mem_is_full <= 1'b0;
|
||||
end else begin
|
||||
if ((wr_addr == 1'b1) && (s_axis_valid == 1'b1)) begin
|
||||
mem_is_full <= 1'b1;
|
||||
end else begin
|
||||
mem_is_full <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// reorder the interleaved data
|
||||
assign m_axis_valid = mem_is_full;
|
||||
for (i=0; i<32; i=i+1) begin
|
||||
assign m_axis_data[ i] = axis_data_int[2*i+1];
|
||||
assign m_axis_data[32+i] = axis_data_int[2*i];
|
||||
end
|
||||
|
||||
end else if (NUM_OF_LANES == 2) begin : g_reorder_2_lanes
|
||||
|
||||
assign m_axis_valid = s_axis_valid;
|
||||
assign m_axis_data = s_axis_data;
|
||||
|
||||
end else if (NUM_OF_LANES == 4) begin : g_reorder_4_lanes
|
||||
|
||||
assign m_axis_valid = s_axis_valid;
|
||||
for (i=0; i<16; i=i+1) begin
|
||||
// first channel
|
||||
assign m_axis_data[2*i ] = s_axis_data[32+i];
|
||||
assign m_axis_data[2*i+1] = s_axis_data[ i];
|
||||
// second channel
|
||||
assign m_axis_data[2*i+32] = s_axis_data[96+i];
|
||||
assign m_axis_data[2*i+33] = s_axis_data[64+i];
|
||||
end
|
||||
|
||||
end else if (NUM_OF_LANES == 8) begin : g_reorder_8_lanes
|
||||
|
||||
assign m_axis_valid = s_axis_valid;
|
||||
for (i=0; i<8; i=i+1) begin
|
||||
// first channel
|
||||
assign m_axis_data[4*i ] = s_axis_data[96+i];
|
||||
assign m_axis_data[4*i+1] = s_axis_data[64+i];
|
||||
assign m_axis_data[4*i+2] = s_axis_data[32+i];
|
||||
assign m_axis_data[4*i+3] = s_axis_data[ i];
|
||||
// second channel
|
||||
assign m_axis_data[4*i+32] = s_axis_data[224+i];
|
||||
assign m_axis_data[4*i+33] = s_axis_data[192+i];
|
||||
assign m_axis_data[4*i+34] = s_axis_data[160+i];
|
||||
assign m_axis_data[4*i+35] = s_axis_data[128+i];
|
||||
end
|
||||
|
||||
end else begin
|
||||
// WARNING: Invalid configuration, leave everybody in the air
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,399 @@
|
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
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<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="e752d664dfd2410e84c9f4ba2321dd08"/>
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<Option Name="Part" Val="xc7vx485tffg1157-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
|
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorVersionXsim" Val="2023.2"/>
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||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
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|
||||
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|
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<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
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||||
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|
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|
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
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<Option Name="BoardPart" Val=""/>
|
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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||||
<Option Name="IPCachePermission" Val="read"/>
|
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<Option Name="IPCachePermission" Val="write"/>
|
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="EnableResourceEstimation" Val="FALSE"/>
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<Option Name="SimCompileState" Val="TRUE"/>
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
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<Option Name="WTXSimLaunchSim" Val="0"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/spi_axis_reorder.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="spi_axis_reorder"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,37 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create spi_axis_reorder
|
||||
adi_ip_files spi_axis_reorder [list \
|
||||
"spi_axis_reorder.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite spi_axis_reorder
|
||||
# Remove all inferred interfaces
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
|
||||
# Interface definitions
|
||||
|
||||
adi_add_bus "s_axis" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"s_axis_ready" "TREADY"} \
|
||||
{"s_axis_valid" "TVALID"} \
|
||||
{"s_axis_data" "TDATA"}]
|
||||
|
||||
adi_add_bus "m_axis" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"m_axis_ready" "TREADY"} \
|
||||
{"m_axis_valid" "TVALID"} \
|
||||
{"m_axis_data" "TDATA"}]
|
||||
|
||||
adi_add_bus_clock "axis_aclk" "s_axis:m_axis" "axis_aresetn"
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "NUM_OF_LANES" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } {
|
||||
# Procedure called to update NUM_OF_LANES when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } {
|
||||
# Procedure called to validate NUM_OF_LANES
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_LANES { MODELPARAM_VALUE.NUM_OF_LANES PARAM_VALUE.NUM_OF_LANES } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_LANES}] ${MODELPARAM_VALUE.NUM_OF_LANES}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
####################################################################################
|
||||
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
|
||||
### SPDX short identifier: BSD-1-Clause
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := spi_engine_execution
|
||||
|
||||
GENERIC_DEPS += spi_engine_execution.v
|
||||
|
||||
XILINX_DEPS += spi_engine_execution_constr.ttcl
|
||||
XILINX_DEPS += spi_engine_execution_ip.tcl
|
||||
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_master.xml
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml
|
||||
|
||||
INTEL_DEPS += spi_engine_execution_hw.tcl
|
||||
|
||||
include ../../scripts/library.mk
|
||||
@@ -0,0 +1,810 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>spi_engine_execution</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_clock</spirit:name>
|
||||
<spirit:displayName>ctrl_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_BUSIF">ctrl</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_reset</spirit:name>
|
||||
<spirit:displayName>ctrl_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SCLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_T</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_t</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>THREE_WIRE</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>three_wire</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CS</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cs</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_reset</spirit:name>
|
||||
<spirit:displayName>spi_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_execution</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>4f3438ce</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_execution</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>4f3438ce</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>3d941b35</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>active</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>echo_sclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.echo_sclk" xilinx:dependency="ECHO_SCLK">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_t</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cs</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CS')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>three_wire</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Num Of Cs</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_CS">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default Spi Cfg</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_SPI_CFG">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default Clk Div</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_CLK_DIV">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Num Of Sdi</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>Sdo Default</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDO_DEFAULT" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>ECHO_SCLK</spirit:name>
|
||||
<spirit:displayName>Echo Sclk</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ECHO_SCLK">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Sdi Delay</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_b71134be</spirit:name>
|
||||
<spirit:enumeration>"0"</spirit:enumeration>
|
||||
<spirit:enumeration>"1"</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_dd9ee503</spirit:name>
|
||||
<spirit:enumeration>0</spirit:enumeration>
|
||||
<spirit:enumeration>1</spirit:enumeration>
|
||||
<spirit:enumeration>2</spirit:enumeration>
|
||||
<spirit:enumeration>3</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>spi_engine_execution_constr.ttcl</spirit:name>
|
||||
<spirit:userFileType>ttcl</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_4f3438ce</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/spi_engine_execution_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_b2ce64e5</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>spi_engine_execution_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Number of CSN lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_CS" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default SPI mode</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_SPI_CFG" spirit:choiceRef="choice_list_dd9ee503">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default SCLK divider</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_CLK_DIV" spirit:minimum="0" spirit:maximum="255" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Parallel data width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="8" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Number of MISO</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_SDI" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>MOSI default level</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SDO_DEFAULT" spirit:choiceRef="choice_list_b71134be" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ECHO_SCLK</spirit:name>
|
||||
<spirit:displayName>Echoed SCLK</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ECHO_SCLK">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Delay MISO latching</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">spi_engine_execution_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>spi_engine_execution_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-14T03:52:49Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b4974010"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c2e40dde"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0dd4e337"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="0194bdcd"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,614 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_execution #(
|
||||
|
||||
parameter NUM_OF_CS = 1,
|
||||
parameter DEFAULT_SPI_CFG = 0,
|
||||
parameter DEFAULT_CLK_DIV = 0,
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1,
|
||||
parameter [0:0] SDO_DEFAULT = 1'b0,
|
||||
parameter ECHO_SCLK = 0,
|
||||
parameter [1:0] SDI_DELAY = 2'b00
|
||||
) (
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
output reg active,
|
||||
|
||||
output cmd_ready,
|
||||
input cmd_valid,
|
||||
input [15:0] cmd,
|
||||
|
||||
input sdo_data_valid,
|
||||
output reg sdo_data_ready,
|
||||
input [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
input sdi_data_ready,
|
||||
output reg sdi_data_valid,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data,
|
||||
|
||||
input sync_ready,
|
||||
output reg sync_valid,
|
||||
output [7:0] sync,
|
||||
|
||||
input echo_sclk,
|
||||
output reg sclk,
|
||||
output reg sdo,
|
||||
output reg sdo_t,
|
||||
input [NUM_OF_SDI-1:0] sdi,
|
||||
output reg [NUM_OF_CS-1:0] cs,
|
||||
output reg three_wire
|
||||
);
|
||||
|
||||
localparam CMD_TRANSFER = 2'b00;
|
||||
localparam CMD_CHIPSELECT = 2'b01;
|
||||
localparam CMD_WRITE = 2'b10;
|
||||
localparam CMD_MISC = 2'b11;
|
||||
|
||||
localparam MISC_SYNC = 1'b0;
|
||||
localparam MISC_SLEEP = 1'b1;
|
||||
|
||||
localparam REG_CLK_DIV = 2'b00;
|
||||
localparam REG_CONFIG = 2'b01;
|
||||
localparam REG_WORD_LENGTH = 2'b10;
|
||||
|
||||
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
|
||||
DATA_WIDTH > 8 ? 4 : 3;
|
||||
|
||||
localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1);
|
||||
localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1};
|
||||
|
||||
reg sclk_int = 1'b0;
|
||||
wire sdo_int_s;
|
||||
reg sdo_t_int = 1'b0;
|
||||
|
||||
reg idle;
|
||||
|
||||
reg [7:0] clk_div_counter = 'h00;
|
||||
reg [7:0] clk_div_counter_next = 'h00;
|
||||
reg clk_div_last;
|
||||
|
||||
reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
|
||||
|
||||
wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
|
||||
wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
|
||||
wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
|
||||
wire ntx_rx = counter[0];
|
||||
|
||||
reg trigger = 1'b0;
|
||||
reg trigger_next = 1'b0;
|
||||
reg wait_for_io = 1'b0;
|
||||
reg transfer_active = 1'b0;
|
||||
|
||||
wire last_bit;
|
||||
wire first_bit;
|
||||
reg last_transfer;
|
||||
reg [7:0] word_length = DATA_WIDTH;
|
||||
reg [7:0] left_aligned = 8'b0;
|
||||
wire end_of_word;
|
||||
|
||||
reg [7:0] sdi_counter = 8'b0;
|
||||
|
||||
assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length));
|
||||
|
||||
reg [15:0] cmd_d1;
|
||||
|
||||
reg cpha = DEFAULT_SPI_CFG[0];
|
||||
reg cpol = DEFAULT_SPI_CFG[1];
|
||||
reg [7:0] clk_div = DEFAULT_CLK_DIV;
|
||||
|
||||
reg sdo_enabled = 1'b0;
|
||||
reg sdi_enabled = 1'b0;
|
||||
|
||||
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
|
||||
|
||||
reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
|
||||
|
||||
wire [1:0] inst = cmd[13:12];
|
||||
wire [1:0] inst_d1 = cmd_d1[13:12];
|
||||
|
||||
wire exec_cmd = cmd_ready && cmd_valid;
|
||||
wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
|
||||
|
||||
wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
|
||||
wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
|
||||
wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
|
||||
wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
|
||||
|
||||
wire trigger_tx;
|
||||
wire trigger_rx;
|
||||
|
||||
wire sleep_counter_compare;
|
||||
wire cs_sleep_counter_compare;
|
||||
wire cs_sleep_early_exit;
|
||||
reg cs_sleep_repeat;
|
||||
|
||||
wire io_ready1;
|
||||
wire io_ready2;
|
||||
wire trigger_rx_s;
|
||||
|
||||
wire last_sdi_bit;
|
||||
wire end_of_sdi_latch;
|
||||
|
||||
(* direct_enable = "yes" *) wire cs_gen;
|
||||
|
||||
assign cs_gen = inst_d1 == CMD_CHIPSELECT
|
||||
&& ((cs_sleep_counter_compare == 1'b1) || cs_sleep_early_exit)
|
||||
&& (cs_sleep_repeat == 1'b0)
|
||||
&& (idle == 1'b0);
|
||||
assign cmd_ready = idle;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (exec_transfer_cmd) begin
|
||||
sdo_enabled <= cmd[8];
|
||||
sdi_enabled <= cmd[9];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cmd_ready & cmd_valid)
|
||||
cmd_d1 <= cmd;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
active <= 1'b0;
|
||||
end else begin
|
||||
if (exec_cmd == 1'b1)
|
||||
active <= 1'b1;
|
||||
else if (sync_ready == 1'b1 && sync_valid == 1'b1)
|
||||
active <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the interface configurations from the 'Configuration Write'
|
||||
// instruction
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cpha <= DEFAULT_SPI_CFG[0];
|
||||
cpol <= DEFAULT_SPI_CFG[1];
|
||||
three_wire <= DEFAULT_SPI_CFG[2];
|
||||
clk_div <= DEFAULT_CLK_DIV;
|
||||
word_length <= DATA_WIDTH;
|
||||
left_aligned <= 8'b0;
|
||||
end else if (exec_write_cmd == 1'b1) begin
|
||||
if (cmd[9:8] == REG_CONFIG) begin
|
||||
cpha <= cmd[0];
|
||||
cpol <= cmd[1];
|
||||
three_wire <= cmd[2];
|
||||
end else if (cmd[9:8] == REG_CLK_DIV) begin
|
||||
clk_div <= cmd[7:0];
|
||||
end else if (cmd[9:8] == REG_WORD_LENGTH) begin
|
||||
// the max value of this reg must be DATA_WIDTH
|
||||
word_length <= cmd[7:0];
|
||||
left_aligned <= DATA_WIDTH - cmd[7:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
|
||||
clk_div_counter == 'h01) || clk_div == 'h00)
|
||||
clk_div_last <= 1'b1;
|
||||
else
|
||||
clk_div_last <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
|
||||
clk_div_counter <= clk_div;
|
||||
trigger <= 1'b1;
|
||||
end else begin
|
||||
clk_div_counter <= clk_div_counter - 1'b1;
|
||||
trigger <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
|
||||
assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
|
||||
|
||||
assign sleep_counter_compare = sleep_counter == cmd_d1[7:0];
|
||||
assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8];
|
||||
assign cs_sleep_early_exit = (cmd_d1[9:8] == 2'b00);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs_sleep_repeat <= 1'b0;
|
||||
end else begin
|
||||
if (idle) begin
|
||||
cs_sleep_repeat <= 1'b0;
|
||||
end else if (cs_sleep_counter_compare && (inst_d1 == CMD_CHIPSELECT)) begin
|
||||
cs_sleep_repeat <= !cs_sleep_repeat;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1 || (cs_sleep_counter_compare && !cs_sleep_repeat && inst_d1 == CMD_CHIPSELECT)) begin
|
||||
counter <= 'h00;
|
||||
end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin
|
||||
if (bit_counter == word_length) begin
|
||||
counter <= (counter & BIT_COUNTER_CLEAR) + (transfer_active ? 'h1 : (2**BIT_COUNTER_WIDTH)) + BIT_COUNTER_CARRY;
|
||||
end else begin
|
||||
counter <= counter + (transfer_active ? 'h1 : (2**BIT_COUNTER_WIDTH));
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
idle <= 1'b1;
|
||||
end else begin
|
||||
if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
|
||||
idle <= 1'b0;
|
||||
end else begin
|
||||
case (inst_d1)
|
||||
CMD_TRANSFER: begin
|
||||
if (transfer_active == 1'b0 && wait_for_io == 1'b0 && end_of_sdi_latch == 1'b1)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_CHIPSELECT: begin
|
||||
if ((cs_sleep_counter_compare && cs_sleep_repeat) || cs_sleep_early_exit)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
CMD_MISC: begin
|
||||
case (cmd_d1[8])
|
||||
MISC_SLEEP: begin
|
||||
if (sleep_counter_compare)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
MISC_SYNC: begin
|
||||
if (sync_ready)
|
||||
idle <= 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
cs <= 'hff;
|
||||
end else if (cs_gen) begin
|
||||
cs <= cmd_d1[NUM_OF_CS-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sync_valid <= 1'b0;
|
||||
end else begin
|
||||
if (exec_sync_cmd == 1'b1) begin
|
||||
sync_valid <= 1'b1;
|
||||
end else if (sync_ready == 1'b1) begin
|
||||
sync_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sync = cmd_d1[7:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdo_data_ready <= 1'b0;
|
||||
else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && transfer_active == 1'b1)
|
||||
sdo_data_ready <= 1'b1;
|
||||
else if (sdo_data_valid == 1'b1)
|
||||
sdo_data_ready <= 1'b0;
|
||||
end
|
||||
|
||||
assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
|
||||
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
last_transfer <= 1'b0;
|
||||
end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
|
||||
if (transfer_counter == cmd_d1[7:0])
|
||||
last_transfer <= 1'b1;
|
||||
else
|
||||
last_transfer <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
transfer_active <= 1'b0;
|
||||
wait_for_io <= 1'b0;
|
||||
end else begin
|
||||
if (exec_transfer_cmd == 1'b1) begin
|
||||
wait_for_io <= 1'b1;
|
||||
transfer_active <= 1'b0;
|
||||
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
|
||||
wait_for_io <= 1'b0;
|
||||
if (last_transfer == 1'b0)
|
||||
transfer_active <= 1'b1;
|
||||
else
|
||||
transfer_active <= 1'b0;
|
||||
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
|
||||
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
|
||||
transfer_active <= 1'b0;
|
||||
if (io_ready2 == 1'b0)
|
||||
wait_for_io <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
|
||||
begin
|
||||
sdo_t_int <= ~sdo_enabled;
|
||||
end else begin
|
||||
sdo_t_int <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Load the SDO parallel data into the SDO shift register. In case of a custom
|
||||
// data width, additional bit shifting must done at load.
|
||||
always @(posedge clk) begin
|
||||
if ((inst_d1 == CMD_TRANSFER) && (!sdo_enabled)) begin
|
||||
data_sdo_shift <= {DATA_WIDTH{SDO_DEFAULT}};
|
||||
end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
|
||||
if (first_bit == 1'b1)
|
||||
data_sdo_shift <= sdo_data << left_aligned;
|
||||
else
|
||||
data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
|
||||
end
|
||||
end
|
||||
|
||||
assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
|
||||
|
||||
// In case of an interface with high clock rate (SCLK > 50MHz), the latch of
|
||||
// the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle.
|
||||
// Taking the fact that in high SCLK frequencies the pre-scaler most likely will
|
||||
// be set to 0, to reduce the core clock's speed, this delay will mean that SDI will
|
||||
// be latched at one of the next consecutive SCLK edge.
|
||||
|
||||
always @(posedge clk) begin
|
||||
trigger_rx_d <= {trigger_rx_d, trigger_rx};
|
||||
end
|
||||
|
||||
assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
|
||||
|
||||
// Load the serial data into SDI shift register(s), then link it to the output
|
||||
// register of the module
|
||||
// NOTE: ECHO_SCLK mode can be used when the SCLK line is looped back to the FPGA
|
||||
// through an other level shifter, in order to remove the round-trip timing delays
|
||||
// introduced by the level shifters. This can improve the timing significantly
|
||||
// on higher SCLK rates. Devices like ad4630 have an echod SCLK, which can be
|
||||
// used to latch the MISO lines, improving the overall timing margin of the
|
||||
// interface.
|
||||
|
||||
wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
|
||||
genvar i;
|
||||
|
||||
// NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point
|
||||
generate
|
||||
if (ECHO_SCLK == 1) begin : g_echo_sclk_miso_latch
|
||||
|
||||
reg [7:0] sdi_counter_d = 8'b0;
|
||||
reg [7:0] sdi_transfer_counter = 8'b0;
|
||||
reg [7:0] num_of_transfers = 8'b0;
|
||||
reg [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data_latch = {(NUM_OF_SDI * DATA_WIDTH){1'b0}};
|
||||
|
||||
if ((DEFAULT_SPI_CFG[1:0] == 2'b01) || (DEFAULT_SPI_CFG[1:0] == 2'b10)) begin : g_echo_miso_nshift_reg
|
||||
|
||||
// MISO shift register runs on negative echo_sclk
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
|
||||
always @(negedge echo_sclk or posedge cs_active_s) begin
|
||||
if (cs_active_s) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
end
|
||||
|
||||
// intended LATCH
|
||||
always @(negedge echo_sclk) begin
|
||||
if (last_sdi_bit)
|
||||
sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @(posedge echo_sclk or posedge cs_active_s) begin
|
||||
if (cs_active_s == 1'b1) begin
|
||||
sdi_counter <= 8'b0;
|
||||
sdi_counter_d <= 8'b0;
|
||||
end else begin
|
||||
sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
|
||||
sdi_counter_d <= sdi_counter;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin : g_echo_miso_pshift_reg
|
||||
|
||||
// MISO shift register runs on positive echo_sclk
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
always @(posedge echo_sclk or posedge cs_active_s) begin
|
||||
if (cs_active_s) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
end
|
||||
// intended LATCH
|
||||
always @(posedge echo_sclk) begin
|
||||
if (last_sdi_bit)
|
||||
sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= data_sdi_shift;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge echo_sclk or posedge cs_active_s) begin
|
||||
if (cs_active_s == 1'b1) begin
|
||||
sdi_counter <= 8'b0;
|
||||
sdi_counter_d <= 8'b0;
|
||||
end else begin
|
||||
sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
|
||||
sdi_counter_d <= sdi_counter;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign sdi_data = sdi_data_latch;
|
||||
assign last_sdi_bit = (sdi_counter == 0) && (sdi_counter_d == word_length-1);
|
||||
|
||||
// sdi_data_valid is synchronous to SPI clock, so synchronize the
|
||||
// last_sdi_bit to SPI clock
|
||||
|
||||
reg [3:0] last_sdi_bit_m = 4'b0;
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
last_sdi_bit_m <= 4'b0;
|
||||
end else begin
|
||||
last_sdi_bit_m <= {last_sdi_bit_m, last_sdi_bit};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
sdi_data_valid <= 1'b0;
|
||||
end else if (sdi_enabled == 1'b1 &&
|
||||
last_sdi_bit_m[3] == 1'b0 &&
|
||||
last_sdi_bit_m[2] == 1'b1) begin
|
||||
sdi_data_valid <= 1'b1;
|
||||
end else if (sdi_data_ready == 1'b1) begin
|
||||
sdi_data_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
num_of_transfers <= 8'b0;
|
||||
end else begin
|
||||
if (cmd_d1[15:12] == 4'b0) begin
|
||||
num_of_transfers <= cmd_d1[7:0] + 1'b1; // cmd_d1 contains the NUM_OF_TRANSFERS - 1
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
sdi_transfer_counter <= 0;
|
||||
end else if (last_sdi_bit_m[2] == 1'b0 &&
|
||||
last_sdi_bit_m[1] == 1'b1) begin
|
||||
sdi_transfer_counter <= sdi_transfer_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign end_of_sdi_latch = last_sdi_bit_m[2] & (sdi_transfer_counter == num_of_transfers);
|
||||
|
||||
end /* g_echo_sclk_miso_latch */
|
||||
else
|
||||
begin : g_sclk_miso_latch
|
||||
|
||||
assign end_of_sdi_latch = 1'b1;
|
||||
|
||||
for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_sdi_shift;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs_active_s) begin
|
||||
data_sdi_shift <= 0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
data_sdi_shift <= {data_sdi_shift, sdi[i]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
|
||||
|
||||
end
|
||||
|
||||
assign last_sdi_bit = (sdi_counter == word_length-1);
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
sdi_counter <= 8'b0;
|
||||
end else begin
|
||||
if (trigger_rx_s == 1'b1) begin
|
||||
sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0)
|
||||
sdi_data_valid <= 1'b0;
|
||||
else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
|
||||
sdi_data_valid <= 1'b1;
|
||||
else if (sdi_data_ready == 1'b1)
|
||||
sdi_data_valid <= 1'b0;
|
||||
end
|
||||
|
||||
end /* g_sclk_miso_latch */
|
||||
endgenerate
|
||||
|
||||
// end_of_word will signal the end of a transaction, pushing the command
|
||||
// stream execution to the next command. end_of_word in normal mode can be
|
||||
// generated using the global bit_counter
|
||||
assign last_bit = bit_counter == word_length - 1;
|
||||
assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (transfer_active == 1'b1) begin
|
||||
sclk_int <= cpol ^ cpha ^ ntx_rx;
|
||||
end else begin
|
||||
sclk_int <= cpol;
|
||||
end
|
||||
end
|
||||
|
||||
// Additional register stage to improve timing
|
||||
always @(posedge clk) begin
|
||||
sclk <= sclk_int;
|
||||
sdo <= sdo_int_s;
|
||||
sdo_t <= sdo_t_int;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,400 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_execution/spi_engine_execution.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="1f06667fc09742279c2aaecc7fa6d70e"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/spi_engine_execution.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/spi_engine_execution_constr.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="spi_engine_execution"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,35 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
<: set echo_sclk [getBooleanValue "ECHO_SCLK"] :>
|
||||
|
||||
# Relax the timing between the SDI shift register and DMA. The shift register
|
||||
# runs at negative edge of echoSCLK and the DMA runs at spi_clk. Registers
|
||||
# will have valid data at worst case (fastest rate) in every 8 echoSCLK cycle.
|
||||
|
||||
set_multicycle_path -setup -from [get_pins -hier -filter {name=~*data_sdi_shift_reg[*]/C}] 8
|
||||
set_multicycle_path -hold -from [get_pins -hier -filter {name=~*data_sdi_shift_reg[*]/C}] 7
|
||||
|
||||
# word_length is updated before transfer, never changes during transfer, therefor
|
||||
# it's safe to define a false path between word_length and sdi_counter
|
||||
set_false_path -from [get_cells -hierarchical -filter {NAME=~*word_length_reg[*]}] -to [get_cells -hierarchical -filter {NAME=~*sdi_counter_reg[*]}]
|
||||
|
||||
<: if { $echo_sclk } { :>
|
||||
|
||||
## SDI counter runs on echo_SCLK but sdi_data_valid is generated with spi_clk which
|
||||
# is synchronous to SCLK. The last_sdi_bit should be transferred into spi_clk domain.
|
||||
set_property ASYNC_REG true [get_cells -hier {*last_sdi_bit_m_reg[0]}]
|
||||
set_property ASYNC_REG true [get_cells -hier {*last_sdi_bit_m_reg[1]}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *last_sdi_bit_m_reg[0]* && IS_SEQUENTIAL}]
|
||||
|
||||
# SDI shift registers are reset asynchronously after a negative edge of CSN - define the reset line as a false path
|
||||
set_false_path -to [get_pins -hierarchical -filter {NAME=~*g_echo_sclk_miso_latch.*.data_sdi_shift_reg[*]/CLR}]
|
||||
|
||||
<: } :>
|
||||
@@ -0,0 +1,90 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create spi_engine_execution {SPI Engine Execution}
|
||||
set_module_property ELABORATION_CALLBACK p_elaboration
|
||||
ad_ip_files spi_engine_execution [list\
|
||||
spi_engine_execution.v]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter NUM_OF_CS INTEGER 1
|
||||
ad_ip_parameter DEFAULT_SPI_CFG INTEGER 0
|
||||
ad_ip_parameter DEFAULT_CLK_DIV INTEGER 0
|
||||
ad_ip_parameter DATA_WIDTH INTEGER 8
|
||||
ad_ip_parameter NUM_OF_SDI INTEGER 1
|
||||
ad_ip_parameter SDI_DELAY INTEGER 0
|
||||
ad_ip_parameter SDO_DEFAULT INTEGER 0
|
||||
|
||||
proc p_elaboration {} {
|
||||
|
||||
set data_width [get_parameter_value DATA_WIDTH]
|
||||
set num_of_sdi [get_parameter_value NUM_OF_SDI]
|
||||
set num_of_cs [get_parameter_value NUM_OF_CS]
|
||||
|
||||
# clock and reset interface
|
||||
|
||||
ad_interface clock clk input 1
|
||||
ad_interface reset resetn input 1 if_clk
|
||||
|
||||
ad_interface signal active output 1
|
||||
|
||||
# command interface
|
||||
|
||||
add_interface cmd axi4stream end
|
||||
add_interface_port cmd cmd_ready tready output 1
|
||||
add_interface_port cmd cmd_valid tvalid input 1
|
||||
add_interface_port cmd cmd tdata input 16
|
||||
|
||||
set_interface_property cmd associatedClock if_clk
|
||||
set_interface_property cmd associatedReset if_resetn
|
||||
|
||||
# SDO data interface
|
||||
|
||||
add_interface sdo_data axi4stream end
|
||||
add_interface_port sdo_data sdo_data_ready tready output 1
|
||||
add_interface_port sdo_data sdo_data_valid tvalid input 1
|
||||
add_interface_port sdo_data sdo_data tdata input $data_width
|
||||
|
||||
set_interface_property sdo_data associatedClock if_clk
|
||||
set_interface_property sdo_data associatedReset if_resetn
|
||||
|
||||
# SDI data interface
|
||||
|
||||
add_interface sdi_data axi4stream start
|
||||
add_interface_port sdi_data sdi_data_ready tready input 1
|
||||
add_interface_port sdi_data sdi_data_valid tvalid output 1
|
||||
add_interface_port sdi_data sdi_data tdata output [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property sdi_data associatedClock if_clk
|
||||
set_interface_property sdi_data associatedReset if_resetn
|
||||
|
||||
# SYNC data interface
|
||||
|
||||
add_interface sync axi4stream start
|
||||
add_interface_port sync sync_valid tvalid output 1
|
||||
add_interface_port sync sync_ready tready input 1
|
||||
add_interface_port sync sync tdata output 8
|
||||
|
||||
set_interface_property sync associatedClock if_clk
|
||||
set_interface_property sync associatedReset if_resetn
|
||||
|
||||
# physical SPI interface
|
||||
|
||||
ad_interface clock sclk output 1
|
||||
|
||||
ad_interface signal sdo output 1
|
||||
ad_interface signal sdo_t output 1
|
||||
ad_interface signal sdi input $num_of_sdi
|
||||
|
||||
ad_interface signal cs output 1
|
||||
ad_interface signal three_wire output 1
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,215 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create spi_engine_execution
|
||||
adi_ip_files spi_engine_execution [list \
|
||||
"spi_engine_execution_constr.ttcl" \
|
||||
"spi_engine_execution.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite spi_engine_execution
|
||||
adi_ip_ttcl spi_engine_execution "spi_engine_execution_constr.ttcl"
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine} [ipx::current_core]
|
||||
|
||||
# Remove all inferred interfaces
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "ctrl" "slave" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{
|
||||
{"cmd_ready" "CMD_READY"} \
|
||||
{"cmd_valid" "CMD_VALID"} \
|
||||
{"cmd" "CMD_DATA"} \
|
||||
{"sdo_data_ready" "SDO_READY"} \
|
||||
{"sdo_data_valid" "SDO_VALID"} \
|
||||
{"sdo_data" "SDO_DATA"} \
|
||||
{"sdi_data_ready" "SDI_READY"} \
|
||||
{"sdi_data_valid" "SDI_VALID"} \
|
||||
{"sdi_data" "SDI_DATA"} \
|
||||
{"sync_ready" "SYNC_READY"} \
|
||||
{"sync_valid" "SYNC_VALID"} \
|
||||
{"sync" "SYNC_DATA"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "ctrl" "resetn"
|
||||
|
||||
adi_add_bus "spi" "master" \
|
||||
"analog.com:interface:spi_master_rtl:1.0" \
|
||||
"analog.com:interface:spi_master:1.0" \
|
||||
{
|
||||
{"sclk" "SCLK"} \
|
||||
{"sdi" "SDI"} \
|
||||
{"sdo" "SDO"} \
|
||||
{"sdo_t" "SDO_T"} \
|
||||
{"three_wire" "THREE_WIRE"} \
|
||||
{"cs" "CS"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "spi" "resetn"
|
||||
|
||||
## Parameter validations
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
## DATA_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "8" \
|
||||
"value_validation_range_maximum" "32" \
|
||||
] \
|
||||
[ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
|
||||
## NUM_OF_CS
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_CS -of_objects $cc]
|
||||
|
||||
## NUM_OF_SDI
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
|
||||
## DEFAULT_SPI_CFG
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "list" \
|
||||
"value_validation_list" "0 1 2 3" \
|
||||
] \
|
||||
[ipx::get_user_parameters DEFAULT_SPI_CFG -of_objects $cc]
|
||||
|
||||
## DEFAULT_CLK_DIV
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "list" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "255" \
|
||||
] \
|
||||
[ipx::get_user_parameters DEFAULT_CLK_DIV -of_objects $cc]
|
||||
|
||||
## SDO_DEFAULT
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "list" \
|
||||
"value_validation_list" "0 1" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDO_DEFAULT -of_objects $cc]
|
||||
|
||||
## SDI_DELAY
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDI_DELAY -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters SDI_DELAY -of_objects $cc]
|
||||
|
||||
## ECHO SCLK
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_user_parameters ECHO_SCLK -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters ECHO_SCLK -of_objects $cc]
|
||||
|
||||
## echo_sclk should be active only when ECHO_SCLK is set
|
||||
adi_set_ports_dependency echo_sclk ECHO_SCLK 0
|
||||
|
||||
## Customize IP Layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create general configuration page
|
||||
ipgui::add_page -name {SPI Engine execution} -component [ipx::current_core] -display_name {AXI SPI Engine execution}
|
||||
set page0 [ipgui::get_pagespec -name "SPI Engine execution" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration" ]
|
||||
|
||||
ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Parallel data width" \
|
||||
"tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_CS" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of CSN lines" \
|
||||
"tooltip" "\[NUM_OF_CS\] Define the number of chip select lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_CS" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO lines" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
set spi_config_group [ipgui::add_group -name "SPI Configuration" -component $cc \
|
||||
-parent $page0 -display_name "SPI Configuration" ]
|
||||
|
||||
ipgui::add_param -name "DEFAULT_SPI_CFG" -component $cc -parent $spi_config_group
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "Default SPI mode" \
|
||||
"tooltip" "\[DEFAULT_SPI_CFG\] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA"
|
||||
] [ipgui::get_guiparamspec -name "DEFAULT_SPI_CFG" -component $cc]
|
||||
|
||||
ipgui::add_param -name "DEFAULT_CLK_DIV" -component $cc -parent $spi_config_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Default SCLK divider" \
|
||||
"tooltip" "\[DEFAULT_CLK_DIV\] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1"
|
||||
] [ipgui::get_guiparamspec -name "DEFAULT_CLK_DIV" -component $cc]
|
||||
|
||||
set mosi_miso_config_group [ipgui::add_group -name "MOSI/MISO Configuration" -component $cc \
|
||||
-parent $page0 -display_name "MOSI/MISO Configuration" ]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $mosi_miso_config_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines"
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDI_DELAY" -component $cc -parent $mosi_miso_config_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Delay MISO latching" \
|
||||
"tooltip" "\[SDI_DELAY\] Delay the MISO latching to the next consecutive SCLK edge"
|
||||
] [ipgui::get_guiparamspec -name "SDI_DELAY" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDO_DEFAULT" -component $cc -parent $mosi_miso_config_group
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "MOSI default level" \
|
||||
"tooltip" "\[SDO_DEFAULT\] Define the default voltage level on MOSI"
|
||||
] [ipgui::get_guiparamspec -name "SDO_DEFAULT" -component $cc]
|
||||
|
||||
set custom_clocking_group [ipgui::add_group -name "Custom clocking options" -component $cc \
|
||||
-parent $page0 -display_name "Custom clocking options" ]
|
||||
|
||||
ipgui::add_param -name "ECHO_SCLK" -component $cc -parent $custom_clocking_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Echoed SCLK" \
|
||||
"tooltip" "\[ECHO_SCLK\] Activate echo SCLK option (hardware support required)"
|
||||
] [ipgui::get_guiparamspec -name "ECHO_SCLK" -component $cc]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files $cc
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,150 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_execution [ipgui::add_page $IPINST -name "SPI Engine execution" -display_name {AXI SPI Engine execution}]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_execution}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_CS [ipgui::add_param $IPINST -name "NUM_OF_CS" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_CS] Define the number of chip select lines} ${NUM_OF_CS}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
|
||||
#Adding Group
|
||||
set SPI_Configuration [ipgui::add_group $IPINST -name "SPI Configuration" -parent ${SPI_Engine_execution}]
|
||||
set DEFAULT_SPI_CFG [ipgui::add_param $IPINST -name "DEFAULT_SPI_CFG" -parent ${SPI_Configuration} -widget comboBox]
|
||||
set_property tooltip {[DEFAULT_SPI_CFG] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA} ${DEFAULT_SPI_CFG}
|
||||
set DEFAULT_CLK_DIV [ipgui::add_param $IPINST -name "DEFAULT_CLK_DIV" -parent ${SPI_Configuration}]
|
||||
set_property tooltip {[DEFAULT_CLK_DIV] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1} ${DEFAULT_CLK_DIV}
|
||||
|
||||
#Adding Group
|
||||
set MOSI/MISO_Configuration [ipgui::add_group $IPINST -name "MOSI/MISO Configuration" -parent ${SPI_Engine_execution}]
|
||||
set SDI_DELAY [ipgui::add_param $IPINST -name "SDI_DELAY" -parent ${MOSI/MISO_Configuration}]
|
||||
set_property tooltip {[SDI_DELAY] Delay the MISO latching to the next consecutive SCLK edge} ${SDI_DELAY}
|
||||
set SDO_DEFAULT [ipgui::add_param $IPINST -name "SDO_DEFAULT" -parent ${MOSI/MISO_Configuration} -widget comboBox]
|
||||
set_property tooltip {[SDO_DEFAULT] Define the default voltage level on MOSI} ${SDO_DEFAULT}
|
||||
|
||||
#Adding Group
|
||||
set Custom_clocking_options [ipgui::add_group $IPINST -name "Custom clocking options" -parent ${SPI_Engine_execution}]
|
||||
set ECHO_SCLK [ipgui::add_param $IPINST -name "ECHO_SCLK" -parent ${Custom_clocking_options}]
|
||||
set_property tooltip {[ECHO_SCLK] Activate echo SCLK option (hardware support required)} ${ECHO_SCLK}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEFAULT_CLK_DIV { PARAM_VALUE.DEFAULT_CLK_DIV } {
|
||||
# Procedure called to update DEFAULT_CLK_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEFAULT_CLK_DIV { PARAM_VALUE.DEFAULT_CLK_DIV } {
|
||||
# Procedure called to validate DEFAULT_CLK_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEFAULT_SPI_CFG { PARAM_VALUE.DEFAULT_SPI_CFG } {
|
||||
# Procedure called to update DEFAULT_SPI_CFG when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEFAULT_SPI_CFG { PARAM_VALUE.DEFAULT_SPI_CFG } {
|
||||
# Procedure called to validate DEFAULT_SPI_CFG
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ECHO_SCLK { PARAM_VALUE.ECHO_SCLK } {
|
||||
# Procedure called to update ECHO_SCLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ECHO_SCLK { PARAM_VALUE.ECHO_SCLK } {
|
||||
# Procedure called to validate ECHO_SCLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } {
|
||||
# Procedure called to update NUM_OF_CS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } {
|
||||
# Procedure called to validate NUM_OF_CS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDI_DELAY { PARAM_VALUE.SDI_DELAY } {
|
||||
# Procedure called to update SDI_DELAY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDI_DELAY { PARAM_VALUE.SDI_DELAY } {
|
||||
# Procedure called to validate SDI_DELAY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_DEFAULT { PARAM_VALUE.SDO_DEFAULT } {
|
||||
# Procedure called to update SDO_DEFAULT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_DEFAULT { PARAM_VALUE.SDO_DEFAULT } {
|
||||
# Procedure called to validate SDO_DEFAULT
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_CS { MODELPARAM_VALUE.NUM_OF_CS PARAM_VALUE.NUM_OF_CS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CS}] ${MODELPARAM_VALUE.NUM_OF_CS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEFAULT_SPI_CFG { MODELPARAM_VALUE.DEFAULT_SPI_CFG PARAM_VALUE.DEFAULT_SPI_CFG } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEFAULT_SPI_CFG}] ${MODELPARAM_VALUE.DEFAULT_SPI_CFG}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEFAULT_CLK_DIV { MODELPARAM_VALUE.DEFAULT_CLK_DIV PARAM_VALUE.DEFAULT_CLK_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEFAULT_CLK_DIV}] ${MODELPARAM_VALUE.DEFAULT_CLK_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_DEFAULT { MODELPARAM_VALUE.SDO_DEFAULT PARAM_VALUE.SDO_DEFAULT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_DEFAULT}] ${MODELPARAM_VALUE.SDO_DEFAULT}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ECHO_SCLK { MODELPARAM_VALUE.ECHO_SCLK PARAM_VALUE.ECHO_SCLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ECHO_SCLK}] ${MODELPARAM_VALUE.ECHO_SCLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDI_DELAY { MODELPARAM_VALUE.SDI_DELAY PARAM_VALUE.SDI_DELAY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDI_DELAY}] ${MODELPARAM_VALUE.SDI_DELAY}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,18 @@
|
||||
####################################################################################
|
||||
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
|
||||
### SPDX short identifier: BSD-1-Clause
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := spi_engine_interconnect
|
||||
|
||||
GENERIC_DEPS += spi_engine_interconnect.v
|
||||
|
||||
XILINX_DEPS += spi_engine_interconnect_ip.tcl
|
||||
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
|
||||
|
||||
INTEL_DEPS += spi_engine_interconnect_hw.tcl
|
||||
|
||||
include ../../scripts/library.mk
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,144 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_interconnect #(
|
||||
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1
|
||||
) (
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
output m_cmd_valid,
|
||||
input m_cmd_ready,
|
||||
output [15:0] m_cmd_data,
|
||||
|
||||
output m_sdo_valid,
|
||||
input m_sdo_ready,
|
||||
output [(DATA_WIDTH-1):0] m_sdo_data,
|
||||
|
||||
input m_sdi_valid,
|
||||
output m_sdi_ready,
|
||||
input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
|
||||
|
||||
input m_sync_valid,
|
||||
output m_sync_ready,
|
||||
input [7:0] m_sync,
|
||||
|
||||
input s0_cmd_valid,
|
||||
output s0_cmd_ready,
|
||||
input [15:0] s0_cmd_data,
|
||||
|
||||
input s0_sdo_valid,
|
||||
output s0_sdo_ready,
|
||||
input [(DATA_WIDTH-1):0] s0_sdo_data,
|
||||
|
||||
output s0_sdi_valid,
|
||||
input s0_sdi_ready,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
|
||||
|
||||
output s0_sync_valid,
|
||||
input s0_sync_ready,
|
||||
output [7:0] s0_sync,
|
||||
|
||||
input s1_cmd_valid,
|
||||
output s1_cmd_ready,
|
||||
input [15:0] s1_cmd_data,
|
||||
|
||||
input s1_sdo_valid,
|
||||
output s1_sdo_ready,
|
||||
input [(DATA_WIDTH-1):0] s1_sdo_data,
|
||||
|
||||
output s1_sdi_valid,
|
||||
input s1_sdi_ready,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
|
||||
|
||||
output s1_sync_valid,
|
||||
input s1_sync_ready,
|
||||
output [7:0] s1_sync
|
||||
);
|
||||
|
||||
reg s_active = 1'b0;
|
||||
|
||||
reg idle = 1'b1;
|
||||
|
||||
`define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))
|
||||
|
||||
assign m_cmd_data = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data;
|
||||
assign m_cmd_valid = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid);
|
||||
assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0);
|
||||
assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready);
|
||||
|
||||
assign m_sdo_data = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data;
|
||||
assign m_sdo_valid = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid);
|
||||
assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0);
|
||||
assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready);
|
||||
|
||||
assign s0_sdi_data = m_sdi_data;
|
||||
assign s1_sdi_data = m_sdi_data;
|
||||
assign m_sdi_ready = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready);
|
||||
assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0);
|
||||
assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid);
|
||||
|
||||
assign s0_sync = m_sync;
|
||||
assign s1_sync = m_sync;
|
||||
assign m_sync_ready = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready);
|
||||
assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
|
||||
assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (idle == 1'b1) begin
|
||||
if (s0_cmd_valid)
|
||||
s_active <= 1'b0;
|
||||
else if (s1_cmd_valid)
|
||||
s_active <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (resetn == 1'b0) begin
|
||||
idle <= 1'b1;
|
||||
end else begin
|
||||
if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
|
||||
idle <= 1'b1;
|
||||
end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
|
||||
idle <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,399 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="d07593d6329248f7b3897d72eb22855e"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/spi_engine_interconnect.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="spi_engine_interconnect"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,150 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create spi_engine_interconnect {SPI Engine Interconnect} p_elaboration
|
||||
ad_ip_files spi_engine_interconnect [list\
|
||||
spi_engine_interconnect.v]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter DATA_WIDTH INTEGER 8
|
||||
ad_ip_parameter NUM_OF_SDI INTEGER 1
|
||||
|
||||
proc p_elaboration {} {
|
||||
|
||||
set data_width [get_parameter_value DATA_WIDTH]
|
||||
set num_of_sdi [get_parameter_value NUM_OF_SDI]
|
||||
|
||||
# clock and reset interface
|
||||
|
||||
ad_interface clock clk input 1
|
||||
ad_interface reset resetn input 1 if_clk
|
||||
|
||||
# command master interface
|
||||
|
||||
add_interface m_cmd axi4stream start
|
||||
add_interface_port m_cmd m_cmd_ready tready input 1
|
||||
add_interface_port m_cmd m_cmd_valid tvalid output 1
|
||||
add_interface_port m_cmd m_cmd_data tdata output 16
|
||||
|
||||
set_interface_property m_cmd associatedClock if_clk
|
||||
set_interface_property m_cmd associatedReset if_resetn
|
||||
|
||||
# SDO data master interface
|
||||
|
||||
add_interface m_sdo axi4stream start
|
||||
add_interface_port m_sdo m_sdo_ready tready input 1
|
||||
add_interface_port m_sdo m_sdo_valid tvalid output 1
|
||||
add_interface_port m_sdo m_sdo_data tdata output $data_width
|
||||
|
||||
set_interface_property m_sdo associatedClock if_clk
|
||||
set_interface_property m_sdo associatedReset if_resetn
|
||||
|
||||
# SDI data master interface
|
||||
|
||||
add_interface m_sdi axi4stream end
|
||||
add_interface_port m_sdi m_sdi_ready tready output 1
|
||||
add_interface_port m_sdi m_sdi_valid tvalid input 1
|
||||
add_interface_port m_sdi m_sdi_data tdata input [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property m_sdi associatedClock if_clk
|
||||
set_interface_property m_sdi associatedReset if_resetn
|
||||
|
||||
# SYNC master interface
|
||||
|
||||
add_interface m_sync axi4stream end
|
||||
add_interface_port m_sync m_sync_valid tvalid input 1
|
||||
add_interface_port m_sync m_sync_ready tready output 1
|
||||
add_interface_port m_sync m_sync tdata input 8
|
||||
|
||||
set_interface_property m_sync associatedClock if_clk
|
||||
set_interface_property m_sync associatedReset if_resetn
|
||||
|
||||
# command slave0 interface
|
||||
|
||||
add_interface s0_cmd axi4stream end
|
||||
add_interface_port s0_cmd s0_cmd_ready tready output 1
|
||||
add_interface_port s0_cmd s0_cmd_valid tvalid input 1
|
||||
add_interface_port s0_cmd s0_cmd_data tdata input 16
|
||||
|
||||
set_interface_property s0_cmd associatedClock if_clk
|
||||
set_interface_property s0_cmd associatedReset if_resetn
|
||||
|
||||
# SDO data slave0 interface
|
||||
|
||||
add_interface s0_sdo axi4stream end
|
||||
add_interface_port s0_sdo s0_sdo_ready tready output 1
|
||||
add_interface_port s0_sdo s0_sdo_valid tvalid input 1
|
||||
add_interface_port s0_sdo s0_sdo_data tdata input $data_width
|
||||
|
||||
set_interface_property s0_sdo associatedClock if_clk
|
||||
set_interface_property s0_sdo associatedReset if_resetn
|
||||
|
||||
# SDI data slave0 interface
|
||||
|
||||
add_interface s0_sdi axi4stream start
|
||||
add_interface_port s0_sdi s0_sdi_ready tready input 1
|
||||
add_interface_port s0_sdi s0_sdi_valid tvalid output 1
|
||||
add_interface_port s0_sdi s0_sdi_data tdata output [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property s0_sdi associatedClock if_clk
|
||||
set_interface_property s0_sdi associatedReset if_resetn
|
||||
|
||||
# SYNC slave0 interface
|
||||
|
||||
add_interface s0_sync axi4stream start
|
||||
add_interface_port s0_sync s0_sync_valid tvalid output 1
|
||||
add_interface_port s0_sync s0_sync_ready tready input 1
|
||||
add_interface_port s0_sync s0_sync tdata output 8
|
||||
|
||||
set_interface_property s0_sync associatedClock if_clk
|
||||
set_interface_property s0_sync associatedReset if_resetn
|
||||
|
||||
# command slave1 interface
|
||||
|
||||
add_interface s1_cmd axi4stream end
|
||||
add_interface_port s1_cmd s1_cmd_ready tready output 1
|
||||
add_interface_port s1_cmd s1_cmd_valid tvalid input 1
|
||||
add_interface_port s1_cmd s1_cmd_data tdata input 16
|
||||
|
||||
set_interface_property s1_cmd associatedClock if_clk
|
||||
set_interface_property s1_cmd associatedReset if_resetn
|
||||
|
||||
# SDO data slave1 interface
|
||||
|
||||
add_interface s1_sdo axi4stream end
|
||||
add_interface_port s1_sdo s1_sdo_ready tready output 1
|
||||
add_interface_port s1_sdo s1_sdo_valid tvalid input 1
|
||||
add_interface_port s1_sdo s1_sdo_data tdata input $data_width
|
||||
|
||||
set_interface_property s1_sdo associatedClock if_clk
|
||||
set_interface_property s1_sdo associatedReset if_resetn
|
||||
|
||||
# SDI data slave1 interface
|
||||
|
||||
add_interface s1_sdi axi4stream start
|
||||
add_interface_port s1_sdi s1_sdi_ready tready input 1
|
||||
add_interface_port s1_sdi s1_sdi_valid tvalid output 1
|
||||
add_interface_port s1_sdi s1_sdi_data tdata output [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property s1_sdi associatedClock if_clk
|
||||
set_interface_property s1_sdi associatedReset if_resetn
|
||||
|
||||
# SYNC slave1 interface
|
||||
|
||||
add_interface s1_sync axi4stream start
|
||||
add_interface_port s1_sync s1_sync_valid tvalid output 1
|
||||
add_interface_port s1_sync s1_sync_ready tready input 1
|
||||
add_interface_port s1_sync s1_sync tdata output 8
|
||||
|
||||
set_interface_property s1_sync associatedClock if_clk
|
||||
set_interface_property s1_sync associatedReset if_resetn
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,111 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create spi_engine_interconnect
|
||||
adi_ip_files spi_engine_interconnect [list \
|
||||
"spi_engine_interconnect.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite spi_engine_interconnect
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/interconnect} [ipx::current_core]
|
||||
|
||||
# Remove all inferred interfaces
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "m_ctrl" "master" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{ \
|
||||
{"m_cmd_ready" "CMD_READY"} \
|
||||
{"m_cmd_valid" "CMD_VALID"} \
|
||||
{"m_cmd_data" "CMD_DATA"} \
|
||||
{"m_sdo_ready" "SDO_READY"} \
|
||||
{"m_sdo_valid" "SDO_VALID"} \
|
||||
{"m_sdo_data" "SDO_DATA"} \
|
||||
{"m_sdi_ready" "SDI_READY"} \
|
||||
{"m_sdi_valid" "SDI_VALID"} \
|
||||
{"m_sdi_data" "SDI_DATA"} \
|
||||
{"m_sync_ready" "SYNC_READY"} \
|
||||
{"m_sync_valid" "SYNC_VALID"} \
|
||||
{"m_sync" "SYNC_DATA"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "m_ctrl" "resetn"
|
||||
|
||||
foreach prefix [list "s0" "s1"] {
|
||||
adi_add_bus [format "%s_ctrl" $prefix] "slave" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
[list \
|
||||
[list [format "%s_cmd_ready" $prefix] "CMD_READY"] \
|
||||
[list [format "%s_cmd_valid" $prefix] "CMD_VALID"] \
|
||||
[list [format "%s_cmd_data" $prefix] "CMD_DATA"] \
|
||||
[list [format "%s_sdo_ready" $prefix] "SDO_READY"] \
|
||||
[list [format "%s_sdo_valid" $prefix] "SDO_VALID"] \
|
||||
[list [format "%s_sdo_data" $prefix] "SDO_DATA"] \
|
||||
[list [format "%s_sdi_ready" $prefix] "SDI_READY"] \
|
||||
[list [format "%s_sdi_valid" $prefix] "SDI_VALID"] \
|
||||
[list [format "%s_sdi_data" $prefix] "SDI_DATA"] \
|
||||
[list [format "%s_sync_ready" $prefix] "SYNC_READY"] \
|
||||
[list [format "%s_sync_valid" $prefix] "SYNC_VALID"] \
|
||||
[list [format "%s_sync" $prefix] "SYNC_DATA"] \
|
||||
]
|
||||
adi_add_bus_clock "clk" [format "%s_ctrl" $prefix] "resetn"
|
||||
}
|
||||
|
||||
## Parameter validations
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
## DATA_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "8" \
|
||||
"value_validation_range_maximum" "256" \
|
||||
] \
|
||||
[ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
|
||||
## NUM_OF_SDI
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
|
||||
## Customize IP Layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create general configuration page
|
||||
ipgui::add_page -name {SPI Engine interconnect} -component [ipx::current_core] -display_name {SPI Engine interconnect}
|
||||
set page0 [ipgui::get_pagespec -name "SPI Engine interconnect" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration" ]
|
||||
|
||||
ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Parallel data width" \
|
||||
"tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO lines" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files $cc
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,45 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_interconnect [ipgui::add_page $IPINST -name "SPI Engine interconnect"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_interconnect}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,24 @@
|
||||
####################################################################################
|
||||
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
|
||||
### SPDX short identifier: BSD-1-Clause
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := spi_engine_offload
|
||||
|
||||
GENERIC_DEPS += spi_engine_offload.v
|
||||
|
||||
XILINX_DEPS += spi_engine_offload_constr.ttcl
|
||||
XILINX_DEPS += spi_engine_offload_ip.tcl
|
||||
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
|
||||
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
|
||||
|
||||
XILINX_LIB_DEPS += util_cdc
|
||||
|
||||
INTEL_DEPS += ../../util_cdc/sync_bits.v
|
||||
INTEL_DEPS += spi_engine_offload_hw.tcl
|
||||
|
||||
include ../../scripts/library.mk
|
||||
@@ -0,0 +1,954 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>spi_engine_offload</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_offload_ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_WR_EN</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_cmd_wr_en</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_WR_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_cmd_wr_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_WR_EN</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_sdo_wr_en</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_WR_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_sdo_wr_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ENABLE</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_enable</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ENABLED</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_enabled</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>MEM_RESET</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_mem_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>status_sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>status_sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>status_sync_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>offload_sdi</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>offload_sdi_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>offload_sdi_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>offload_sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_ctrl_offload_sdi_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_engine_ctrl_offload_sdi_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>spi_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi_engine_ctrl:offload_sdi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_CLOCK.ASSOCIATED_RESET">spi_resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_ctrl_offload_sdi_signal_reset</spirit:name>
|
||||
<spirit:displayName>spi_engine_ctrl_offload_sdi_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>spi_resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_offload_ctrl_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_engine_offload_ctrl_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi_engine_offload_ctrl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_offload</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>54da56d5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_offload</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>54da56d5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>9caa5391</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
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|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_sdo_wr_data</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_enable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_enabled</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_mem_reset</spirit:name>
|
||||
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|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>status_sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>status_sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
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|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>status_sync_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
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|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>spi_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>spi_resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>trigger</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
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|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
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|
||||
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|
||||
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|
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<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
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||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
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|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
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|
||||
</spirit:wireTypeDef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_SPI_CLK</spirit:name>
|
||||
<spirit:displayName>Async Spi Clk</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_SPI_CLK">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_TRIG</spirit:name>
|
||||
<spirit:displayName>Async Trig</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_TRIG">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CMD_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Cmd Mem Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDO_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Sdo Mem Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Num Of Sdi</spirit:displayName>
|
||||
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:name>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
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<spirit:vendorExtensions>
|
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<xilinx:subCoreRef>
|
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<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0"/>
|
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</xilinx:subCoreRef>
|
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</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>spi_engine_offload_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASYNC_SPI_CLK</spirit:name>
|
||||
<spirit:displayName>Asynchronous core clock</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_SPI_CLK">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASYNC_TRIG</spirit:name>
|
||||
<spirit:displayName>Asynchronous trigger</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_TRIG">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CMD_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Command FIFO address width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDO_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>MOSI FIFO address width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Shift register's data width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="8" spirit:maximum="256" spirit:rangeType="long">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Number of MISO lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_SDI" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">spi_engine_offload_v1_0</spirit:value>
|
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</spirit:parameter>
|
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
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</xilinx:taxonomies>
|
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<xilinx:displayName>spi_engine_offload_v1_0</xilinx:displayName>
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-14T03:53:04Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8689cb20"/>
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||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="2756ddd5"/>
|
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ae1a9eae"/>
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|
||||
</spirit:component>
|
||||
@@ -0,0 +1,304 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_offload #(
|
||||
|
||||
parameter ASYNC_SPI_CLK = 0,
|
||||
parameter ASYNC_TRIG = 0,
|
||||
parameter CMD_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter SDO_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1
|
||||
) (
|
||||
input ctrl_clk,
|
||||
|
||||
input ctrl_cmd_wr_en,
|
||||
input [15:0] ctrl_cmd_wr_data,
|
||||
|
||||
input ctrl_sdo_wr_en,
|
||||
input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
|
||||
|
||||
input ctrl_enable,
|
||||
output ctrl_enabled,
|
||||
input ctrl_mem_reset,
|
||||
|
||||
output status_sync_valid,
|
||||
input status_sync_ready,
|
||||
output [7:0] status_sync_data,
|
||||
|
||||
input spi_clk,
|
||||
input spi_resetn,
|
||||
|
||||
input trigger,
|
||||
|
||||
output cmd_valid,
|
||||
input cmd_ready,
|
||||
output [15:0] cmd,
|
||||
|
||||
output sdo_data_valid,
|
||||
input sdo_data_ready,
|
||||
output [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
input sdi_data_valid,
|
||||
output sdi_data_ready,
|
||||
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
|
||||
|
||||
input sync_valid,
|
||||
output sync_ready,
|
||||
input [7:0] sync_data,
|
||||
|
||||
output offload_sdi_valid,
|
||||
input offload_sdi_ready,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
|
||||
);
|
||||
|
||||
reg spi_active = 1'b0;
|
||||
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
|
||||
|
||||
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
|
||||
reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
|
||||
|
||||
wire [15:0] cmd_int_s;
|
||||
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
|
||||
wire spi_enable;
|
||||
|
||||
assign cmd_valid = spi_active;
|
||||
assign sdo_data_valid = spi_active;
|
||||
|
||||
assign offload_sdi_valid = sdi_data_valid;
|
||||
|
||||
// we don't want to block the SDI interface after disabling the module
|
||||
// so just assert the SDI_READY if the sink module (DMA) is disabled
|
||||
assign sdi_data_ready = (spi_enable) ? offload_sdi_ready : 1'b1;
|
||||
|
||||
assign offload_sdi_data = sdi_data;
|
||||
|
||||
assign cmd_int_s = cmd_mem[spi_cmd_rd_addr];
|
||||
assign sdo_data = sdo_mem[spi_sdo_rd_addr];
|
||||
|
||||
/* SYNC ID counter. The offload module increments the sync_id on each
|
||||
* transaction. The initial value of the sync_id is the value of the last
|
||||
* sync_id command loaded into the command buffer.
|
||||
*/
|
||||
|
||||
reg [ 7:0] ctrl_sync_id_init = 8'b0;
|
||||
reg ctrl_sync_id_load = 1'b0;
|
||||
reg [ 7:0] spi_sync_id_counter = 8'b0;
|
||||
|
||||
wire [ 7:0] spi_sync_id_init_s;
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset == 1'b1) begin
|
||||
ctrl_sync_id_init <= 8'b0;
|
||||
ctrl_sync_id_load <= 1'b0;
|
||||
end else begin
|
||||
if (ctrl_cmd_wr_en && (ctrl_cmd_wr_data[15:8] == 8'h30)) begin
|
||||
ctrl_sync_id_init <= ctrl_cmd_wr_data;
|
||||
ctrl_sync_id_load <= 1'b1;
|
||||
end else begin
|
||||
ctrl_sync_id_load <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire spi_sync_id_load_s;
|
||||
|
||||
sync_event #(
|
||||
.NUM_OF_EVENTS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_sync_id_load (
|
||||
.in_clk (ctrl_clk),
|
||||
.in_event(ctrl_sync_id_load),
|
||||
.out_clk(spi_clk),
|
||||
.out_event(spi_sync_id_load_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(8),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_sync_id (
|
||||
.in_bits(ctrl_sync_id_init),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_sync_id_init_s));
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (spi_resetn == 1'b0) begin
|
||||
spi_sync_id_counter <= 8'b0;
|
||||
end else begin
|
||||
if (spi_sync_id_load_s) begin
|
||||
spi_sync_id_counter <= spi_sync_id_init_s;
|
||||
end else if(cmd_valid && cmd_ready && (cmd[15:8] == 8'h30)) begin
|
||||
spi_sync_id_counter <= spi_sync_id_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cmd = (cmd_int_s[15:8] == 8'h30) ? {cmd_int_s[15:8], spi_sync_id_counter} : cmd_int_s;
|
||||
|
||||
/*
|
||||
* Forwarded SYNC interface, this can be used to monitor the state of the
|
||||
* offload command sequence through SPI Engine regmap
|
||||
*/
|
||||
|
||||
assign status_sync_data = sync_data;
|
||||
assign status_sync_valid = sync_valid;
|
||||
assign sync_ready = status_sync_ready;
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
/*
|
||||
* The synchronization circuit takes care that there are no glitches on the
|
||||
* ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
|
||||
* asserted, but only deasserted once the signal has been synchronized back from
|
||||
* the SPI domain. This makes sure that we can't end up in a state where the
|
||||
* enable signal in the SPI domain is asserted, but neither enable nor enabled
|
||||
* is asserted in the control domain.
|
||||
*/
|
||||
|
||||
reg ctrl_do_enable = 1'b0;
|
||||
wire ctrl_is_enabled;
|
||||
reg spi_enabled = 1'b0;
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_enable == 1'b1) begin
|
||||
ctrl_do_enable <= 1'b1;
|
||||
end else if (ctrl_is_enabled == 1'b1) begin
|
||||
ctrl_do_enable <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
spi_enabled <= spi_enable | spi_active;
|
||||
end
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enable (
|
||||
.in_bits(ctrl_do_enable),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enabled (
|
||||
.in_bits(spi_enabled),
|
||||
.out_clk(ctrl_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(ctrl_is_enabled));
|
||||
|
||||
end else begin
|
||||
assign spi_enable = ctrl_enable;
|
||||
assign ctrl_enabled = spi_enable | spi_active;
|
||||
end endgenerate
|
||||
|
||||
assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
|
||||
|
||||
wire trigger_s;
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_TRIG)
|
||||
) i_sync_trigger (
|
||||
.in_bits(trigger),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(trigger_s));
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (spi_resetn == 1'b0) begin
|
||||
spi_active <= 1'b0;
|
||||
end else begin
|
||||
if (spi_active == 1'b0) begin
|
||||
// start offload when we have a valid trigger, offload is enabled and
|
||||
// the DMA is enabled
|
||||
if (trigger_s == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1)
|
||||
spi_active <= 1'b1;
|
||||
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
|
||||
spi_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (cmd_valid == 1'b0) begin
|
||||
spi_cmd_rd_addr <= 'h00;
|
||||
end else if (cmd_ready == 1'b1) begin
|
||||
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (spi_active == 1'b0) begin
|
||||
spi_sdo_rd_addr <= 'h00;
|
||||
end else if (sdo_data_ready == 1'b1) begin
|
||||
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset == 1'b1)
|
||||
ctrl_cmd_wr_addr <= 'h00;
|
||||
else if (ctrl_cmd_wr_en == 1'b1)
|
||||
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_cmd_wr_en == 1'b1)
|
||||
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset == 1'b1)
|
||||
ctrl_sdo_wr_addr <= 'h00;
|
||||
else if (ctrl_sdo_wr_en == 1'b1)
|
||||
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_sdo_wr_en == 1'b1)
|
||||
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,400 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="30b4a7c406754ea493b787146654d616"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/spi_engine_offload.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/spi_engine_offload_constr.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="spi_engine_offload"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,36 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
|
||||
|
||||
<: if { $async_spi_clk } { :>
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_out/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_in/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enable/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enabled/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_trigger/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
<: } :>
|
||||
@@ -0,0 +1,117 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create spi_engine_offload {SPI Engine Offload} p_elaboration
|
||||
ad_ip_files spi_engine_offload [list\
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
spi_engine_offload.v]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter ASYNC_SPI_CLK INTEGER 0
|
||||
ad_ip_parameter ASYNC_TRIG INTEGER 0
|
||||
ad_ip_parameter CMD_MEM_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter SDO_MEM_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter DATA_WIDTH INTEGER 8
|
||||
ad_ip_parameter NUM_OF_SDI INTEGER 1
|
||||
|
||||
proc p_elaboration {} {
|
||||
|
||||
set data_width [get_parameter_value DATA_WIDTH]
|
||||
set num_of_sdi [get_parameter_value NUM_OF_SDI]
|
||||
|
||||
# control interface
|
||||
|
||||
ad_interface clock ctrl_clk input 1
|
||||
ad_interface reset spi_resetn input 1 if_spi_clk
|
||||
|
||||
add_interface ctrl_cmd_wr conduit end
|
||||
add_interface_port ctrl_cmd_wr ctrl_cmd_wr_en wre input 1
|
||||
add_interface_port ctrl_cmd_wr ctrl_cmd_wr_data data input 16
|
||||
|
||||
set_interface_property ctrl_cmd_wr associatedClock if_ctrl_clk
|
||||
set_interface_property ctrl_cmd_wr associatedReset none
|
||||
|
||||
add_interface ctrl_sdo_wr conduit end
|
||||
add_interface_port ctrl_sdo_wr ctrl_sdo_wr_en wre input 1
|
||||
add_interface_port ctrl_sdo_wr ctrl_sdo_wr_data data input $data_width
|
||||
|
||||
set_interface_property ctrl_sdo_wr associatedClock if_ctrl_clk
|
||||
set_interface_property ctrl_sdo_wr associatedReset none
|
||||
|
||||
ad_interface signal ctrl_enable input 1 enable
|
||||
ad_interface signal ctrl_enabled output 1 enabled
|
||||
ad_interface signal ctrl_mem_reset input 1 reset
|
||||
|
||||
add_interface status_sync axi4stream start
|
||||
add_interface_port status_sync status_sync_valid tvalid output 1
|
||||
add_interface_port status_sync status_sync_ready tready input 1
|
||||
add_interface_port status_sync status_sync_data tdata output 8
|
||||
|
||||
set_interface_property status_sync associatedClock if_spi_clk
|
||||
set_interface_property status_sync associatedReset if_spi_resetn
|
||||
|
||||
# SPI Engine interfaces
|
||||
|
||||
ad_interface clock spi_clk input 1
|
||||
ad_interface resetn spi_resetn input 1 if_spi_clk
|
||||
|
||||
ad_interface signal trigger input 1 if_pwm
|
||||
|
||||
## command interface
|
||||
|
||||
add_interface cmd axi4stream start
|
||||
add_interface_port cmd cmd_valid tvalid output 1
|
||||
add_interface_port cmd cmd_ready tready input 1
|
||||
add_interface_port cmd cmd tdata output 16
|
||||
|
||||
set_interface_property cmd associatedClock if_spi_clk
|
||||
set_interface_property cmd associatedReset if_spi_resetn
|
||||
|
||||
## SDO data interface
|
||||
|
||||
add_interface sdo_data axi4stream start
|
||||
add_interface_port sdo_data sdo_data_valid tvalid output 1
|
||||
add_interface_port sdo_data sdo_data_ready tready input 1
|
||||
add_interface_port sdo_data sdo_data tdata output $data_width
|
||||
|
||||
set_interface_property sdo_data associatedClock if_spi_clk
|
||||
set_interface_property sdo_data associatedReset if_spi_resetn
|
||||
|
||||
## SDI data interface
|
||||
|
||||
add_interface sdi_data axi4stream end
|
||||
add_interface_port sdi_data sdi_data_valid tvalid input 1
|
||||
add_interface_port sdi_data sdi_data_ready tready output 1
|
||||
add_interface_port sdi_data sdi_data tdata input [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property sdi_data associatedClock if_spi_clk
|
||||
set_interface_property sdi_data associatedReset if_spi_resetn
|
||||
|
||||
## SYNC data interface
|
||||
|
||||
add_interface sync axi4stream end
|
||||
add_interface_port sync sync_valid tvalid input 1
|
||||
add_interface_port sync sync_ready tready output 1
|
||||
add_interface_port sync sync_data tdata input 8
|
||||
|
||||
set_interface_property sync associatedClock if_spi_clk
|
||||
set_interface_property sync associatedReset if_spi_resetn
|
||||
|
||||
## Offload SDI data interface
|
||||
|
||||
add_interface offload_sdi axi4stream start
|
||||
add_interface_port offload_sdi offload_sdi_valid tvalid output 1
|
||||
add_interface_port offload_sdi offload_sdi_ready tready input 1
|
||||
add_interface_port offload_sdi offload_sdi_data tdata output [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property offload_sdi associatedClock if_spi_clk
|
||||
set_interface_property offload_sdi associatedReset if_spi_resetn
|
||||
|
||||
}
|
||||
@@ -0,0 +1,193 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create spi_engine_offload
|
||||
adi_ip_files spi_engine_offload [list \
|
||||
"spi_engine_offload_constr.ttcl" \
|
||||
"spi_engine_offload.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite spi_engine_offload
|
||||
adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl"
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload} [ipx::current_core]
|
||||
|
||||
# Remove all inferred interfaces
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "spi_engine_ctrl" "master" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{
|
||||
{"cmd_ready" "CMD_READY"} \
|
||||
{"cmd_valid" "CMD_VALID"} \
|
||||
{"cmd" "CMD_DATA"} \
|
||||
{"sdo_data_ready" "SDO_READY"} \
|
||||
{"sdo_data_valid" "SDO_VALID"} \
|
||||
{"sdo_data" "SDO_DATA"} \
|
||||
{"sdi_data_ready" "SDI_READY"} \
|
||||
{"sdi_data_valid" "SDI_VALID"} \
|
||||
{"sdi_data" "SDI_DATA"} \
|
||||
{"sync_ready" "SYNC_READY"} \
|
||||
{"sync_valid" "SYNC_VALID"} \
|
||||
{"sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus "spi_engine_offload_ctrl" "slave" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
|
||||
{ \
|
||||
{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
|
||||
{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
|
||||
{ "ctrl_sdo_wr_en" "SDO_WR_EN"} \
|
||||
{ "ctrl_sdo_wr_data" "SDO_WR_DATA"} \
|
||||
{ "ctrl_enable" "ENABLE"} \
|
||||
{ "ctrl_enabled" "ENABLED"} \
|
||||
{ "ctrl_mem_reset" "MEM_RESET"} \
|
||||
{ "status_sync_ready" "SYNC_READY"} \
|
||||
{ "status_sync_valid" "SYNC_VALID"} \
|
||||
{ "status_sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus "offload_sdi" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{ \
|
||||
{"offload_sdi_valid" "TVALID"} \
|
||||
{"offload_sdi_ready" "TREADY"} \
|
||||
{"offload_sdi_data" "TDATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus_clock "spi_clk" "spi_engine_ctrl:offload_sdi" "spi_resetn"
|
||||
adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
|
||||
|
||||
## Parameter validations
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
## ASYNC_SPI_CLK
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc]
|
||||
|
||||
## ASYNC_TRIG
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_user_parameters ASYNC_TRIG -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters ASYNC_TRIG -of_objects $cc]
|
||||
|
||||
## NUM_OF_SDI
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
|
||||
## DATA_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "8" \
|
||||
"value_validation_range_maximum" "256" \
|
||||
] \
|
||||
[ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
|
||||
## CMD_MEM_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters CMD_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## SDO_MEM_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDO_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## Customize IP Layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create general configuration page
|
||||
ipgui::add_page -name {SPI Engine RX offload} -component [ipx::current_core] -display_name {SPI Engine RX offload}
|
||||
set page0 [ipgui::get_pagespec -name "SPI Engine RX offload" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration" ]
|
||||
|
||||
ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Shift register's data width" \
|
||||
"tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO lines" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Asynchronous core clock" \
|
||||
"tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \
|
||||
] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc]
|
||||
|
||||
ipgui::add_param -name "ASYNC_TRIG" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Asynchronous trigger" \
|
||||
"tooltip" "\[ASYNC_TRIG\] Set if the external trigger is asynchronous to the core clk" \
|
||||
] [ipgui::get_guiparamspec -name "ASYNC_TRIG" -component $cc]
|
||||
|
||||
## Command stream FIFO depth configuration
|
||||
set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \
|
||||
-parent $page0 -display_name "Command stream FIFO configuration" ]
|
||||
|
||||
ipgui::add_param -name "CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Command FIFO address width" \
|
||||
"tooltip" "\[CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "CMD_MEM_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "MOSI FIFO address width" \
|
||||
"tooltip" "\[SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "SDO_MEM_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files $cc
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,112 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_RX_offload [ipgui::add_page $IPINST -name "SPI Engine RX offload"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_RX_offload}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
set ASYNC_SPI_CLK [ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_SPI_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_SPI_CLK}
|
||||
set ASYNC_TRIG [ipgui::add_param $IPINST -name "ASYNC_TRIG" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_TRIG] Set if the external trigger is asynchronous to the core clk} ${ASYNC_TRIG}
|
||||
|
||||
#Adding Group
|
||||
set Command_stream_FIFO_configuration [ipgui::add_group $IPINST -name "Command stream FIFO configuration" -parent ${SPI_Engine_RX_offload}]
|
||||
set CMD_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "CMD_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[CMD_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${CMD_MEM_ADDRESS_WIDTH}
|
||||
set SDO_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDO_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDO_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDO_MEM_ADDRESS_WIDTH}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to validate ASYNC_SPI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to update ASYNC_TRIG when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to validate ASYNC_TRIG
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate CMD_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDO_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_TRIG { MODELPARAM_VALUE.ASYNC_TRIG PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_TRIG}] ${MODELPARAM_VALUE.ASYNC_TRIG}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user