initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_spi_engine
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GENERIC_DEPS += ../../common/ad_rst.v
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GENERIC_DEPS += ../../common/up_axi.v
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GENERIC_DEPS += axi_spi_engine.v
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XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += axi_spi_engine_constr.ttcl
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XILINX_DEPS += axi_spi_engine_ip.tcl
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
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XILINX_LIB_DEPS += util_axis_fifo
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XILINX_LIB_DEPS += util_cdc
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INTEL_DEPS += ../../common/ad_mem.v
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INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
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INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo_address_generator.v
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INTEL_DEPS += ../../util_cdc/sync_bits.v
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INTEL_DEPS += ../../util_cdc/sync_gray.v
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INTEL_DEPS += axi_spi_engine_constr.sdc
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INTEL_DEPS += axi_spi_engine_hw.tcl
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include ../../scripts/library.mk
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@@ -0,0 +1,653 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_spi_engine #(
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parameter CMD_FIFO_ADDRESS_WIDTH = 4,
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parameter SYNC_FIFO_ADDRESS_WIDTH = 4,
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parameter SDO_FIFO_ADDRESS_WIDTH = 5,
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parameter SDI_FIFO_ADDRESS_WIDTH = 5,
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parameter MM_IF_TYPE = 0,
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parameter ASYNC_SPI_CLK = 0,
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parameter NUM_OFFLOAD = 0,
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parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,
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parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
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parameter ID = 0,
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parameter [15:0] DATA_WIDTH = 8,
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parameter [ 7:0] NUM_OF_SDI = 1,
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parameter CFG_INFO_0 = 0,
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parameter CFG_INFO_1 = 0,
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parameter CFG_INFO_2 = 0,
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parameter CFG_INFO_3 = 0
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) (
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// Slave AXI interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// up interface
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input up_clk,
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input up_rstn,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack,
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output reg irq,
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// SPI signals
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input spi_clk,
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output spi_resetn,
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input cmd_ready,
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output cmd_valid,
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output [15:0] cmd_data,
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input sdo_data_ready,
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output sdo_data_valid,
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output [(DATA_WIDTH-1):0] sdo_data,
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output sdi_data_ready,
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input sdi_data_valid,
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input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
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output sync_ready,
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input sync_valid,
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input [7:0] sync_data,
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// Offload ctrl signals
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output offload0_cmd_wr_en,
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output [15:0] offload0_cmd_wr_data,
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output offload0_sdo_wr_en,
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output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
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output offload0_mem_reset,
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output offload0_enable,
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input offload0_enabled,
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output offload_sync_ready,
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input offload_sync_valid,
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input [7:0] offload_sync_data
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);
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localparam PCORE_VERSION = 'h010071;
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localparam S_AXI = 0;
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localparam UP_FIFO = 1;
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wire clk;
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wire rstn;
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wire [CMD_FIFO_ADDRESS_WIDTH-1:0] cmd_fifo_room;
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wire cmd_fifo_almost_empty;
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wire up_cmd_fifo_almost_empty;
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wire [15:0] cmd_fifo_in_data;
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wire cmd_fifo_in_ready;
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wire cmd_fifo_in_valid;
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wire [SDO_FIFO_ADDRESS_WIDTH-1:0] sdo_fifo_room;
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wire sdo_fifo_almost_empty;
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wire up_sdo_fifo_almost_empty;
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wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
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wire sdo_fifo_in_ready;
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wire sdo_fifo_in_valid;
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wire sdi_fifo_out_data_msb_s;
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wire [SDI_FIFO_ADDRESS_WIDTH-1:0] sdi_fifo_level;
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wire sdi_fifo_almost_full;
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wire up_sdi_fifo_almost_full;
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wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
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wire sdi_fifo_out_ready;
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wire sdi_fifo_out_valid;
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wire [7:0] sync_fifo_data;
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wire sync_fifo_valid;
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wire [7:0] offload_sync_fifo_data;
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wire offload_sync_fifo_valid;
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reg up_sw_reset = 1'b1;
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wire up_sw_resetn = ~up_sw_reset;
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reg [31:0] up_rdata_ff = 'd0;
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reg up_wack_ff = 1'b0;
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reg up_rack_ff = 1'b0;
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wire up_wreq_s;
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wire up_rreq_s;
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wire [31:0] up_wdata_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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// Scratch register
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reg [31:0] up_scratch = 'h00;
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reg [7:0] sync_id = 'h00;
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reg sync_id_pending = 1'b0;
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reg [7:0] offload_sync_id = 'h00;
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reg offload_sync_id_pending = 1'b0;
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generate if (MM_IF_TYPE == S_AXI) begin
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// assign clock and reset
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assign clk = s_axi_aclk;
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assign rstn = s_axi_aresetn;
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// interface wrapper
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up_axi #(
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.AXI_ADDRESS_WIDTH (16)
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) i_up_axi (
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.up_rstn(rstn),
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.up_clk(clk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq(up_wreq_s),
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.up_waddr(up_waddr_s),
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.up_wdata(up_wdata_s),
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.up_wack(up_wack_ff),
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.up_rreq(up_rreq_s),
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.up_raddr(up_raddr_s),
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.up_rdata(up_rdata_ff),
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.up_rack(up_rack_ff));
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assign up_rdata = 32'b0;
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assign up_rack = 1'b0;
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assign up_wack = 1'b0;
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end
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endgenerate
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generate if (MM_IF_TYPE == UP_FIFO) begin
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// assign clock and reset
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assign clk = up_clk;
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assign rstn = up_rstn;
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assign up_wreq_s = up_wreq;
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assign up_waddr_s = up_waddr;
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assign up_wdata_s = up_wdata;
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assign up_wack = up_wack_ff;
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assign up_rreq_s = up_rreq;
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assign up_raddr_s = up_raddr;
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assign up_rdata = up_rdata_ff;
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assign up_rack = up_rack_ff;
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end
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endgenerate
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// IRQ handling
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reg [4:0] up_irq_mask = 5'h0;
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wire [4:0] up_irq_source;
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wire [4:0] up_irq_pending;
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assign up_irq_source = {
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offload_sync_id_pending,
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sync_id_pending,
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up_sdi_fifo_almost_full,
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up_sdo_fifo_almost_empty,
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up_cmd_fifo_almost_empty
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};
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assign up_irq_pending = up_irq_mask & up_irq_source;
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always @(posedge clk) begin
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if (rstn == 1'b0)
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irq <= 1'b0;
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else
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irq <= |up_irq_pending;
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end
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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up_wack_ff <= 1'b0;
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up_scratch <= 'h00;
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up_sw_reset <= 1'b1;
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end else begin
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up_wack_ff <= up_wreq_s;
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h02: up_scratch <= up_wdata_s;
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8'h10: up_sw_reset <= up_wdata_s;
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endcase
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end
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end
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end
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reg offload0_enable_reg;
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reg offload0_mem_reset_reg;
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wire offload0_enabled_s;
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// the software reset should reset all the registers
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always @(posedge clk) begin
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if (up_sw_resetn == 1'b0) begin
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up_irq_mask <= 'h00;
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offload0_enable_reg <= 1'b0;
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offload0_mem_reset_reg <= 1'b0;
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end else begin
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h20: up_irq_mask <= up_wdata_s;
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8'h40: offload0_enable_reg <= up_wdata_s[0];
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8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
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endcase
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end
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end
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end
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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up_rack_ff <= 'd0;
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end else begin
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up_rack_ff <= up_rreq_s;
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end
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end
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generate
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if (NUM_OF_SDI > 1) begin
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// Only the first two SDI data can be recovered through AXI regmap
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
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end else begin
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
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end
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endgenerate
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always @(posedge clk) begin
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case (up_raddr_s)
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8'h00: up_rdata_ff <= PCORE_VERSION;
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8'h01: up_rdata_ff <= ID;
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8'h02: up_rdata_ff <= up_scratch;
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8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
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8'h10: up_rdata_ff <= up_sw_reset;
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8'h20: up_rdata_ff <= up_irq_mask;
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8'h21: up_rdata_ff <= up_irq_pending;
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8'h22: up_rdata_ff <= up_irq_source;
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8'h30: up_rdata_ff <= sync_id;
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8'h31: up_rdata_ff <= offload_sync_id;
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8'h34: up_rdata_ff <= cmd_fifo_room;
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8'h35: up_rdata_ff <= sdo_fifo_room;
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8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* beacuse of first-word-fall-through */
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8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
|
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8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
|
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8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
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8'h40: up_rdata_ff <= {offload0_enable_reg};
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8'h41: up_rdata_ff <= {offload0_enabled_s};
|
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8'h80: up_rdata_ff <= CFG_INFO_0;
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8'h81: up_rdata_ff <= CFG_INFO_1;
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8'h82: up_rdata_ff <= CFG_INFO_2;
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8'h83: up_rdata_ff <= CFG_INFO_3;
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default: up_rdata_ff <= 'h00;
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endcase
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end
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always @(posedge clk) begin
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if (up_sw_resetn == 1'b0) begin
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sync_id <= 'h00;
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sync_id_pending <= 1'b0;
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end else begin
|
||||
if (sync_fifo_valid == 1'b1) begin
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||||
sync_id <= sync_fifo_data;
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sync_id_pending <= 1'b1;
|
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end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
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sync_id_pending <= 1'b0;
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end
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||||
end
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||||
end
|
||||
|
||||
always @(posedge clk) begin
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||||
if (up_sw_resetn == 1'b0) begin
|
||||
offload_sync_id <= 'h00;
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end else begin
|
||||
if (offload_sync_fifo_valid == 1'b1) begin
|
||||
offload_sync_id <= offload_sync_fifo_data;
|
||||
offload_sync_id_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[4] == 1'b1) begin
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
wire spi_reset;
|
||||
ad_rst i_spi_resetn (
|
||||
.rst_async(up_sw_reset),
|
||||
.clk(spi_clk),
|
||||
.rst(spi_reset),
|
||||
.rstn());
|
||||
assign spi_resetn = ~spi_reset;
|
||||
end else begin
|
||||
assign spi_resetn = ~up_sw_reset;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38;
|
||||
assign cmd_fifo_in_data = up_wdata_s[15:0];
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(1)
|
||||
) i_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(cmd_fifo_in_ready),
|
||||
.s_axis_valid(cmd_fifo_in_valid),
|
||||
.s_axis_data(cmd_fifo_in_data),
|
||||
.s_axis_room(cmd_fifo_room),
|
||||
.s_axis_tlast(1'b0),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(cmd_ready),
|
||||
.m_axis_valid(cmd_valid),
|
||||
.m_axis_data(cmd_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty(cmd_fifo_almost_empty),
|
||||
.m_axis_level());
|
||||
|
||||
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
|
||||
assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(1)
|
||||
) i_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(sdo_fifo_in_ready),
|
||||
.s_axis_valid(sdo_fifo_in_valid),
|
||||
.s_axis_data(sdo_fifo_in_data),
|
||||
.s_axis_room(sdo_fifo_room),
|
||||
.s_axis_tlast(1'b0),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(sdo_data_ready),
|
||||
.m_axis_valid(sdo_data_valid),
|
||||
.m_axis_data(sdo_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty(sdo_fifo_almost_empty));
|
||||
|
||||
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0),
|
||||
.ALMOST_EMPTY_THRESHOLD(1),
|
||||
.ALMOST_FULL_THRESHOLD(31)
|
||||
) i_sdi_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sdi_data_ready),
|
||||
.s_axis_valid(sdi_data_valid),
|
||||
.s_axis_data(sdi_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_tlast(),
|
||||
.s_axis_full(),
|
||||
.s_axis_almost_full(sdi_fifo_almost_full),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(sdi_fifo_out_ready),
|
||||
.m_axis_valid(sdi_fifo_out_valid),
|
||||
.m_axis_data(sdi_fifo_out_data),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_level(sdi_fifo_level),
|
||||
.m_axis_empty(),
|
||||
.m_axis_almost_empty());
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
// synchronization FIFO for the SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sync_ready),
|
||||
.s_axis_valid(sync_valid),
|
||||
.s_axis_data(sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(sync_fifo_valid),
|
||||
.m_axis_data(sync_fifo_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
// synchronization FIFO for the offload command interface
|
||||
wire up_offload0_cmd_wr_en_s;
|
||||
wire [15:0] up_offload0_cmd_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_offload_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_cmd_wr_en_s),
|
||||
.s_axis_data(up_offload0_cmd_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_cmd_wr_en),
|
||||
.m_axis_data(offload0_cmd_wr_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
|
||||
|
||||
// synchronization FIFO for the offload SDO interface
|
||||
wire up_offload0_sdo_wr_en_s;
|
||||
wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_offload_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_sdo_wr_en_s),
|
||||
.s_axis_data(up_offload0_sdo_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_sdo_wr_en),
|
||||
.m_axis_data(offload0_sdo_wr_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
// synchronization FIFO for the Offload SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.M_AXIS_REGISTERED(0)
|
||||
) i_offload_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(offload_sync_ready),
|
||||
.s_axis_valid(offload_sync_valid),
|
||||
.s_axis_data(offload_sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_full(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload_sync_fifo_valid),
|
||||
.m_axis_data(offload_sync_fifo_data),
|
||||
.m_axis_level(),
|
||||
.m_axis_empty());
|
||||
|
||||
end else begin /* ASYNC_SPI_CLK == 0 */
|
||||
|
||||
assign sync_fifo_valid = sync_valid;
|
||||
assign sync_fifo_data = sync_data;
|
||||
assign sync_ready = 1'b1;
|
||||
|
||||
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign offload0_cmd_wr_data = up_wdata_s[15:0];
|
||||
|
||||
assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
assign offload_sync_fifo_valid = offload_sync_valid;
|
||||
assign offload_sync_fifo_data = offload_sync_data;
|
||||
assign offload_sync_ready = 1'b1;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enable_sync (
|
||||
.in_bits (offload0_enable_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enabled_sync (
|
||||
.in_bits (offload0_enabled),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (clk),
|
||||
.out_bits (offload0_enabled_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_mem_reset_sync (
|
||||
.in_bits (offload0_mem_reset_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_mem_reset));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (3),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_fifo_status (
|
||||
.in_bits ({cmd_fifo_almost_empty, sdi_fifo_almost_full, sdo_fifo_almost_empty}),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (clk),
|
||||
.out_bits ({up_cmd_fifo_almost_empty, up_sdi_fifo_almost_full, up_sdo_fifo_almost_empty}));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,420 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="7614137f133e45a3b5014a3375bb1862"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_spi_engine.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_spi_engine_constr.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_spi_engine"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../xilinx/common/ad_rst_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,8 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
set_false_path \
|
||||
-to [get_registers *cdc_sync_stage1*]
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
# SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
|
||||
|
||||
<: if { $async_spi_clk } { :>
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
|
||||
|
||||
set_false_path -quiet \
|
||||
-from [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enable_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enabled_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_mem_reset_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_fifo_status/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
<: } :>
|
||||
@@ -0,0 +1,188 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create axi_spi_engine {AXI SPI Engine} p_elaboration
|
||||
ad_ip_files axi_spi_engine [list\
|
||||
$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v \
|
||||
$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo_address_generator.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_gray.v \
|
||||
$ad_hdl_dir/library/common/ad_mem.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/ad_rst.v \
|
||||
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
|
||||
axi_spi_engine_constr.sdc \
|
||||
axi_spi_engine.v]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter CMD_FIFO_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter SYNC_FIFO_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter SDO_FIFO_ADDRESS_WIDTH INTEGER 5
|
||||
ad_ip_parameter SDI_FIFO_ADDRESS_WIDTH INTEGER 5
|
||||
ad_ip_parameter MM_IF_TYPE INTEGER 1
|
||||
ad_ip_parameter ASYNC_SPI_CLK INTEGER 0
|
||||
ad_ip_parameter NUM_OFFLOAD INTEGER 1
|
||||
ad_ip_parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter ID INTEGER 0
|
||||
ad_ip_parameter DATA_WIDTH INTEGER 8
|
||||
ad_ip_parameter NUM_OF_SDI INTEGER 1
|
||||
|
||||
proc p_elaboration {} {
|
||||
|
||||
# read parameters
|
||||
|
||||
set mm_if_type [get_parameter_value "MM_IF_TYPE"]
|
||||
|
||||
set num_of_sdi [get_parameter_value NUM_OF_SDI]
|
||||
set data_width [get_parameter_value DATA_WIDTH]
|
||||
|
||||
# interrupt
|
||||
|
||||
add_interface interrupt_sender interrupt end
|
||||
add_interface_port interrupt_sender irq irq Output 1
|
||||
|
||||
# Microprocessor interface
|
||||
|
||||
ad_interface clock up_clk input 1
|
||||
ad_interface reset up_rstn input 1 if_up_clk
|
||||
ad_interface signal up_wreq input 1
|
||||
ad_interface signal up_wack output 1
|
||||
ad_interface signal up_waddr input 14
|
||||
ad_interface signal up_wdata input 32
|
||||
ad_interface signal up_rreq input 1
|
||||
ad_interface signal up_rack output 1
|
||||
ad_interface signal up_raddr output 14
|
||||
ad_interface signal up_rdata output 32
|
||||
|
||||
# AXI Memory Mapped interface
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16
|
||||
|
||||
set disabled_intfs {}
|
||||
if {$mm_if_type} {
|
||||
|
||||
# uProcessor interface active for regmap, deactivate S_AXI
|
||||
lappend disabled_intfs s_axi
|
||||
|
||||
set_port_property s_axi_aclk termination true
|
||||
set_port_property s_axi_aresetn termination true
|
||||
set_port_property s_axi_aresetn termination_value 1
|
||||
set_port_property s_axi_awvalid termination true
|
||||
set_port_property s_axi_awaddr termination true
|
||||
set_port_property s_axi_awprot termination true
|
||||
set_port_property s_axi_wvalid termination true
|
||||
set_port_property s_axi_wdata termination true
|
||||
set_port_property s_axi_wstrb termination true
|
||||
set_port_property s_axi_bready termination true
|
||||
set_port_property s_axi_arvalid termination true
|
||||
set_port_property s_axi_araddr termination true
|
||||
set_port_property s_axi_arprot termination true
|
||||
set_port_property s_axi_rready termination true
|
||||
|
||||
} else {
|
||||
|
||||
set_interface_property interrupt_sender associatedAddressablePoint s_axi
|
||||
set_interface_property interrupt_sender associatedClock s_axi_clock
|
||||
set_interface_property interrupt_sender associatedReset s_axi_reset
|
||||
set_interface_property interrupt_sender ENABLED true
|
||||
|
||||
# AXI4 Slave is active for regmap, deactivate uP
|
||||
lappend disabled_intfs if_up_clk if_up_rstn if_up_wreq if_up_wack if_up_waddr \
|
||||
if_up_wdata if_up_rreq if_up_rack if_up_raddr if_up_rdata
|
||||
|
||||
set_port_property up_clk termination true
|
||||
set_port_property up_rstn termination true
|
||||
set_port_property up_rstn termination_value 1
|
||||
set_port_property up_wreq termination true
|
||||
set_port_property up_waddr termination true
|
||||
set_port_property up_wdata termination true
|
||||
set_port_property up_rreq termination true
|
||||
set_port_property up_raddr termination true
|
||||
|
||||
}
|
||||
|
||||
ad_interface signal pulse_gen_period output 32
|
||||
ad_interface signal pulse_gen_width output 32
|
||||
ad_interface signal pulse_gen_load output 1
|
||||
|
||||
lappend disabled_intfs if_pulse_gen_period if_pulse_gen_width if_pulse_gen_load
|
||||
|
||||
foreach interface $disabled_intfs {
|
||||
set_interface_property $interface ENABLED false
|
||||
}
|
||||
|
||||
# SPI Engine interfaces
|
||||
|
||||
ad_interface clock spi_clk input 1
|
||||
ad_interface reset spi_resetn output 1 if_spi_clk
|
||||
|
||||
add_interface cmd axi4stream start
|
||||
add_interface_port cmd cmd_ready tready input 1
|
||||
add_interface_port cmd cmd_valid tvalid output 1
|
||||
add_interface_port cmd cmd_data tdata output 16
|
||||
|
||||
set_interface_property cmd associatedClock if_spi_clk
|
||||
set_interface_property cmd associatedReset if_spi_resetn
|
||||
|
||||
add_interface sdo_data axi4stream start
|
||||
add_interface_port sdo_data sdo_data_ready tready input 1
|
||||
add_interface_port sdo_data sdo_data_valid tvalid output 1
|
||||
add_interface_port sdo_data sdo_data tdata output $data_width
|
||||
|
||||
set_interface_property sdo_data associatedClock if_spi_clk
|
||||
set_interface_property sdo_data associatedReset if_spi_resetn
|
||||
|
||||
add_interface sdi_data axi4stream end
|
||||
add_interface_port sdi_data sdi_data_ready tready output 1
|
||||
add_interface_port sdi_data sdi_data_valid tvalid input 1
|
||||
add_interface_port sdi_data sdi_data tdata input [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property sdi_data associatedClock if_spi_clk
|
||||
set_interface_property sdi_data associatedReset if_spi_resetn
|
||||
|
||||
add_interface sync axi4stream end
|
||||
add_interface_port sync sync_valid tvalid input 1
|
||||
add_interface_port sync sync_ready tready output 1
|
||||
add_interface_port sync sync_data tdata input 8
|
||||
|
||||
set_interface_property sync associatedClock if_spi_clk
|
||||
set_interface_property sync associatedReset if_spi_resetn
|
||||
|
||||
# Offload interfaces
|
||||
|
||||
add_interface offload0_cmd conduit end
|
||||
add_interface_port offload0_cmd offload0_cmd_wr_en wre output 1
|
||||
add_interface_port offload0_cmd offload0_cmd_wr_data data output 16
|
||||
|
||||
set_interface_property offload0_cmd associatedClock if_spi_clk
|
||||
set_interface_property offload0_cmd associatedReset none
|
||||
|
||||
add_interface offload0_sdo conduit end
|
||||
add_interface_port offload0_sdo offload0_sdo_wr_en wre output 1
|
||||
add_interface_port offload0_sdo offload0_sdo_wr_data data output $data_width
|
||||
|
||||
set_interface_property offload0_sdo associatedClock if_spi_clk
|
||||
set_interface_property offload0_sdo associatedReset none
|
||||
|
||||
ad_interface signal offload0_mem_reset output 1 reset
|
||||
ad_interface signal offload0_enable output 1 enable
|
||||
ad_interface signal offload0_enabled input 1 enabled
|
||||
|
||||
add_interface offload_sync axi4stream end
|
||||
add_interface_port offload_sync offload_sync_valid tvalid input 1
|
||||
add_interface_port offload_sync offload_sync_ready tready output 1
|
||||
add_interface_port offload_sync offload_sync_data tdata input 8
|
||||
|
||||
set_interface_property offload_sync associatedClock if_spi_clk
|
||||
set_interface_property offload_sync associatedReset if_spi_resetn
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,304 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ip
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create axi_spi_engine
|
||||
adi_ip_files axi_spi_engine [list \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"axi_spi_engine_constr.ttcl" \
|
||||
"axi_spi_engine.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties axi_spi_engine
|
||||
adi_ip_ttcl axi_spi_engine "axi_spi_engine_constr.ttcl"
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
]
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi} [ipx::current_core]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "spi_engine_ctrl" "master" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{
|
||||
{"cmd_ready" "CMD_READY"} \
|
||||
{"cmd_valid" "CMD_VALID"} \
|
||||
{"cmd_data" "CMD_DATA"} \
|
||||
{"sdo_data_ready" "SDO_READY"} \
|
||||
{"sdo_data_valid" "SDO_VALID"} \
|
||||
{"sdo_data" "SDO_DATA"} \
|
||||
{"sdi_data_ready" "SDI_READY"} \
|
||||
{"sdi_data_valid" "SDI_VALID"} \
|
||||
{"sdi_data" "SDI_DATA"} \
|
||||
{"sync_ready" "SYNC_READY"} \
|
||||
{"sync_valid" "SYNC_VALID"} \
|
||||
{"sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master"
|
||||
|
||||
adi_add_bus "spi_engine_offload_ctrl0" "master" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
|
||||
{ \
|
||||
{ "offload0_cmd_wr_en" "CMD_WR_EN"} \
|
||||
{ "offload0_cmd_wr_data" "CMD_WR_DATA"} \
|
||||
{ "offload0_sdo_wr_en" "SDO_WR_EN"} \
|
||||
{ "offload0_sdo_wr_data" "SDO_WR_DATA"} \
|
||||
{ "offload0_enable" "ENABLE"} \
|
||||
{ "offload0_enabled" "ENABLED"} \
|
||||
{ "offload0_mem_reset" "MEM_RESET"} \
|
||||
{ "offload_sync_ready" "SYNC_READY"} \
|
||||
{ "offload_sync_valid" "SYNC_VALID"} \
|
||||
{ "offload_sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn"
|
||||
|
||||
foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} {
|
||||
set_property DRIVER_VALUE "0" [ipx::get_ports $port]
|
||||
}
|
||||
adi_set_bus_dependency "spi_engine_offload_ctrl0" "spi_engine_offload_ctrl0" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OFFLOAD')) > 0)"
|
||||
|
||||
adi_set_bus_dependency "s_axi" "s_axi" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 0)"
|
||||
|
||||
adi_set_ports_dependency "up_clk" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_rstn" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_wreq" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_waddr" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_wdata" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_rreq" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_raddr" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_wack" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_rdata" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
adi_set_ports_dependency "up_rack" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)"
|
||||
|
||||
## Parameter validations
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
## ID
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "255" \
|
||||
] \
|
||||
[ipx::get_user_parameters ID -of_objects $cc]
|
||||
|
||||
## CMD_FIFO_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters CMD_FIFO_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## SYNC_FIFO_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters SYNC_FIFO_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## SDO_FIFO_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDO_FIFO_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## SDI_FIFO_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDI_FIFO_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## MM_IF_TYPE
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "pairs" \
|
||||
"value_validation_pairs" { \
|
||||
"AXI4 Memory Mapped" "0" \
|
||||
"ADI uP FIFO" "1" \
|
||||
} \
|
||||
] \
|
||||
[ipx::get_user_parameters MM_IF_TYPE -of_objects $cc]
|
||||
|
||||
## ASYNC_SPI_CLK
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc]
|
||||
|
||||
## NUM_OFFLOAD
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OFFLOAD -of_objects $cc]
|
||||
|
||||
## OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## DATA_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "8" \
|
||||
"value_validation_range_maximum" "256" \
|
||||
] \
|
||||
[ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
|
||||
## NUM_OF_SDI
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
|
||||
## Customize IP Layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create general configuration page
|
||||
ipgui::add_page -name {AXI SPI Engine soft-controller} -component [ipx::current_core] -display_name {AXI SPI Engine soft-controller}
|
||||
set page0 [ipgui::get_pagespec -name "AXI SPI Engine soft-controller" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration" ]
|
||||
|
||||
ipgui::add_param -name "ID" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Core ID" \
|
||||
"tooltip" "\[ID\] Core instance ID" \
|
||||
] [ipgui::get_guiparamspec -name "ID" -component $cc]
|
||||
|
||||
ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Parallel data width" \
|
||||
"tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO lines" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
ipgui::add_param -name "MM_IF_TYPE" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Memory Mapped Interface Type" \
|
||||
"tooltip" "\[MM_IF_TYPE\] Define the memory mapped interface type" \
|
||||
] [ipgui::get_guiparamspec -name "MM_IF_TYPE" -component $cc]
|
||||
|
||||
ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Asynchronous core clock" \
|
||||
"tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \
|
||||
] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc]
|
||||
|
||||
## Command stream FIFO depth configuration
|
||||
set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \
|
||||
-parent $page0 -display_name "Command stream FIFO configuration" ]
|
||||
|
||||
ipgui::add_param -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Command FIFO address width" \
|
||||
"tooltip" "\[CMD_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "SYNC FIFO address width" \
|
||||
"tooltip" "\[SYNC_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "MOSI FIFO address width" \
|
||||
"tooltip" "\[SDO_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "MISO FIFO address width" \
|
||||
"tooltip" "\[SDI_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
## Offload module(s) configuration
|
||||
set offload_group [ipgui::add_group -name "Offload module configuration" -component $cc \
|
||||
-parent $page0 -display_name "Offload module configuration" ]
|
||||
|
||||
ipgui::add_param -name "NUM_OFFLOAD" -component $cc -parent $offload_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of offloads" \
|
||||
"tooltip" "\[NUM_OFFLOAD\] Number of offloads" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OFFLOAD" -component $cc]
|
||||
|
||||
ipgui::add_param -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Offload command FIFO address width" \
|
||||
"tooltip" "\[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc]
|
||||
set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
ipgui::add_param -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Offload MOSI FIFO address width" \
|
||||
"tooltip" "\[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc]
|
||||
set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files $cc
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,3 @@
|
||||
# This file is automatically written. Do not modify.
|
||||
proc gen_USERPARAMETER_OFFLOAD0_CMD_MEM_ADDRESS_WIDTH_ENABLEMENT {NUM_OFFLOAD } {expr $NUM_OFFLOAD > 0}
|
||||
proc gen_USERPARAMETER_OFFLOAD0_SDO_MEM_ADDRESS_WIDTH_ENABLEMENT {NUM_OFFLOAD } {expr $NUM_OFFLOAD > 0}
|
||||
@@ -0,0 +1,289 @@
|
||||
|
||||
# Loading additional proc with user specified bodies to compute parameter values.
|
||||
source [file join [file dirname [file dirname [info script]]] gui/axi_spi_engine_v1_0.gtcl]
|
||||
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set AXI_SPI_Engine_soft-controller [ipgui::add_page $IPINST -name "AXI SPI Engine soft-controller"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${AXI_SPI_Engine_soft-controller}]
|
||||
set ID [ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ID] Core instance ID} ${ID}
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
set MM_IF_TYPE [ipgui::add_param $IPINST -name "MM_IF_TYPE" -parent ${General_Configuration}]
|
||||
set_property tooltip {[MM_IF_TYPE] Define the memory mapped interface type} ${MM_IF_TYPE}
|
||||
set ASYNC_SPI_CLK [ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_SPI_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_SPI_CLK}
|
||||
|
||||
#Adding Group
|
||||
set Command_stream_FIFO_configuration [ipgui::add_group $IPINST -name "Command stream FIFO configuration" -parent ${AXI_SPI_Engine_soft-controller}]
|
||||
set CMD_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "CMD_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[CMD_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${CMD_FIFO_ADDRESS_WIDTH}
|
||||
set SYNC_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SYNC_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SYNC_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SYNC_FIFO_ADDRESS_WIDTH}
|
||||
set SDO_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDO_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDO_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDO_FIFO_ADDRESS_WIDTH}
|
||||
set SDI_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDI_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDI_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDI_FIFO_ADDRESS_WIDTH}
|
||||
|
||||
#Adding Group
|
||||
set Offload_module_configuration [ipgui::add_group $IPINST -name "Offload module configuration" -parent ${AXI_SPI_Engine_soft-controller}]
|
||||
set NUM_OFFLOAD [ipgui::add_param $IPINST -name "NUM_OFFLOAD" -parent ${Offload_module_configuration}]
|
||||
set_property tooltip {[NUM_OFFLOAD] Number of offloads} ${NUM_OFFLOAD}
|
||||
set OFFLOAD0_CMD_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -parent ${Offload_module_configuration}]
|
||||
set_property tooltip {[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}
|
||||
set OFFLOAD0_SDO_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -parent ${Offload_module_configuration}]
|
||||
set_property tooltip {[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to update OFFLOAD0_CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
|
||||
set OFFLOAD0_CMD_MEM_ADDRESS_WIDTH ${PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}
|
||||
set NUM_OFFLOAD ${PARAM_VALUE.NUM_OFFLOAD}
|
||||
set values(NUM_OFFLOAD) [get_property value $NUM_OFFLOAD]
|
||||
if { [gen_USERPARAMETER_OFFLOAD0_CMD_MEM_ADDRESS_WIDTH_ENABLEMENT $values(NUM_OFFLOAD)] } {
|
||||
set_property enabled true $OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
} else {
|
||||
set_property enabled false $OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to update OFFLOAD0_SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
|
||||
set OFFLOAD0_SDO_MEM_ADDRESS_WIDTH ${PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}
|
||||
set NUM_OFFLOAD ${PARAM_VALUE.NUM_OFFLOAD}
|
||||
set values(NUM_OFFLOAD) [get_property value $NUM_OFFLOAD]
|
||||
if { [gen_USERPARAMETER_OFFLOAD0_SDO_MEM_ADDRESS_WIDTH_ENABLEMENT $values(NUM_OFFLOAD)] } {
|
||||
set_property enabled true $OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
} else {
|
||||
set_property enabled false $OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate OFFLOAD0_SDO_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to validate ASYNC_SPI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_0 { PARAM_VALUE.CFG_INFO_0 } {
|
||||
# Procedure called to update CFG_INFO_0 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_0 { PARAM_VALUE.CFG_INFO_0 } {
|
||||
# Procedure called to validate CFG_INFO_0
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_1 { PARAM_VALUE.CFG_INFO_1 } {
|
||||
# Procedure called to update CFG_INFO_1 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_1 { PARAM_VALUE.CFG_INFO_1 } {
|
||||
# Procedure called to validate CFG_INFO_1
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_2 { PARAM_VALUE.CFG_INFO_2 } {
|
||||
# Procedure called to update CFG_INFO_2 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_2 { PARAM_VALUE.CFG_INFO_2 } {
|
||||
# Procedure called to validate CFG_INFO_2
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CFG_INFO_3 { PARAM_VALUE.CFG_INFO_3 } {
|
||||
# Procedure called to update CFG_INFO_3 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CFG_INFO_3 { PARAM_VALUE.CFG_INFO_3 } {
|
||||
# Procedure called to validate CFG_INFO_3
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update CMD_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate CMD_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MM_IF_TYPE { PARAM_VALUE.MM_IF_TYPE } {
|
||||
# Procedure called to update MM_IF_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MM_IF_TYPE { PARAM_VALUE.MM_IF_TYPE } {
|
||||
# Procedure called to validate MM_IF_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OFFLOAD { PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to update NUM_OFFLOAD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OFFLOAD { PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to validate NUM_OFFLOAD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDI_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDI_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDO_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDO_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SYNC_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SYNC_FIFO_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MM_IF_TYPE { MODELPARAM_VALUE.MM_IF_TYPE PARAM_VALUE.MM_IF_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MM_IF_TYPE}] ${MODELPARAM_VALUE.MM_IF_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OFFLOAD { MODELPARAM_VALUE.NUM_OFFLOAD PARAM_VALUE.NUM_OFFLOAD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OFFLOAD}] ${MODELPARAM_VALUE.NUM_OFFLOAD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_0 { MODELPARAM_VALUE.CFG_INFO_0 PARAM_VALUE.CFG_INFO_0 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_0}] ${MODELPARAM_VALUE.CFG_INFO_0}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_1 { MODELPARAM_VALUE.CFG_INFO_1 PARAM_VALUE.CFG_INFO_1 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_1}] ${MODELPARAM_VALUE.CFG_INFO_1}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_2 { MODELPARAM_VALUE.CFG_INFO_2 PARAM_VALUE.CFG_INFO_2 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_2}] ${MODELPARAM_VALUE.CFG_INFO_2}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CFG_INFO_3 { MODELPARAM_VALUE.CFG_INFO_3 PARAM_VALUE.CFG_INFO_3 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CFG_INFO_3}] ${MODELPARAM_VALUE.CFG_INFO_3}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user