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initial commit, add dds_par module

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josh
2024-01-15 09:36:08 +08:00
commit 315a673005
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adi_library/spi_engine/axi_spi_engine/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_spi_engine
GENERIC_DEPS += ../../common/ad_rst.v
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += axi_spi_engine.v
XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += axi_spi_engine_constr.ttcl
XILINX_DEPS += axi_spi_engine_ip.tcl
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_cdc
INTEL_DEPS += ../../common/ad_mem.v
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo_address_generator.v
INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../../util_cdc/sync_gray.v
INTEL_DEPS += axi_spi_engine_constr.sdc
INTEL_DEPS += axi_spi_engine_hw.tcl
include ../../scripts/library.mk