initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := spi_engine_interconnect
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GENERIC_DEPS += spi_engine_interconnect.v
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XILINX_DEPS += spi_engine_interconnect_ip.tcl
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
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INTEL_DEPS += spi_engine_interconnect_hw.tcl
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include ../../scripts/library.mk
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,144 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
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||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
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||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
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||||
//
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||||
// Redistribution and use of source or resulting binaries, with or without modification
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||||
// of this file, are permitted under one of the following two license terms:
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||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
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||||
// of this repository (LICENSE_GPL2), and also online at:
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||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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||||
// This will allow to generate bit files and not release the source code,
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||||
// as long as it attaches to an ADI device.
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||||
//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module spi_engine_interconnect #(
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parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
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parameter NUM_OF_SDI = 1
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) (
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input clk,
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input resetn,
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output m_cmd_valid,
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input m_cmd_ready,
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output [15:0] m_cmd_data,
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output m_sdo_valid,
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input m_sdo_ready,
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output [(DATA_WIDTH-1):0] m_sdo_data,
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input m_sdi_valid,
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output m_sdi_ready,
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input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
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input m_sync_valid,
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output m_sync_ready,
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input [7:0] m_sync,
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input s0_cmd_valid,
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output s0_cmd_ready,
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input [15:0] s0_cmd_data,
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input s0_sdo_valid,
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output s0_sdo_ready,
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input [(DATA_WIDTH-1):0] s0_sdo_data,
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output s0_sdi_valid,
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input s0_sdi_ready,
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output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
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output s0_sync_valid,
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input s0_sync_ready,
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output [7:0] s0_sync,
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input s1_cmd_valid,
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output s1_cmd_ready,
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input [15:0] s1_cmd_data,
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input s1_sdo_valid,
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output s1_sdo_ready,
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input [(DATA_WIDTH-1):0] s1_sdo_data,
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output s1_sdi_valid,
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input s1_sdi_ready,
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output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
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output s1_sync_valid,
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input s1_sync_ready,
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output [7:0] s1_sync
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);
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reg s_active = 1'b0;
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reg idle = 1'b1;
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`define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1))
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assign m_cmd_data = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data;
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assign m_cmd_valid = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid);
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assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0);
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assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready);
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assign m_sdo_data = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data;
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assign m_sdo_valid = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid);
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assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0);
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assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready);
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assign s0_sdi_data = m_sdi_data;
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assign s1_sdi_data = m_sdi_data;
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assign m_sdi_ready = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready);
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assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0);
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assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid);
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assign s0_sync = m_sync;
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assign s1_sync = m_sync;
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assign m_sync_ready = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready);
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assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
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assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
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always @(posedge clk) begin
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if (idle == 1'b1) begin
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if (s0_cmd_valid)
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s_active <= 1'b0;
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else if (s1_cmd_valid)
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s_active <= 1'b1;
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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idle <= 1'b1;
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end else begin
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if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
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idle <= 1'b1;
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end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
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idle <= 1'b0;
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end
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end
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end
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endmodule
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@@ -0,0 +1,399 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
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<!-- -->
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||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr">
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||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="d07593d6329248f7b3897d72eb22855e"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/spi_engine_interconnect.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="spi_engine_interconnect"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,150 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create spi_engine_interconnect {SPI Engine Interconnect} p_elaboration
|
||||
ad_ip_files spi_engine_interconnect [list\
|
||||
spi_engine_interconnect.v]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter DATA_WIDTH INTEGER 8
|
||||
ad_ip_parameter NUM_OF_SDI INTEGER 1
|
||||
|
||||
proc p_elaboration {} {
|
||||
|
||||
set data_width [get_parameter_value DATA_WIDTH]
|
||||
set num_of_sdi [get_parameter_value NUM_OF_SDI]
|
||||
|
||||
# clock and reset interface
|
||||
|
||||
ad_interface clock clk input 1
|
||||
ad_interface reset resetn input 1 if_clk
|
||||
|
||||
# command master interface
|
||||
|
||||
add_interface m_cmd axi4stream start
|
||||
add_interface_port m_cmd m_cmd_ready tready input 1
|
||||
add_interface_port m_cmd m_cmd_valid tvalid output 1
|
||||
add_interface_port m_cmd m_cmd_data tdata output 16
|
||||
|
||||
set_interface_property m_cmd associatedClock if_clk
|
||||
set_interface_property m_cmd associatedReset if_resetn
|
||||
|
||||
# SDO data master interface
|
||||
|
||||
add_interface m_sdo axi4stream start
|
||||
add_interface_port m_sdo m_sdo_ready tready input 1
|
||||
add_interface_port m_sdo m_sdo_valid tvalid output 1
|
||||
add_interface_port m_sdo m_sdo_data tdata output $data_width
|
||||
|
||||
set_interface_property m_sdo associatedClock if_clk
|
||||
set_interface_property m_sdo associatedReset if_resetn
|
||||
|
||||
# SDI data master interface
|
||||
|
||||
add_interface m_sdi axi4stream end
|
||||
add_interface_port m_sdi m_sdi_ready tready output 1
|
||||
add_interface_port m_sdi m_sdi_valid tvalid input 1
|
||||
add_interface_port m_sdi m_sdi_data tdata input [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property m_sdi associatedClock if_clk
|
||||
set_interface_property m_sdi associatedReset if_resetn
|
||||
|
||||
# SYNC master interface
|
||||
|
||||
add_interface m_sync axi4stream end
|
||||
add_interface_port m_sync m_sync_valid tvalid input 1
|
||||
add_interface_port m_sync m_sync_ready tready output 1
|
||||
add_interface_port m_sync m_sync tdata input 8
|
||||
|
||||
set_interface_property m_sync associatedClock if_clk
|
||||
set_interface_property m_sync associatedReset if_resetn
|
||||
|
||||
# command slave0 interface
|
||||
|
||||
add_interface s0_cmd axi4stream end
|
||||
add_interface_port s0_cmd s0_cmd_ready tready output 1
|
||||
add_interface_port s0_cmd s0_cmd_valid tvalid input 1
|
||||
add_interface_port s0_cmd s0_cmd_data tdata input 16
|
||||
|
||||
set_interface_property s0_cmd associatedClock if_clk
|
||||
set_interface_property s0_cmd associatedReset if_resetn
|
||||
|
||||
# SDO data slave0 interface
|
||||
|
||||
add_interface s0_sdo axi4stream end
|
||||
add_interface_port s0_sdo s0_sdo_ready tready output 1
|
||||
add_interface_port s0_sdo s0_sdo_valid tvalid input 1
|
||||
add_interface_port s0_sdo s0_sdo_data tdata input $data_width
|
||||
|
||||
set_interface_property s0_sdo associatedClock if_clk
|
||||
set_interface_property s0_sdo associatedReset if_resetn
|
||||
|
||||
# SDI data slave0 interface
|
||||
|
||||
add_interface s0_sdi axi4stream start
|
||||
add_interface_port s0_sdi s0_sdi_ready tready input 1
|
||||
add_interface_port s0_sdi s0_sdi_valid tvalid output 1
|
||||
add_interface_port s0_sdi s0_sdi_data tdata output [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property s0_sdi associatedClock if_clk
|
||||
set_interface_property s0_sdi associatedReset if_resetn
|
||||
|
||||
# SYNC slave0 interface
|
||||
|
||||
add_interface s0_sync axi4stream start
|
||||
add_interface_port s0_sync s0_sync_valid tvalid output 1
|
||||
add_interface_port s0_sync s0_sync_ready tready input 1
|
||||
add_interface_port s0_sync s0_sync tdata output 8
|
||||
|
||||
set_interface_property s0_sync associatedClock if_clk
|
||||
set_interface_property s0_sync associatedReset if_resetn
|
||||
|
||||
# command slave1 interface
|
||||
|
||||
add_interface s1_cmd axi4stream end
|
||||
add_interface_port s1_cmd s1_cmd_ready tready output 1
|
||||
add_interface_port s1_cmd s1_cmd_valid tvalid input 1
|
||||
add_interface_port s1_cmd s1_cmd_data tdata input 16
|
||||
|
||||
set_interface_property s1_cmd associatedClock if_clk
|
||||
set_interface_property s1_cmd associatedReset if_resetn
|
||||
|
||||
# SDO data slave1 interface
|
||||
|
||||
add_interface s1_sdo axi4stream end
|
||||
add_interface_port s1_sdo s1_sdo_ready tready output 1
|
||||
add_interface_port s1_sdo s1_sdo_valid tvalid input 1
|
||||
add_interface_port s1_sdo s1_sdo_data tdata input $data_width
|
||||
|
||||
set_interface_property s1_sdo associatedClock if_clk
|
||||
set_interface_property s1_sdo associatedReset if_resetn
|
||||
|
||||
# SDI data slave1 interface
|
||||
|
||||
add_interface s1_sdi axi4stream start
|
||||
add_interface_port s1_sdi s1_sdi_ready tready input 1
|
||||
add_interface_port s1_sdi s1_sdi_valid tvalid output 1
|
||||
add_interface_port s1_sdi s1_sdi_data tdata output [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property s1_sdi associatedClock if_clk
|
||||
set_interface_property s1_sdi associatedReset if_resetn
|
||||
|
||||
# SYNC slave1 interface
|
||||
|
||||
add_interface s1_sync axi4stream start
|
||||
add_interface_port s1_sync s1_sync_valid tvalid output 1
|
||||
add_interface_port s1_sync s1_sync_ready tready input 1
|
||||
add_interface_port s1_sync s1_sync tdata output 8
|
||||
|
||||
set_interface_property s1_sync associatedClock if_clk
|
||||
set_interface_property s1_sync associatedReset if_resetn
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,111 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create spi_engine_interconnect
|
||||
adi_ip_files spi_engine_interconnect [list \
|
||||
"spi_engine_interconnect.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite spi_engine_interconnect
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/interconnect} [ipx::current_core]
|
||||
|
||||
# Remove all inferred interfaces
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "m_ctrl" "master" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{ \
|
||||
{"m_cmd_ready" "CMD_READY"} \
|
||||
{"m_cmd_valid" "CMD_VALID"} \
|
||||
{"m_cmd_data" "CMD_DATA"} \
|
||||
{"m_sdo_ready" "SDO_READY"} \
|
||||
{"m_sdo_valid" "SDO_VALID"} \
|
||||
{"m_sdo_data" "SDO_DATA"} \
|
||||
{"m_sdi_ready" "SDI_READY"} \
|
||||
{"m_sdi_valid" "SDI_VALID"} \
|
||||
{"m_sdi_data" "SDI_DATA"} \
|
||||
{"m_sync_ready" "SYNC_READY"} \
|
||||
{"m_sync_valid" "SYNC_VALID"} \
|
||||
{"m_sync" "SYNC_DATA"} \
|
||||
}
|
||||
adi_add_bus_clock "clk" "m_ctrl" "resetn"
|
||||
|
||||
foreach prefix [list "s0" "s1"] {
|
||||
adi_add_bus [format "%s_ctrl" $prefix] "slave" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
[list \
|
||||
[list [format "%s_cmd_ready" $prefix] "CMD_READY"] \
|
||||
[list [format "%s_cmd_valid" $prefix] "CMD_VALID"] \
|
||||
[list [format "%s_cmd_data" $prefix] "CMD_DATA"] \
|
||||
[list [format "%s_sdo_ready" $prefix] "SDO_READY"] \
|
||||
[list [format "%s_sdo_valid" $prefix] "SDO_VALID"] \
|
||||
[list [format "%s_sdo_data" $prefix] "SDO_DATA"] \
|
||||
[list [format "%s_sdi_ready" $prefix] "SDI_READY"] \
|
||||
[list [format "%s_sdi_valid" $prefix] "SDI_VALID"] \
|
||||
[list [format "%s_sdi_data" $prefix] "SDI_DATA"] \
|
||||
[list [format "%s_sync_ready" $prefix] "SYNC_READY"] \
|
||||
[list [format "%s_sync_valid" $prefix] "SYNC_VALID"] \
|
||||
[list [format "%s_sync" $prefix] "SYNC_DATA"] \
|
||||
]
|
||||
adi_add_bus_clock "clk" [format "%s_ctrl" $prefix] "resetn"
|
||||
}
|
||||
|
||||
## Parameter validations
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
## DATA_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "8" \
|
||||
"value_validation_range_maximum" "256" \
|
||||
] \
|
||||
[ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
|
||||
## NUM_OF_SDI
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
|
||||
## Customize IP Layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create general configuration page
|
||||
ipgui::add_page -name {SPI Engine interconnect} -component [ipx::current_core] -display_name {SPI Engine interconnect}
|
||||
set page0 [ipgui::get_pagespec -name "SPI Engine interconnect" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration" ]
|
||||
|
||||
ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Parallel data width" \
|
||||
"tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO lines" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files $cc
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,45 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_interconnect [ipgui::add_page $IPINST -name "SPI Engine interconnect"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_interconnect}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user