initial commit, add dds_par module
This commit is contained in:
@@ -0,0 +1,24 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := spi_engine_offload
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GENERIC_DEPS += spi_engine_offload.v
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XILINX_DEPS += spi_engine_offload_constr.ttcl
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XILINX_DEPS += spi_engine_offload_ip.tcl
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
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XILINX_LIB_DEPS += util_cdc
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INTEL_DEPS += ../../util_cdc/sync_bits.v
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INTEL_DEPS += spi_engine_offload_hw.tcl
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include ../../scripts/library.mk
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@@ -0,0 +1,954 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
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||||
<spirit:name>spi_engine_offload</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_offload_ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_WR_EN</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_cmd_wr_en</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_WR_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_cmd_wr_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_WR_EN</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_sdo_wr_en</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_WR_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_sdo_wr_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ENABLE</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_enable</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ENABLED</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_enabled</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>MEM_RESET</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_mem_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>status_sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>status_sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>status_sync_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>offload_sdi</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>offload_sdi_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>offload_sdi_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>offload_sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_ctrl_offload_sdi_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_engine_ctrl_offload_sdi_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>spi_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi_engine_ctrl:offload_sdi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_CLOCK.ASSOCIATED_RESET">spi_resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_ctrl_offload_sdi_signal_reset</spirit:name>
|
||||
<spirit:displayName>spi_engine_ctrl_offload_sdi_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>spi_resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_OFFLOAD_SDI_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_engine_offload_ctrl_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_engine_offload_ctrl_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ctrl_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi_engine_offload_ctrl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_offload</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>54da56d5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>spi_engine_offload</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>54da56d5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>9caa5391</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_cmd_wr_en</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_cmd_wr_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_sdo_wr_en</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_sdo_wr_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_enable</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_enabled</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ctrl_mem_reset</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>status_sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>status_sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>status_sync_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>spi_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>spi_resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>trigger</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>offload_sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_SPI_CLK</spirit:name>
|
||||
<spirit:displayName>Async Spi Clk</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_SPI_CLK">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_TRIG</spirit:name>
|
||||
<spirit:displayName>Async Trig</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_TRIG">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CMD_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Cmd Mem Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDO_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Sdo Mem Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Num Of Sdi</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:value>
|
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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<spirit:vendorExtensions>
|
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<xilinx:subCoreRef>
|
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<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0"/>
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</xilinx:subCoreRef>
|
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</spirit:vendorExtensions>
|
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</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>spi_engine_offload_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASYNC_SPI_CLK</spirit:name>
|
||||
<spirit:displayName>Asynchronous core clock</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_SPI_CLK">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASYNC_TRIG</spirit:name>
|
||||
<spirit:displayName>Asynchronous trigger</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_TRIG">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CMD_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Command FIFO address width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDO_MEM_ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>MOSI FIFO address width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Shift register's data width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="8" spirit:maximum="256" spirit:rangeType="long">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Number of MISO lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_SDI" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">spi_engine_offload_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
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<spirit:vendorExtensions>
|
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<xilinx:coreExtensions>
|
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<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
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</xilinx:supportedFamilies>
|
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<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>spi_engine_offload_v1_0</xilinx:displayName>
|
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-14T03:53:04Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
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||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8689cb20"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="2756ddd5"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ae1a9eae"/>
|
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="e2e1ec4a"/>
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</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,304 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module spi_engine_offload #(
|
||||
|
||||
parameter ASYNC_SPI_CLK = 0,
|
||||
parameter ASYNC_TRIG = 0,
|
||||
parameter CMD_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter SDO_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
|
||||
parameter NUM_OF_SDI = 1
|
||||
) (
|
||||
input ctrl_clk,
|
||||
|
||||
input ctrl_cmd_wr_en,
|
||||
input [15:0] ctrl_cmd_wr_data,
|
||||
|
||||
input ctrl_sdo_wr_en,
|
||||
input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
|
||||
|
||||
input ctrl_enable,
|
||||
output ctrl_enabled,
|
||||
input ctrl_mem_reset,
|
||||
|
||||
output status_sync_valid,
|
||||
input status_sync_ready,
|
||||
output [7:0] status_sync_data,
|
||||
|
||||
input spi_clk,
|
||||
input spi_resetn,
|
||||
|
||||
input trigger,
|
||||
|
||||
output cmd_valid,
|
||||
input cmd_ready,
|
||||
output [15:0] cmd,
|
||||
|
||||
output sdo_data_valid,
|
||||
input sdo_data_ready,
|
||||
output [(DATA_WIDTH-1):0] sdo_data,
|
||||
|
||||
input sdi_data_valid,
|
||||
output sdi_data_ready,
|
||||
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
|
||||
|
||||
input sync_valid,
|
||||
output sync_ready,
|
||||
input [7:0] sync_data,
|
||||
|
||||
output offload_sdi_valid,
|
||||
input offload_sdi_ready,
|
||||
output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
|
||||
);
|
||||
|
||||
reg spi_active = 1'b0;
|
||||
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
|
||||
|
||||
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
|
||||
reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
|
||||
|
||||
wire [15:0] cmd_int_s;
|
||||
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
|
||||
wire spi_enable;
|
||||
|
||||
assign cmd_valid = spi_active;
|
||||
assign sdo_data_valid = spi_active;
|
||||
|
||||
assign offload_sdi_valid = sdi_data_valid;
|
||||
|
||||
// we don't want to block the SDI interface after disabling the module
|
||||
// so just assert the SDI_READY if the sink module (DMA) is disabled
|
||||
assign sdi_data_ready = (spi_enable) ? offload_sdi_ready : 1'b1;
|
||||
|
||||
assign offload_sdi_data = sdi_data;
|
||||
|
||||
assign cmd_int_s = cmd_mem[spi_cmd_rd_addr];
|
||||
assign sdo_data = sdo_mem[spi_sdo_rd_addr];
|
||||
|
||||
/* SYNC ID counter. The offload module increments the sync_id on each
|
||||
* transaction. The initial value of the sync_id is the value of the last
|
||||
* sync_id command loaded into the command buffer.
|
||||
*/
|
||||
|
||||
reg [ 7:0] ctrl_sync_id_init = 8'b0;
|
||||
reg ctrl_sync_id_load = 1'b0;
|
||||
reg [ 7:0] spi_sync_id_counter = 8'b0;
|
||||
|
||||
wire [ 7:0] spi_sync_id_init_s;
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset == 1'b1) begin
|
||||
ctrl_sync_id_init <= 8'b0;
|
||||
ctrl_sync_id_load <= 1'b0;
|
||||
end else begin
|
||||
if (ctrl_cmd_wr_en && (ctrl_cmd_wr_data[15:8] == 8'h30)) begin
|
||||
ctrl_sync_id_init <= ctrl_cmd_wr_data;
|
||||
ctrl_sync_id_load <= 1'b1;
|
||||
end else begin
|
||||
ctrl_sync_id_load <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire spi_sync_id_load_s;
|
||||
|
||||
sync_event #(
|
||||
.NUM_OF_EVENTS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_sync_id_load (
|
||||
.in_clk (ctrl_clk),
|
||||
.in_event(ctrl_sync_id_load),
|
||||
.out_clk(spi_clk),
|
||||
.out_event(spi_sync_id_load_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(8),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_sync_id (
|
||||
.in_bits(ctrl_sync_id_init),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_sync_id_init_s));
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (spi_resetn == 1'b0) begin
|
||||
spi_sync_id_counter <= 8'b0;
|
||||
end else begin
|
||||
if (spi_sync_id_load_s) begin
|
||||
spi_sync_id_counter <= spi_sync_id_init_s;
|
||||
end else if(cmd_valid && cmd_ready && (cmd[15:8] == 8'h30)) begin
|
||||
spi_sync_id_counter <= spi_sync_id_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cmd = (cmd_int_s[15:8] == 8'h30) ? {cmd_int_s[15:8], spi_sync_id_counter} : cmd_int_s;
|
||||
|
||||
/*
|
||||
* Forwarded SYNC interface, this can be used to monitor the state of the
|
||||
* offload command sequence through SPI Engine regmap
|
||||
*/
|
||||
|
||||
assign status_sync_data = sync_data;
|
||||
assign status_sync_valid = sync_valid;
|
||||
assign sync_ready = status_sync_ready;
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
/*
|
||||
* The synchronization circuit takes care that there are no glitches on the
|
||||
* ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
|
||||
* asserted, but only deasserted once the signal has been synchronized back from
|
||||
* the SPI domain. This makes sure that we can't end up in a state where the
|
||||
* enable signal in the SPI domain is asserted, but neither enable nor enabled
|
||||
* is asserted in the control domain.
|
||||
*/
|
||||
|
||||
reg ctrl_do_enable = 1'b0;
|
||||
wire ctrl_is_enabled;
|
||||
reg spi_enabled = 1'b0;
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_enable == 1'b1) begin
|
||||
ctrl_do_enable <= 1'b1;
|
||||
end else if (ctrl_is_enabled == 1'b1) begin
|
||||
ctrl_do_enable <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
spi_enabled <= spi_enable | spi_active;
|
||||
end
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enable (
|
||||
.in_bits(ctrl_do_enable),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enabled (
|
||||
.in_bits(spi_enabled),
|
||||
.out_clk(ctrl_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(ctrl_is_enabled));
|
||||
|
||||
end else begin
|
||||
assign spi_enable = ctrl_enable;
|
||||
assign ctrl_enabled = spi_enable | spi_active;
|
||||
end endgenerate
|
||||
|
||||
assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
|
||||
|
||||
wire trigger_s;
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_TRIG)
|
||||
) i_sync_trigger (
|
||||
.in_bits(trigger),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(trigger_s));
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (spi_resetn == 1'b0) begin
|
||||
spi_active <= 1'b0;
|
||||
end else begin
|
||||
if (spi_active == 1'b0) begin
|
||||
// start offload when we have a valid trigger, offload is enabled and
|
||||
// the DMA is enabled
|
||||
if (trigger_s == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1)
|
||||
spi_active <= 1'b1;
|
||||
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
|
||||
spi_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (cmd_valid == 1'b0) begin
|
||||
spi_cmd_rd_addr <= 'h00;
|
||||
end else if (cmd_ready == 1'b1) begin
|
||||
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (spi_active == 1'b0) begin
|
||||
spi_sdo_rd_addr <= 'h00;
|
||||
end else if (sdo_data_ready == 1'b1) begin
|
||||
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset == 1'b1)
|
||||
ctrl_cmd_wr_addr <= 'h00;
|
||||
else if (ctrl_cmd_wr_en == 1'b1)
|
||||
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_cmd_wr_en == 1'b1)
|
||||
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset == 1'b1)
|
||||
ctrl_sdo_wr_addr <= 'h00;
|
||||
else if (ctrl_sdo_wr_en == 1'b1)
|
||||
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_sdo_wr_en == 1'b1)
|
||||
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,400 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="30b4a7c406754ea493b787146654d616"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/spi_engine_offload.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/spi_engine_offload_constr.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="spi_engine_offload"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,36 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
|
||||
|
||||
<: if { $async_spi_clk } { :>
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
|
||||
[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_out/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_in/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enable/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enabled/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
set_false_path -quiet \
|
||||
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_trigger/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
|
||||
|
||||
<: } :>
|
||||
@@ -0,0 +1,117 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create spi_engine_offload {SPI Engine Offload} p_elaboration
|
||||
ad_ip_files spi_engine_offload [list\
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
spi_engine_offload.v]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter ASYNC_SPI_CLK INTEGER 0
|
||||
ad_ip_parameter ASYNC_TRIG INTEGER 0
|
||||
ad_ip_parameter CMD_MEM_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter SDO_MEM_ADDRESS_WIDTH INTEGER 4
|
||||
ad_ip_parameter DATA_WIDTH INTEGER 8
|
||||
ad_ip_parameter NUM_OF_SDI INTEGER 1
|
||||
|
||||
proc p_elaboration {} {
|
||||
|
||||
set data_width [get_parameter_value DATA_WIDTH]
|
||||
set num_of_sdi [get_parameter_value NUM_OF_SDI]
|
||||
|
||||
# control interface
|
||||
|
||||
ad_interface clock ctrl_clk input 1
|
||||
ad_interface reset spi_resetn input 1 if_spi_clk
|
||||
|
||||
add_interface ctrl_cmd_wr conduit end
|
||||
add_interface_port ctrl_cmd_wr ctrl_cmd_wr_en wre input 1
|
||||
add_interface_port ctrl_cmd_wr ctrl_cmd_wr_data data input 16
|
||||
|
||||
set_interface_property ctrl_cmd_wr associatedClock if_ctrl_clk
|
||||
set_interface_property ctrl_cmd_wr associatedReset none
|
||||
|
||||
add_interface ctrl_sdo_wr conduit end
|
||||
add_interface_port ctrl_sdo_wr ctrl_sdo_wr_en wre input 1
|
||||
add_interface_port ctrl_sdo_wr ctrl_sdo_wr_data data input $data_width
|
||||
|
||||
set_interface_property ctrl_sdo_wr associatedClock if_ctrl_clk
|
||||
set_interface_property ctrl_sdo_wr associatedReset none
|
||||
|
||||
ad_interface signal ctrl_enable input 1 enable
|
||||
ad_interface signal ctrl_enabled output 1 enabled
|
||||
ad_interface signal ctrl_mem_reset input 1 reset
|
||||
|
||||
add_interface status_sync axi4stream start
|
||||
add_interface_port status_sync status_sync_valid tvalid output 1
|
||||
add_interface_port status_sync status_sync_ready tready input 1
|
||||
add_interface_port status_sync status_sync_data tdata output 8
|
||||
|
||||
set_interface_property status_sync associatedClock if_spi_clk
|
||||
set_interface_property status_sync associatedReset if_spi_resetn
|
||||
|
||||
# SPI Engine interfaces
|
||||
|
||||
ad_interface clock spi_clk input 1
|
||||
ad_interface resetn spi_resetn input 1 if_spi_clk
|
||||
|
||||
ad_interface signal trigger input 1 if_pwm
|
||||
|
||||
## command interface
|
||||
|
||||
add_interface cmd axi4stream start
|
||||
add_interface_port cmd cmd_valid tvalid output 1
|
||||
add_interface_port cmd cmd_ready tready input 1
|
||||
add_interface_port cmd cmd tdata output 16
|
||||
|
||||
set_interface_property cmd associatedClock if_spi_clk
|
||||
set_interface_property cmd associatedReset if_spi_resetn
|
||||
|
||||
## SDO data interface
|
||||
|
||||
add_interface sdo_data axi4stream start
|
||||
add_interface_port sdo_data sdo_data_valid tvalid output 1
|
||||
add_interface_port sdo_data sdo_data_ready tready input 1
|
||||
add_interface_port sdo_data sdo_data tdata output $data_width
|
||||
|
||||
set_interface_property sdo_data associatedClock if_spi_clk
|
||||
set_interface_property sdo_data associatedReset if_spi_resetn
|
||||
|
||||
## SDI data interface
|
||||
|
||||
add_interface sdi_data axi4stream end
|
||||
add_interface_port sdi_data sdi_data_valid tvalid input 1
|
||||
add_interface_port sdi_data sdi_data_ready tready output 1
|
||||
add_interface_port sdi_data sdi_data tdata input [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property sdi_data associatedClock if_spi_clk
|
||||
set_interface_property sdi_data associatedReset if_spi_resetn
|
||||
|
||||
## SYNC data interface
|
||||
|
||||
add_interface sync axi4stream end
|
||||
add_interface_port sync sync_valid tvalid input 1
|
||||
add_interface_port sync sync_ready tready output 1
|
||||
add_interface_port sync sync_data tdata input 8
|
||||
|
||||
set_interface_property sync associatedClock if_spi_clk
|
||||
set_interface_property sync associatedReset if_spi_resetn
|
||||
|
||||
## Offload SDI data interface
|
||||
|
||||
add_interface offload_sdi axi4stream start
|
||||
add_interface_port offload_sdi offload_sdi_valid tvalid output 1
|
||||
add_interface_port offload_sdi offload_sdi_ready tready input 1
|
||||
add_interface_port offload_sdi offload_sdi_data tdata output [expr $num_of_sdi * $data_width]
|
||||
|
||||
set_interface_property offload_sdi associatedClock if_spi_clk
|
||||
set_interface_property offload_sdi associatedReset if_spi_resetn
|
||||
|
||||
}
|
||||
@@ -0,0 +1,193 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create spi_engine_offload
|
||||
adi_ip_files spi_engine_offload [list \
|
||||
"spi_engine_offload_constr.ttcl" \
|
||||
"spi_engine_offload.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite spi_engine_offload
|
||||
adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl"
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload} [ipx::current_core]
|
||||
|
||||
# Remove all inferred interfaces
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "spi_engine_ctrl" "master" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{
|
||||
{"cmd_ready" "CMD_READY"} \
|
||||
{"cmd_valid" "CMD_VALID"} \
|
||||
{"cmd" "CMD_DATA"} \
|
||||
{"sdo_data_ready" "SDO_READY"} \
|
||||
{"sdo_data_valid" "SDO_VALID"} \
|
||||
{"sdo_data" "SDO_DATA"} \
|
||||
{"sdi_data_ready" "SDI_READY"} \
|
||||
{"sdi_data_valid" "SDI_VALID"} \
|
||||
{"sdi_data" "SDI_DATA"} \
|
||||
{"sync_ready" "SYNC_READY"} \
|
||||
{"sync_valid" "SYNC_VALID"} \
|
||||
{"sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus "spi_engine_offload_ctrl" "slave" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
|
||||
{ \
|
||||
{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
|
||||
{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
|
||||
{ "ctrl_sdo_wr_en" "SDO_WR_EN"} \
|
||||
{ "ctrl_sdo_wr_data" "SDO_WR_DATA"} \
|
||||
{ "ctrl_enable" "ENABLE"} \
|
||||
{ "ctrl_enabled" "ENABLED"} \
|
||||
{ "ctrl_mem_reset" "MEM_RESET"} \
|
||||
{ "status_sync_ready" "SYNC_READY"} \
|
||||
{ "status_sync_valid" "SYNC_VALID"} \
|
||||
{ "status_sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus "offload_sdi" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{ \
|
||||
{"offload_sdi_valid" "TVALID"} \
|
||||
{"offload_sdi_ready" "TREADY"} \
|
||||
{"offload_sdi_data" "TDATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus_clock "spi_clk" "spi_engine_ctrl:offload_sdi" "spi_resetn"
|
||||
adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
|
||||
|
||||
## Parameter validations
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
## ASYNC_SPI_CLK
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc]
|
||||
|
||||
## ASYNC_TRIG
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_user_parameters ASYNC_TRIG -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "false" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters ASYNC_TRIG -of_objects $cc]
|
||||
|
||||
## NUM_OF_SDI
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "8" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_SDI -of_objects $cc]
|
||||
|
||||
## DATA_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "8" \
|
||||
"value_validation_range_maximum" "256" \
|
||||
] \
|
||||
[ipx::get_user_parameters DATA_WIDTH -of_objects $cc]
|
||||
|
||||
## CMD_MEM_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters CMD_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## SDO_MEM_ADDRESS_WIDTH
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "16" \
|
||||
] \
|
||||
[ipx::get_user_parameters SDO_MEM_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
## Customize IP Layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create general configuration page
|
||||
ipgui::add_page -name {SPI Engine RX offload} -component [ipx::current_core] -display_name {SPI Engine RX offload}
|
||||
set page0 [ipgui::get_pagespec -name "SPI Engine RX offload" -component $cc]
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration" ]
|
||||
|
||||
ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Shift register's data width" \
|
||||
"tooltip" "\[DATA_WIDTH\] Define the data interface width"
|
||||
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of MISO lines" \
|
||||
"tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \
|
||||
] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc]
|
||||
|
||||
ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Asynchronous core clock" \
|
||||
"tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \
|
||||
] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc]
|
||||
|
||||
ipgui::add_param -name "ASYNC_TRIG" -component $cc -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Asynchronous trigger" \
|
||||
"tooltip" "\[ASYNC_TRIG\] Set if the external trigger is asynchronous to the core clk" \
|
||||
] [ipgui::get_guiparamspec -name "ASYNC_TRIG" -component $cc]
|
||||
|
||||
## Command stream FIFO depth configuration
|
||||
set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \
|
||||
-parent $page0 -display_name "Command stream FIFO configuration" ]
|
||||
|
||||
ipgui::add_param -name "CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Command FIFO address width" \
|
||||
"tooltip" "\[CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "CMD_MEM_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group
|
||||
set_property -dict [list \
|
||||
"display_name" "MOSI FIFO address width" \
|
||||
"tooltip" "\[SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
|
||||
] [ipgui::get_guiparamspec -name "SDO_MEM_ADDRESS_WIDTH" -component $cc]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files $cc
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,112 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set SPI_Engine_RX_offload [ipgui::add_page $IPINST -name "SPI Engine RX offload"]
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_RX_offload}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}]
|
||||
set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH}
|
||||
set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}]
|
||||
set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI}
|
||||
set ASYNC_SPI_CLK [ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_SPI_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_SPI_CLK}
|
||||
set ASYNC_TRIG [ipgui::add_param $IPINST -name "ASYNC_TRIG" -parent ${General_Configuration}]
|
||||
set_property tooltip {[ASYNC_TRIG] Set if the external trigger is asynchronous to the core clk} ${ASYNC_TRIG}
|
||||
|
||||
#Adding Group
|
||||
set Command_stream_FIFO_configuration [ipgui::add_group $IPINST -name "Command stream FIFO configuration" -parent ${SPI_Engine_RX_offload}]
|
||||
set CMD_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "CMD_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[CMD_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${CMD_MEM_ADDRESS_WIDTH}
|
||||
set SDO_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDO_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}]
|
||||
set_property tooltip {[SDO_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDO_MEM_ADDRESS_WIDTH}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to validate ASYNC_SPI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to update ASYNC_TRIG when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to validate ASYNC_TRIG
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate CMD_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to validate NUM_OF_SDI
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDO_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_TRIG { MODELPARAM_VALUE.ASYNC_TRIG PARAM_VALUE.ASYNC_TRIG } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_TRIG}] ${MODELPARAM_VALUE.ASYNC_TRIG}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user