initial commit, add dds_par module
This commit is contained in:
@@ -0,0 +1,18 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := util_axis_fifo
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GENERIC_DEPS += ../common/ad_mem.v
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GENERIC_DEPS += ../common/ad_mem_asym.v
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GENERIC_DEPS += util_axis_fifo.v
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GENERIC_DEPS += util_axis_fifo_address_generator.v
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XILINX_DEPS += util_axis_fifo_ip.tcl
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XILINX_LIB_DEPS += util_cdc
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include ../scripts/library.mk
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@@ -0,0 +1,840 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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||||
<spirit:library>user</spirit:library>
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||||
<spirit:name>util_axis_fifo</spirit:name>
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||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
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||||
<spirit:name>s_axis</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>s_axis_valid</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_ready</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>TLAST</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tlast</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>TKEEP</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tkeep</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TKEEP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tkeep</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis_signal_clock</spirit:name>
|
||||
<spirit:displayName>m_axis_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
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||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">m_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">m_axis_aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis_signal_reset</spirit:name>
|
||||
<spirit:displayName>m_axis_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis_signal_clock</spirit:name>
|
||||
<spirit:displayName>s_axis_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">s_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">s_axis_aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis_signal_reset</spirit:name>
|
||||
<spirit:displayName>s_axis_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>util_axis_fifo</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>4837ce55</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>util_axis_fifo</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>4837ce55</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>fa323617</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_utilityxitfiles</spirit:name>
|
||||
<spirit:displayName>Utility XIT/TTCL</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xit.util</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_utilityxitfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">63</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tkeep</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.TKEEP_EN')) = 1)">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.TLAST_EN')) = 1)">false</xilinx:isEnabled>
|
||||
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|
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<spirit:displayName>Master AXIS Registered output</spirit:displayName>
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|
||||
<spirit:name>ALMOST_EMPTY_THRESHOLD</spirit:name>
|
||||
<spirit:displayName>Almost empty threshold</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ALMOST_EMPTY_THRESHOLD" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ALMOST_FULL_THRESHOLD</spirit:name>
|
||||
<spirit:displayName>Almost full threshold</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ALMOST_FULL_THRESHOLD" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TLAST_EN</spirit:name>
|
||||
<spirit:displayName>TLAST Enable</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.TLAST_EN">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TKEEP_EN</spirit:name>
|
||||
<spirit:displayName>TKEEP Enable</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.TKEEP_EN">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>REMOVE_NULL_BEAT_EN</spirit:name>
|
||||
<spirit:displayName>REMOVE_NULL_BEAT_EN Enable</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.REMOVE_NULL_BEAT_EN">false</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.REMOVE_NULL_BEAT_EN">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">util_axis_fifo_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
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||||
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
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||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
|
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<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
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<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>ADI AXI Stream FIFO</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_axis_fifo</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-14T03:45:42Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="59ef6667"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="de18f3ae"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="7abddce6"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="c7e77367"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,2 @@
|
||||
# This file is automatically written. Do not modify.
|
||||
proc gen_USERPARAMETER_REMOVE_NULL_BEAT_EN_ENABLEMENT {TKEEP_EN } {expr $TKEEP_EN == "true"}
|
||||
@@ -0,0 +1,358 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module util_axis_fifo #(
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter ADDRESS_WIDTH = 5,
|
||||
parameter ASYNC_CLK = 1,
|
||||
parameter M_AXIS_REGISTERED = 1,
|
||||
parameter [ADDRESS_WIDTH-1:0] ALMOST_EMPTY_THRESHOLD = 16,
|
||||
parameter [ADDRESS_WIDTH-1:0] ALMOST_FULL_THRESHOLD = 16,
|
||||
parameter TLAST_EN = 0,
|
||||
parameter TKEEP_EN = 0,
|
||||
parameter REMOVE_NULL_BEAT_EN = 0
|
||||
) (
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output m_axis_valid,
|
||||
output [DATA_WIDTH-1:0] m_axis_data,
|
||||
output [DATA_WIDTH/8-1:0] m_axis_tkeep,
|
||||
output m_axis_tlast,
|
||||
output [ADDRESS_WIDTH-1:0] m_axis_level,
|
||||
output m_axis_empty,
|
||||
output m_axis_almost_empty,
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output s_axis_ready,
|
||||
input s_axis_valid,
|
||||
input [DATA_WIDTH-1:0] s_axis_data,
|
||||
input [DATA_WIDTH/8-1:0] s_axis_tkeep,
|
||||
input s_axis_tlast,
|
||||
output [ADDRESS_WIDTH-1:0] s_axis_room,
|
||||
output s_axis_full,
|
||||
output s_axis_almost_full
|
||||
);
|
||||
|
||||
localparam MEM_WORD = (TKEEP_EN & TLAST_EN) ? (DATA_WIDTH+DATA_WIDTH/8+1) :
|
||||
(TKEEP_EN) ? (DATA_WIDTH+DATA_WIDTH/8) :
|
||||
(TLAST_EN) ? (DATA_WIDTH+1) :
|
||||
(DATA_WIDTH);
|
||||
|
||||
wire [MEM_WORD-1:0] s_axis_data_int_s;
|
||||
wire [MEM_WORD-1:0] m_axis_data_int_s;
|
||||
|
||||
generate if (ADDRESS_WIDTH == 0) begin : zerodeep /* it's not a real FIFO, just a 1 stage pipeline */
|
||||
|
||||
if (ASYNC_CLK) begin
|
||||
|
||||
(* KEEP = "yes" *) reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
|
||||
reg s_axis_waddr = 1'b0;
|
||||
reg m_axis_raddr = 1'b0;
|
||||
|
||||
wire m_axis_waddr;
|
||||
wire s_axis_raddr;
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_CLK)
|
||||
) i_waddr_sync (
|
||||
.out_clk(m_axis_aclk),
|
||||
.out_resetn(m_axis_aresetn),
|
||||
.in_bits(s_axis_waddr),
|
||||
.out_bits(m_axis_waddr));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_CLK)
|
||||
) i_raddr_sync (
|
||||
.out_clk(s_axis_aclk),
|
||||
.out_resetn(s_axis_aresetn),
|
||||
.in_bits(m_axis_raddr),
|
||||
.out_bits(s_axis_raddr));
|
||||
|
||||
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
|
||||
assign m_axis_level = ~m_axis_ready;
|
||||
assign m_axis_empty = 0;
|
||||
assign m_axis_almost_empty = 0;
|
||||
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
|
||||
assign s_axis_full = 0;
|
||||
assign s_axis_almost_full = 0;
|
||||
assign s_axis_room = s_axis_ready;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
|
||||
cdc_sync_fifo_ram <= s_axis_data;
|
||||
end
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
s_axis_waddr <= 1'b0;
|
||||
end else if (s_axis_ready & s_axis_valid) begin
|
||||
s_axis_waddr <= s_axis_waddr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
m_axis_raddr <= 1'b0;
|
||||
end else begin
|
||||
if (m_axis_valid & m_axis_ready)
|
||||
m_axis_raddr <= m_axis_raddr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign m_axis_data = cdc_sync_fifo_ram;
|
||||
|
||||
// TLAST support
|
||||
if (TLAST_EN) begin
|
||||
|
||||
reg axis_tlast_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
|
||||
axis_tlast_d <= s_axis_tlast;
|
||||
end
|
||||
assign m_axis_tlast = axis_tlast_d;
|
||||
|
||||
end
|
||||
|
||||
// TKEEP support
|
||||
if (TKEEP_EN) begin
|
||||
|
||||
reg axis_tkeep_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
|
||||
axis_tkeep_d <= s_axis_tkeep;
|
||||
end
|
||||
assign m_axis_tkeep = axis_tkeep_d;
|
||||
|
||||
end
|
||||
|
||||
end /* zerodeep */
|
||||
else
|
||||
begin /* !ASYNC_CLK */
|
||||
|
||||
// Note: In this mode, the write and read interface must have a symmetric
|
||||
// aspect ratio
|
||||
reg [DATA_WIDTH-1:0] axis_data_d;
|
||||
reg axis_valid_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (!s_axis_aresetn) begin
|
||||
axis_data_d <= {DATA_WIDTH{1'b0}};
|
||||
axis_valid_d <= 1'b0;
|
||||
end else if (s_axis_ready) begin
|
||||
axis_data_d <= s_axis_data;
|
||||
axis_valid_d <= s_axis_valid;
|
||||
end
|
||||
end
|
||||
|
||||
assign m_axis_data = axis_data_d;
|
||||
assign m_axis_valid = axis_valid_d;
|
||||
assign s_axis_ready = m_axis_ready | ~m_axis_valid;
|
||||
assign m_axis_empty = 1'b0;
|
||||
assign m_axis_almost_empty = 1'b0;
|
||||
assign m_axis_level = 1'b0;
|
||||
assign s_axis_full = 1'b0;
|
||||
assign s_axis_almost_full = 1'b0;
|
||||
assign s_axis_room = 1'b0;
|
||||
|
||||
// TLAST support
|
||||
if (TLAST_EN) begin
|
||||
reg axis_tlast_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (!s_axis_aresetn) begin
|
||||
axis_tlast_d <= 1'b0;
|
||||
end else if (s_axis_ready) begin
|
||||
axis_tlast_d <= s_axis_tlast;
|
||||
end
|
||||
end
|
||||
assign m_axis_tlast = axis_tlast_d;
|
||||
end
|
||||
|
||||
// TKEEP support
|
||||
if (TKEEP_EN) begin
|
||||
reg axis_tkeep_d;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (!s_axis_aresetn) begin
|
||||
axis_tkeep_d <= 1'b0;
|
||||
end else if (s_axis_ready) begin
|
||||
axis_tkeep_d <= s_axis_tkeep;
|
||||
end
|
||||
end
|
||||
assign m_axis_tkeep = axis_tkeep_d;
|
||||
|
||||
end
|
||||
|
||||
end /* !ASYNC_CLK */
|
||||
|
||||
end else begin : fifo /* ADDRESS_WIDTH != 0 - this is a real FIFO implementation */
|
||||
|
||||
wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
|
||||
wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
|
||||
wire _m_axis_ready;
|
||||
wire _m_axis_valid;
|
||||
|
||||
wire s_mem_write;
|
||||
wire m_mem_read;
|
||||
|
||||
reg valid = 1'b0;
|
||||
|
||||
/* Control for first falls through */
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
valid <= 1'b0;
|
||||
end else begin
|
||||
if (_m_axis_valid)
|
||||
valid <= 1'b1;
|
||||
else if (m_axis_ready)
|
||||
valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (REMOVE_NULL_BEAT_EN) begin
|
||||
// remove NULL bytes from the stream - NOTE: TKEEP is all-LOW or all-HIGH
|
||||
assign s_mem_write = s_axis_ready & s_axis_valid & (&s_axis_tkeep);
|
||||
end else begin
|
||||
assign s_mem_write = s_axis_ready & s_axis_valid;
|
||||
end
|
||||
assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid;
|
||||
|
||||
util_axis_fifo_address_generator #(
|
||||
.ASYNC_CLK(ASYNC_CLK),
|
||||
.ADDRESS_WIDTH(ADDRESS_WIDTH),
|
||||
.ALMOST_EMPTY_THRESHOLD (ALMOST_EMPTY_THRESHOLD),
|
||||
.ALMOST_FULL_THRESHOLD (ALMOST_FULL_THRESHOLD)
|
||||
) i_address_gray (
|
||||
.m_axis_aclk(m_axis_aclk),
|
||||
.m_axis_aresetn(m_axis_aresetn),
|
||||
.m_axis_ready(_m_axis_ready),
|
||||
.m_axis_valid(_m_axis_valid),
|
||||
.m_axis_raddr(m_axis_raddr),
|
||||
.m_axis_level(m_axis_level),
|
||||
.m_axis_empty(m_axis_empty),
|
||||
.m_axis_almost_empty(m_axis_almost_empty),
|
||||
.s_axis_aclk(s_axis_aclk),
|
||||
.s_axis_aresetn(s_axis_aresetn),
|
||||
.s_axis_ready(s_axis_ready),
|
||||
.s_axis_valid(s_axis_valid),
|
||||
.s_axis_full(s_axis_full),
|
||||
.s_axis_almost_full(s_axis_almost_full),
|
||||
.s_axis_waddr(s_axis_waddr),
|
||||
.s_axis_room(s_axis_room));
|
||||
|
||||
// TLAST and TKEEP support
|
||||
if (TLAST_EN & TKEEP_EN) begin
|
||||
assign s_axis_data_int_s = {s_axis_tkeep, s_axis_tlast, s_axis_data};
|
||||
assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
|
||||
assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
|
||||
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
|
||||
end else if (TKEEP_EN) begin
|
||||
assign s_axis_data_int_s = {s_axis_tkeep, s_axis_data};
|
||||
assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
|
||||
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
|
||||
end else if (TLAST_EN) begin
|
||||
assign s_axis_data_int_s = {s_axis_tlast, s_axis_data};
|
||||
assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
|
||||
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
|
||||
end else begin
|
||||
assign s_axis_data_int_s = {s_axis_data};
|
||||
assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
|
||||
end
|
||||
|
||||
if (ASYNC_CLK == 1) begin : async_clocks /* Asynchronous WRITE/READ clocks */
|
||||
|
||||
// The assumption is that in this mode the M_AXIS_REGISTERED is 1
|
||||
// When the clocks are asynchronous instantiate a block RAM
|
||||
// regardless of the requested size to make sure we threat the
|
||||
// clock crossing correctly
|
||||
ad_mem #(
|
||||
.DATA_WIDTH (MEM_WORD),
|
||||
.ADDRESS_WIDTH (ADDRESS_WIDTH)
|
||||
) i_mem (
|
||||
.clka(s_axis_aclk),
|
||||
.wea(s_mem_write),
|
||||
.addra(s_axis_waddr),
|
||||
.dina(s_axis_data_int_s),
|
||||
.clkb(m_axis_aclk),
|
||||
.reb(m_mem_read),
|
||||
.addrb(m_axis_raddr),
|
||||
.doutb(m_axis_data_int_s));
|
||||
|
||||
assign _m_axis_ready = ~valid || m_axis_ready;
|
||||
assign m_axis_valid = valid;
|
||||
|
||||
end else begin : sync_clocks /* Synchronous WRITE/READ clocks */
|
||||
|
||||
reg [MEM_WORD-1:0] ram[0:2**ADDRESS_WIDTH-1];
|
||||
|
||||
// When the clocks are synchronous use behavioral modeling for the SDP RAM
|
||||
// Let the synthesizer decide what to infer (distributed or block RAM)
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_mem_write)
|
||||
ram[s_axis_waddr] <= s_axis_data_int_s;
|
||||
end
|
||||
|
||||
if (M_AXIS_REGISTERED == 1) begin
|
||||
|
||||
reg [MEM_WORD-1:0] data;
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_mem_read)
|
||||
data <= ram[m_axis_raddr];
|
||||
end
|
||||
|
||||
assign _m_axis_ready = ~valid || m_axis_ready;
|
||||
assign m_axis_data_int_s = data;
|
||||
assign m_axis_valid = valid;
|
||||
|
||||
end else begin
|
||||
|
||||
assign _m_axis_ready = m_axis_ready;
|
||||
assign m_axis_valid = _m_axis_valid;
|
||||
assign m_axis_data_int_s = ram[m_axis_raddr];
|
||||
|
||||
end
|
||||
end
|
||||
end /* fifo */
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,421 @@
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<!-- -->
|
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|
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<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
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<DefaultLaunch Dir="$PRUNDIR"/>
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|
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|
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<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
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<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
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<Option Name="SimTypes" Val="bfm"/>
|
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<Option Name="SimTypes" Val="tlm"/>
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<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
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||||
<Filter Type="Srcs"/>
|
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<File Path="$PPRDIR/../common/ad_mem.v">
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<FileInfo>
|
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|
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|
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<File Path="$PPRDIR/util_axis_fifo_address_generator.v">
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||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
|
||||
</File>
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<File Path="$PPRDIR/util_axis_fifo.v">
|
||||
<FileInfo>
|
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_mem_asym.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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|
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<FileInfo SFType="IPXACT"/>
|
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</File>
|
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<Config>
|
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<Option Name="DesignMode" Val="RTL"/>
|
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<Option Name="TopModule" Val="util_axis_fifo"/>
|
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</Config>
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|
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<Filter Type="Utils"/>
|
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<Config>
|
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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<Option Name="Description" Val="Vivado Simulator"/>
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<Option Name="CompiledLib" Val="0"/>
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<Option Name="Description" Val="ModelSim Simulator"/>
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<Simulator Name="Questa">
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<Option Name="Description" Val="Xcelium Parallel Simulator"/>
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<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,172 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module util_axis_fifo_address_generator #(
|
||||
parameter ASYNC_CLK = 0, // single or double clocked FIFO
|
||||
parameter ADDRESS_WIDTH = 4, // address width, effective FIFO depth
|
||||
parameter [ADDRESS_WIDTH-1:0] ALMOST_EMPTY_THRESHOLD = 16,
|
||||
parameter [ADDRESS_WIDTH-1:0] ALMOST_FULL_THRESHOLD = 16
|
||||
) (
|
||||
|
||||
// Read interface - Sink side
|
||||
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output m_axis_valid,
|
||||
output m_axis_empty,
|
||||
output m_axis_almost_empty,
|
||||
output [ADDRESS_WIDTH-1:0] m_axis_raddr,
|
||||
output [ADDRESS_WIDTH-1:0] m_axis_level,
|
||||
|
||||
// Write interface - Source side
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output s_axis_ready,
|
||||
input s_axis_valid,
|
||||
output s_axis_full,
|
||||
output s_axis_almost_full,
|
||||
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
|
||||
output [ADDRESS_WIDTH-1:0] s_axis_room
|
||||
);
|
||||
|
||||
localparam FIFO_DEPTH = {ADDRESS_WIDTH{1'b1}};
|
||||
|
||||
// Definition of address counters
|
||||
// All the counters are wider with one bit to indicate wraparounds
|
||||
reg [ADDRESS_WIDTH:0] s_axis_waddr_reg = 'h0;
|
||||
reg [ADDRESS_WIDTH:0] m_axis_raddr_reg = 'h0;
|
||||
|
||||
wire [ADDRESS_WIDTH:0] s_axis_raddr_reg;
|
||||
wire [ADDRESS_WIDTH:0] m_axis_waddr_reg;
|
||||
|
||||
wire s_axis_write_s;
|
||||
wire s_axis_ready_s;
|
||||
|
||||
wire m_axis_read_s;
|
||||
wire m_axis_valid_s;
|
||||
wire [ADDRESS_WIDTH-1:0] m_axis_level_s;
|
||||
|
||||
// Write address counter
|
||||
|
||||
assign s_axis_write_s = s_axis_ready && s_axis_valid && ~s_axis_full;
|
||||
always @(posedge s_axis_aclk)
|
||||
begin
|
||||
if (!s_axis_aresetn)
|
||||
s_axis_waddr_reg <= 'h0;
|
||||
else
|
||||
if (s_axis_write_s)
|
||||
s_axis_waddr_reg <= s_axis_waddr_reg + 1'b1;
|
||||
end
|
||||
|
||||
// Read address counter
|
||||
|
||||
assign m_axis_read_s = m_axis_ready && m_axis_valid && ~m_axis_empty;
|
||||
always @(posedge m_axis_aclk)
|
||||
begin
|
||||
if (!m_axis_aresetn)
|
||||
m_axis_raddr_reg <= 'h0;
|
||||
else
|
||||
if (m_axis_read_s)
|
||||
m_axis_raddr_reg <= m_axis_raddr_reg + 1'b1;
|
||||
end
|
||||
|
||||
// Output assignments
|
||||
|
||||
assign s_axis_waddr = s_axis_waddr_reg[ADDRESS_WIDTH-1:0];
|
||||
assign m_axis_raddr = m_axis_raddr_reg[ADDRESS_WIDTH-1:0];
|
||||
|
||||
// CDC circuits for double clock configuration
|
||||
|
||||
generate if (ASYNC_CLK == 1) begin : g_async_clock
|
||||
// CDC transfer of the write pointer to the read clock domain
|
||||
sync_gray #(
|
||||
.DATA_WIDTH(ADDRESS_WIDTH + 1)
|
||||
) i_waddr_sync_gray (
|
||||
.in_clk(s_axis_aclk),
|
||||
.in_resetn(s_axis_aresetn),
|
||||
.out_clk(m_axis_aclk),
|
||||
.out_resetn(m_axis_aresetn),
|
||||
.in_count(s_axis_waddr_reg),
|
||||
.out_count(m_axis_waddr_reg));
|
||||
|
||||
// CDC transfer of the read pointer to the write clock domain
|
||||
sync_gray #(
|
||||
.DATA_WIDTH(ADDRESS_WIDTH + 1)
|
||||
) i_raddr_sync_gray (
|
||||
.in_clk(m_axis_aclk),
|
||||
.in_resetn(m_axis_aresetn),
|
||||
.out_clk(s_axis_aclk),
|
||||
.out_resetn(s_axis_aresetn),
|
||||
.in_count(m_axis_raddr_reg),
|
||||
.out_count(s_axis_raddr_reg));
|
||||
end else begin
|
||||
assign m_axis_waddr_reg = s_axis_waddr_reg;
|
||||
assign s_axis_raddr_reg = m_axis_raddr_reg;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// FIFO write logic - upstream
|
||||
//
|
||||
// s_axis_full - FIFO is full if next write pointer equal to read pointer
|
||||
// s_axis_ready - FIFO is always ready, unless it's full
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
wire [ADDRESS_WIDTH:0] s_axis_fifo_fill = s_axis_waddr_reg - s_axis_raddr_reg;
|
||||
assign s_axis_full = (s_axis_fifo_fill == {ADDRESS_WIDTH{1'b1}});
|
||||
assign s_axis_almost_full = s_axis_fifo_fill > {1'b0, ~ALMOST_FULL_THRESHOLD};
|
||||
assign s_axis_ready = ~s_axis_full;
|
||||
assign s_axis_room = ~s_axis_fifo_fill;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// FIFO read logic - downstream
|
||||
//
|
||||
// m_axis_empty - FIFO is empty if read pointer equal to write pointer
|
||||
// m_axis_valid - FIFO has a valid output data, if it's not empty
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
wire [ADDRESS_WIDTH:0] m_axis_fifo_fill = m_axis_waddr_reg - m_axis_raddr_reg;
|
||||
assign m_axis_empty = m_axis_fifo_fill == 0;
|
||||
assign m_axis_almost_empty = (m_axis_fifo_fill < ALMOST_EMPTY_THRESHOLD);
|
||||
assign m_axis_valid = ~m_axis_empty;
|
||||
assign m_axis_level = m_axis_fifo_fill;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,198 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create util_axis_fifo
|
||||
adi_ip_files util_axis_fifo [list \
|
||||
"util_axis_fifo_address_generator.v" \
|
||||
"../common/ad_mem.v" \
|
||||
"../common/ad_mem_asym.v" \
|
||||
"util_axis_fifo.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite util_axis_fifo
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
]
|
||||
|
||||
set_property display_name "ADI AXI Stream FIFO" [ipx::current_core]
|
||||
set_property description "ADI AXI Stream FIFO" [ipx::current_core]
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_axis_fifo} [ipx::current_core]
|
||||
|
||||
## Interface definitions
|
||||
|
||||
adi_add_bus "s_axis" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{
|
||||
{"s_axis_valid" "TVALID"} \
|
||||
{"s_axis_ready" "TREADY"} \
|
||||
{"s_axis_data" "TDATA"} \
|
||||
{"s_axis_tlast" "TLAST"} \
|
||||
{"s_axis_tkeep" "TKEEP"} \
|
||||
}
|
||||
|
||||
adi_set_ports_dependency "s_axis_tlast" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.TLAST_EN')) = 1)"
|
||||
adi_set_ports_dependency "s_axis_tkeep" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.TKEEP_EN')) = 1)"
|
||||
|
||||
adi_add_bus "m_axis" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{
|
||||
{"m_axis_valid" "TVALID"} \
|
||||
{"m_axis_ready" "TREADY"} \
|
||||
{"m_axis_data" "TDATA"} \
|
||||
{"m_axis_tlast" "TLAST"} \
|
||||
{"m_axis_tkeep" "TKEEP"} \
|
||||
}
|
||||
|
||||
adi_set_ports_dependency "m_axis_tlast" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.TLAST_EN')) = 1)"
|
||||
adi_set_ports_dependency "m_axis_tkeep" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.TKEEP_EN')) = 1)"
|
||||
|
||||
adi_add_bus_clock "m_axis_aclk" "m_axis" "m_axis_aresetn"
|
||||
adi_add_bus_clock "s_axis_aclk" "s_axis" "s_axis_aresetn"
|
||||
|
||||
## Parameter validation
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "list" \
|
||||
"value_validation_list" "8 16 32 64 128 256 512 1024 2048 4096" \
|
||||
] \
|
||||
[ipx::get_user_parameters DATA_WIDTH -of_objects [ipx::current_core]]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "4096" \
|
||||
] \
|
||||
[ipx::get_user_parameters ADDRESS_WIDTH -of_objects [ipx::current_core]]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
] \
|
||||
[ipx::get_user_parameters ALMOST_FULL_THRESHOLD -of_objects [ipx::current_core]]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
] \
|
||||
[ipx::get_user_parameters ALMOST_EMPTY_THRESHOLD -of_objects [ipx::current_core]]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "pairs" \
|
||||
"value_validation_pairs" { \
|
||||
"Synchronous" "0" \
|
||||
"Asynchronous" "1" \
|
||||
} \
|
||||
] \
|
||||
[ipx::get_user_parameters ASYNC_CLK -of_objects [ipx::current_core]]
|
||||
|
||||
foreach {k v} { \
|
||||
"M_AXIS_REGISTERED" "true" \
|
||||
"TLAST_EN" "false" \
|
||||
"TKEEP_EN" "true" \
|
||||
"REMOVE_NULL_BEAT_EN" "false" \
|
||||
} { \
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" $v \
|
||||
] \
|
||||
[ipx::get_user_parameters $k -of_objects [ipx::current_core]]
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" $v \
|
||||
] \
|
||||
[ipx::get_hdl_parameters $k -of_objects [ipx::current_core]]
|
||||
}
|
||||
|
||||
## Customize IP layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component [ipx::current_core] [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
## Create a new GUI page
|
||||
ipgui::add_page -name {AXI Stream FIFO} -component [ipx::current_core] -display_name {AXI Stream FIFO}
|
||||
set page0 [ipgui::get_pagespec -name "AXI Stream FIFO" -component [ipx::current_core]]
|
||||
|
||||
set clock_group [ipgui::add_group -name "Clock Configuration" -component [ipx::current_core] \
|
||||
-parent $page0 -display_name "Clock Configuration" ]
|
||||
|
||||
ipgui::add_param -name "ASYNC_CLK" -component [ipx::current_core] -parent $clock_group
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "Clocking mode" \
|
||||
"tooltip" "\[ASYNC_CLK\] If enabled the readn and write interface of the FIFO is asynchronous (its clocks are from different clock domain)."
|
||||
] [ipgui::get_guiparamspec -name "ASYNC_CLK" -component [ipx::current_core]]
|
||||
|
||||
set interface_group [ipgui::add_group -name "Interface Configuration" -component [ipx::current_core] \
|
||||
-parent $page0 -display_name "Interface Configuration" ]
|
||||
|
||||
ipgui::add_param -name "DATA_WIDTH" -component [ipx::current_core] -parent $interface_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Data width" \
|
||||
"tooltip" "\[DATA_WIDTH\] Data width of the AXI stream interfaces." \
|
||||
] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_param -name "ADDRESS_WIDTH" -component [ipx::current_core] -parent $interface_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Address width" \
|
||||
"tooltip" "\[ADDRESS_WIDTH\] Address width of the read and write address pointers. It defines the depth of the FIFO : DATA_WIDTH/8 * (2 ^ ADDRESS_WIDTH)" \
|
||||
] [ipgui::get_guiparamspec -name "ADDRESS_WIDTH" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_param -name "ALMOST_FULL_THRESHOLD" -component [ipx::current_core] -parent $interface_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Almost full threshold" \
|
||||
"tooltip" "\[ALMOST_FULL_THRESHOLD\] The offset between the almost full assertion and full assertion in number of FIFO words." \
|
||||
] [ipgui::get_guiparamspec -name "ALMOST_FULL_THRESHOLD" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_param -name "ALMOST_EMPTY_THRESHOLD" -component [ipx::current_core] -parent $interface_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Almost empty threshold" \
|
||||
"tooltip" "\[ALMOST_EMPTY_THRESHOLD\] The offset between the almost empty assertion and empty assertion in number of FIFO words." \
|
||||
] [ipgui::get_guiparamspec -name "ALMOST_EMPTY_THRESHOLD" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_param -name "TLAST_EN" -component [ipx::current_core] -parent $interface_group
|
||||
set_property -dict [list \
|
||||
"display_name" "TLAST Enable" \
|
||||
"tooltip" "\[TLAST_EN\] Enable the TLAST for the AXI stream interface, signaling packet boundaries." \
|
||||
] [ipgui::get_guiparamspec -name "TLAST_EN" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_param -name "TKEEP_EN" -component [ipx::current_core] -parent $interface_group
|
||||
set_property -dict [list \
|
||||
"display_name" "TKEEP Enable" \
|
||||
"tooltip" "\[TKEEP_EN\] Enable the TKEEP for the AXI stream interface, for data byte qualification for each AXIS beat." \
|
||||
] [ipgui::get_guiparamspec -name "TKEEP_EN" -component [ipx::current_core]]
|
||||
|
||||
set other_group [ipgui::add_group -name "Other Features" -component [ipx::current_core] \
|
||||
-parent $page0 -display_name "Other Features" ]
|
||||
|
||||
ipgui::add_param -name "M_AXIS_REGISTERED" -component [ipx::current_core] -parent $other_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Master AXIS Registered output" \
|
||||
"tooltip" "\[M_AXIS_REGISTERED\] Add an additional register stage to the master AXI stream data output." \
|
||||
] [ipgui::get_guiparamspec -name "M_AXIS_REGISTERED" -component [ipx::current_core]]
|
||||
|
||||
ipgui::add_param -name "REMOVE_NULL_BEAT_EN" -component [ipx::current_core] -parent $other_group
|
||||
set_property -dict [list \
|
||||
"display_name" "REMOVE_NULL_BEAT_EN Enable" \
|
||||
"tooltip" "\[REMOVE_NULL_BEAT_EN\] Filteres out all the beats with a null TKEEP qualifier." \
|
||||
] [ipgui::get_guiparamspec -name "REMOVE_NULL_BEAT_EN" -component [ipx::current_core]]
|
||||
set_property enablement_tcl_expr {$TKEEP_EN == "true"} [ipx::get_user_parameters REMOVE_NULL_BEAT_EN -of_objects [ipx::current_core]]
|
||||
|
||||
## Create and save the XGUI file
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,176 @@
|
||||
|
||||
# Loading additional proc with user specified bodies to compute parameter values.
|
||||
source [file join [file dirname [file dirname [info script]]] gui/util_axis_fifo_v1_0.gtcl]
|
||||
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set AXI_Stream_FIFO [ipgui::add_page $IPINST -name "AXI Stream FIFO"]
|
||||
#Adding Group
|
||||
set Clock_Configuration [ipgui::add_group $IPINST -name "Clock Configuration" -parent ${AXI_Stream_FIFO}]
|
||||
set ASYNC_CLK [ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Clock_Configuration} -widget comboBox]
|
||||
set_property tooltip {[ASYNC_CLK] If enabled the readn and write interface of the FIFO is asynchronous (its clocks are from different clock domain).} ${ASYNC_CLK}
|
||||
|
||||
#Adding Group
|
||||
set Interface_Configuration [ipgui::add_group $IPINST -name "Interface Configuration" -parent ${AXI_Stream_FIFO}]
|
||||
set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Interface_Configuration} -widget comboBox]
|
||||
set_property tooltip {[DATA_WIDTH] Data width of the AXI stream interfaces.} ${DATA_WIDTH}
|
||||
set ADDRESS_WIDTH [ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[ADDRESS_WIDTH] Address width of the read and write address pointers. It defines the depth of the FIFO : DATA_WIDTH/8 * (2 ^ ADDRESS_WIDTH)} ${ADDRESS_WIDTH}
|
||||
set ALMOST_FULL_THRESHOLD [ipgui::add_param $IPINST -name "ALMOST_FULL_THRESHOLD" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[ALMOST_FULL_THRESHOLD] The offset between the almost full assertion and full assertion in number of FIFO words.} ${ALMOST_FULL_THRESHOLD}
|
||||
set ALMOST_EMPTY_THRESHOLD [ipgui::add_param $IPINST -name "ALMOST_EMPTY_THRESHOLD" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[ALMOST_EMPTY_THRESHOLD] The offset between the almost empty assertion and empty assertion in number of FIFO words.} ${ALMOST_EMPTY_THRESHOLD}
|
||||
set TLAST_EN [ipgui::add_param $IPINST -name "TLAST_EN" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[TLAST_EN] Enable the TLAST for the AXI stream interface, signaling packet boundaries.} ${TLAST_EN}
|
||||
set TKEEP_EN [ipgui::add_param $IPINST -name "TKEEP_EN" -parent ${Interface_Configuration}]
|
||||
set_property tooltip {[TKEEP_EN] Enable the TKEEP for the AXI stream interface, for data byte qualification for each AXIS beat.} ${TKEEP_EN}
|
||||
|
||||
#Adding Group
|
||||
set Other_Features [ipgui::add_group $IPINST -name "Other Features" -parent ${AXI_Stream_FIFO}]
|
||||
set M_AXIS_REGISTERED [ipgui::add_param $IPINST -name "M_AXIS_REGISTERED" -parent ${Other_Features}]
|
||||
set_property tooltip {[M_AXIS_REGISTERED] Add an additional register stage to the master AXI stream data output.} ${M_AXIS_REGISTERED}
|
||||
set REMOVE_NULL_BEAT_EN [ipgui::add_param $IPINST -name "REMOVE_NULL_BEAT_EN" -parent ${Other_Features}]
|
||||
set_property tooltip {[REMOVE_NULL_BEAT_EN] Filteres out all the beats with a null TKEEP qualifier.} ${REMOVE_NULL_BEAT_EN}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.REMOVE_NULL_BEAT_EN { PARAM_VALUE.REMOVE_NULL_BEAT_EN PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to update REMOVE_NULL_BEAT_EN when any of the dependent parameters in the arguments change
|
||||
|
||||
set REMOVE_NULL_BEAT_EN ${PARAM_VALUE.REMOVE_NULL_BEAT_EN}
|
||||
set TKEEP_EN ${PARAM_VALUE.TKEEP_EN}
|
||||
set values(TKEEP_EN) [get_property value $TKEEP_EN]
|
||||
if { [gen_USERPARAMETER_REMOVE_NULL_BEAT_EN_ENABLEMENT $values(TKEEP_EN)] } {
|
||||
set_property enabled true $REMOVE_NULL_BEAT_EN
|
||||
} else {
|
||||
set_property enabled false $REMOVE_NULL_BEAT_EN
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.REMOVE_NULL_BEAT_EN { PARAM_VALUE.REMOVE_NULL_BEAT_EN } {
|
||||
# Procedure called to validate REMOVE_NULL_BEAT_EN
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to validate ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } {
|
||||
# Procedure called to update ALMOST_EMPTY_THRESHOLD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } {
|
||||
# Procedure called to validate ALMOST_EMPTY_THRESHOLD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } {
|
||||
# Procedure called to update ALMOST_FULL_THRESHOLD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } {
|
||||
# Procedure called to validate ALMOST_FULL_THRESHOLD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to validate ASYNC_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } {
|
||||
# Procedure called to update M_AXIS_REGISTERED when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } {
|
||||
# Procedure called to validate M_AXIS_REGISTERED
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to update TKEEP_EN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to validate TKEEP_EN
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } {
|
||||
# Procedure called to update TLAST_EN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } {
|
||||
# Procedure called to validate TLAST_EN
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.M_AXIS_REGISTERED { MODELPARAM_VALUE.M_AXIS_REGISTERED PARAM_VALUE.M_AXIS_REGISTERED } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.M_AXIS_REGISTERED}] ${MODELPARAM_VALUE.M_AXIS_REGISTERED}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD { MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ALMOST_EMPTY_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD { MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD PARAM_VALUE.ALMOST_FULL_THRESHOLD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ALMOST_FULL_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.TLAST_EN { MODELPARAM_VALUE.TLAST_EN PARAM_VALUE.TLAST_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.TLAST_EN}] ${MODELPARAM_VALUE.TLAST_EN}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.TKEEP_EN { MODELPARAM_VALUE.TKEEP_EN PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.TKEEP_EN}] ${MODELPARAM_VALUE.TKEEP_EN}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.REMOVE_NULL_BEAT_EN { MODELPARAM_VALUE.REMOVE_NULL_BEAT_EN PARAM_VALUE.REMOVE_NULL_BEAT_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.REMOVE_NULL_BEAT_EN}] ${MODELPARAM_VALUE.REMOVE_NULL_BEAT_EN}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user