initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := util_axis_fifo_asym
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GENERIC_DEPS += util_axis_fifo_asym.v
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XILINX_DEPS += util_axis_fifo_asym_ip.tcl
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XILINX_LIB_DEPS += util_axis_fifo
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XILINX_LIB_DEPS += util_cdc
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include ../scripts/library.mk
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@@ -0,0 +1,775 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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||||
<spirit:library>user</spirit:library>
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||||
<spirit:name>util_axis_fifo_asym</spirit:name>
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||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
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||||
<spirit:busInterface>
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||||
<spirit:name>s_axis</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>TVALID</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>s_axis_valid</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>TREADY</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>s_axis_ready</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
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||||
<spirit:name>TDATA</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>s_axis_data</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>s_axis_tlast</spirit:name>
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</spirit:physicalPort>
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||||
</spirit:portMap>
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</spirit:portMaps>
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||||
</spirit:busInterface>
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||||
<spirit:busInterface>
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||||
<spirit:name>m_axis</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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<spirit:master/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_valid</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_ready</spirit:name>
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||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_data</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
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||||
<spirit:name>m_axis_tlast</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
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||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis_signal_clock</spirit:name>
|
||||
<spirit:displayName>m_axis_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">m_axis</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">m_axis_aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis_signal_reset</spirit:name>
|
||||
<spirit:displayName>m_axis_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
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||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis_signal_clock</spirit:name>
|
||||
<spirit:displayName>s_axis_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">s_axis</spirit:value>
|
||||
</spirit:parameter>
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||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">s_axis_aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis_signal_reset</spirit:name>
|
||||
<spirit:displayName>s_axis_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
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||||
</spirit:busInterfaces>
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||||
<spirit:model>
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||||
<spirit:views>
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||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>util_axis_fifo_asym</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>94187aef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>util_axis_fifo_asym</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>94187aef</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>02216b5c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.M_DATA_WIDTH')) - 1)">127</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tkeep</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.M_DATA_WIDTH')) / 8) - 1)">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_empty</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>m_axis_almost_empty</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
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<spirit:name>M_AXIS_REGISTERED</spirit:name>
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<spirit:displayName>M Axis Registered</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M_AXIS_REGISTERED">1</spirit:value>
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<spirit:name>ALMOST_EMPTY_THRESHOLD</spirit:name>
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<spirit:displayName>Almost Empty Threshold</spirit:displayName>
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<spirit:name>ALMOST_FULL_THRESHOLD</spirit:name>
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<spirit:displayName>Almost Full Threshold</spirit:displayName>
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<spirit:name>TLAST_EN</spirit:name>
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<spirit:displayName>Tlast En</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TLAST_EN">0</spirit:value>
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<spirit:name>TKEEP_EN</spirit:name>
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<spirit:displayName>Tkeep En</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TKEEP_EN">0</spirit:value>
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<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
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<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>util_axis_fifo_asym_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
||||
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_axis_fifo_asym</xilinx:vendorURL>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-01-14T03:50:07Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e69cf0b7"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="5e0743cc"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="4ac641e5"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="91f73006"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,307 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module util_axis_fifo_asym #(
|
||||
parameter ASYNC_CLK = 1,
|
||||
parameter S_DATA_WIDTH = 64,
|
||||
parameter S_ADDRESS_WIDTH = 5,
|
||||
parameter M_DATA_WIDTH = 128,
|
||||
parameter M_AXIS_REGISTERED = 1,
|
||||
parameter ALMOST_EMPTY_THRESHOLD = 4,
|
||||
parameter ALMOST_FULL_THRESHOLD = 4,
|
||||
parameter TLAST_EN = 0,
|
||||
parameter TKEEP_EN = 0
|
||||
) (
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output m_axis_valid,
|
||||
output [M_DATA_WIDTH-1:0] m_axis_data,
|
||||
output [M_DATA_WIDTH/8-1:0] m_axis_tkeep,
|
||||
output m_axis_tlast,
|
||||
output m_axis_empty,
|
||||
output m_axis_almost_empty,
|
||||
output [31:0] m_axis_level,
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output s_axis_ready,
|
||||
input s_axis_valid,
|
||||
input [S_DATA_WIDTH-1:0] s_axis_data,
|
||||
input [S_DATA_WIDTH/8-1:0] s_axis_tkeep,
|
||||
input s_axis_tlast,
|
||||
output s_axis_full,
|
||||
output s_axis_almost_full,
|
||||
output [S_ADDRESS_WIDTH-1:0] s_axis_room
|
||||
);
|
||||
|
||||
// define which interface has a wider bus
|
||||
localparam RATIO_TYPE = (S_DATA_WIDTH >= M_DATA_WIDTH) ? 1 : 0;
|
||||
|
||||
// bus width ratio
|
||||
localparam RATIO = (RATIO_TYPE) ? S_DATA_WIDTH/M_DATA_WIDTH : M_DATA_WIDTH/S_DATA_WIDTH;
|
||||
|
||||
// atomic parameters - NOTE: depth is always defined by the slave attributes
|
||||
localparam A_WIDTH = (RATIO_TYPE) ? M_DATA_WIDTH : S_DATA_WIDTH;
|
||||
localparam A_ADDRESS = (RATIO_TYPE) ? S_ADDRESS_WIDTH : (S_ADDRESS_WIDTH-$clog2(RATIO));
|
||||
localparam A_ALMOST_FULL_THRESHOLD = (RATIO_TYPE) ? ALMOST_FULL_THRESHOLD : (ALMOST_FULL_THRESHOLD/RATIO);
|
||||
localparam A_ALMOST_EMPTY_THRESHOLD = (RATIO_TYPE) ? (ALMOST_EMPTY_THRESHOLD/RATIO) : ALMOST_EMPTY_THRESHOLD;
|
||||
|
||||
// slave and master sequencers
|
||||
reg [$clog2(RATIO)-1:0] s_axis_counter;
|
||||
reg [$clog2(RATIO)-1:0] m_axis_counter;
|
||||
|
||||
wire [RATIO-1:0] m_axis_ready_int_s;
|
||||
wire [RATIO-1:0] m_axis_valid_int_s;
|
||||
wire [RATIO*A_WIDTH-1:0] m_axis_data_int_s;
|
||||
wire [RATIO*A_WIDTH/8-1:0] m_axis_tkeep_int_s;
|
||||
wire [RATIO-1:0] m_axis_tlast_int_s;
|
||||
wire [RATIO-1:0] m_axis_empty_int_s;
|
||||
wire [RATIO-1:0] m_axis_almost_empty_int_s;
|
||||
wire [RATIO*A_ADDRESS-1:0] m_axis_level_int_s;
|
||||
|
||||
wire [RATIO-1:0] s_axis_ready_int_s;
|
||||
wire [RATIO-1:0] s_axis_valid_int_s;
|
||||
wire [RATIO*A_WIDTH-1:0] s_axis_data_int_s;
|
||||
wire [RATIO*A_WIDTH/8-1:0] s_axis_tkeep_int_s;
|
||||
wire [RATIO-1:0] s_axis_tlast_int_s;
|
||||
wire [RATIO-1:0] s_axis_full_int_s;
|
||||
wire [RATIO-1:0] s_axis_almost_full_int_s;
|
||||
wire [RATIO*A_ADDRESS-1:0] s_axis_room_int_s;
|
||||
|
||||
// instantiate the FIFOs
|
||||
genvar i;
|
||||
generate
|
||||
for (i=0; i<RATIO; i=i+1) begin
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH (A_WIDTH),
|
||||
.ADDRESS_WIDTH (A_ADDRESS),
|
||||
.ASYNC_CLK (ASYNC_CLK),
|
||||
.M_AXIS_REGISTERED (M_AXIS_REGISTERED),
|
||||
.ALMOST_EMPTY_THRESHOLD (A_ALMOST_EMPTY_THRESHOLD),
|
||||
.ALMOST_FULL_THRESHOLD (A_ALMOST_FULL_THRESHOLD),
|
||||
.TKEEP_EN (TKEEP_EN),
|
||||
.TLAST_EN (TLAST_EN)
|
||||
) i_fifo (
|
||||
.m_axis_aclk (m_axis_aclk),
|
||||
.m_axis_aresetn (m_axis_aresetn),
|
||||
.m_axis_ready (m_axis_ready_int_s[i]),
|
||||
.m_axis_valid (m_axis_valid_int_s[i]),
|
||||
.m_axis_data (m_axis_data_int_s[A_WIDTH*i+:A_WIDTH]),
|
||||
.m_axis_tlast (m_axis_tlast_int_s[i]),
|
||||
.m_axis_tkeep (m_axis_tkeep_int_s[A_WIDTH/8*i+:A_WIDTH/8]),
|
||||
.m_axis_level (m_axis_level_int_s[A_ADDRESS*i+:A_ADDRESS]),
|
||||
.m_axis_empty (m_axis_empty_int_s[i]),
|
||||
.m_axis_almost_empty (m_axis_almost_empty_int_s[i]),
|
||||
.s_axis_aclk (s_axis_aclk),
|
||||
.s_axis_aresetn (s_axis_aresetn),
|
||||
.s_axis_ready (s_axis_ready_int_s[i]),
|
||||
.s_axis_valid (s_axis_valid_int_s[i]),
|
||||
.s_axis_data (s_axis_data_int_s[A_WIDTH*i+:A_WIDTH]),
|
||||
.s_axis_tkeep (s_axis_tkeep_int_s[A_WIDTH/8*i+:A_WIDTH/8]),
|
||||
.s_axis_tlast (s_axis_tlast_int_s[i]),
|
||||
.s_axis_room (s_axis_room_int_s[A_ADDRESS*i+:A_ADDRESS]),
|
||||
.s_axis_full (s_axis_full_int_s[i]),
|
||||
.s_axis_almost_full (s_axis_almost_full_int_s[i]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// write or slave logic
|
||||
generate
|
||||
|
||||
if (RATIO_TYPE) begin : big_slave
|
||||
|
||||
for (i=0; i<RATIO; i=i+1) begin
|
||||
assign s_axis_valid_int_s[i] = s_axis_valid & s_axis_ready;
|
||||
assign s_axis_tlast_int_s[i] = s_axis_tlast;
|
||||
end
|
||||
|
||||
assign s_axis_tkeep_int_s = s_axis_tkeep;
|
||||
assign s_axis_data_int_s = s_axis_data;
|
||||
// if every instance is ready, the interface is ready
|
||||
assign s_axis_ready = &(s_axis_ready_int_s);
|
||||
// if one of the atomic instance is full, s_axis_full is asserted
|
||||
assign s_axis_full = |s_axis_full_int_s;
|
||||
assign s_axis_almost_full = |s_axis_almost_full_int_s;
|
||||
// the FIFO has the same room as the atomic FIFO
|
||||
assign s_axis_room = s_axis_room_int_s[A_ADDRESS-1:0];
|
||||
|
||||
end else begin : small_slave
|
||||
|
||||
reg [RATIO-1:0] s_axis_valid_int_d = {RATIO{1'b0}};
|
||||
|
||||
for (i=0; i<RATIO; i=i+1) begin
|
||||
assign s_axis_data_int_s[A_WIDTH*i+:A_WIDTH] = s_axis_data;
|
||||
assign s_axis_tkeep_int_s[A_WIDTH/8*i+:A_WIDTH/8] = (s_axis_counter == i) ? s_axis_tkeep : {A_WIDTH/8{1'b0}};
|
||||
assign s_axis_tlast_int_s[i] = (s_axis_counter == i) ? s_axis_tlast : 1'b0;
|
||||
end
|
||||
|
||||
// insert invalid writes (TKEEP==0) in case if the TLAST arrives before the RATIO
|
||||
// boundary
|
||||
always @(*) begin
|
||||
case ({s_axis_valid, s_axis_tlast})
|
||||
2'b00 : s_axis_valid_int_d = {RATIO{1'b0}};
|
||||
2'b01 : s_axis_valid_int_d = {RATIO{1'b0}};
|
||||
2'b10 : s_axis_valid_int_d = {{RATIO-1{1'b0}}, 1'b1} << s_axis_counter;
|
||||
2'b11 : s_axis_valid_int_d = {RATIO{1'b1}} << s_axis_counter;
|
||||
endcase
|
||||
end
|
||||
assign s_axis_valid_int_s = s_axis_valid_int_d;
|
||||
|
||||
// READY/FULL/ALMOST_FULL is driven by the current atomic instance
|
||||
assign s_axis_ready = s_axis_ready_int_s >> s_axis_counter;
|
||||
assign s_axis_almost_full = s_axis_almost_full_int_s >> s_axis_counter;
|
||||
|
||||
// the FIFO has the same room as the last atomic instance
|
||||
// (NOTE: this is not the real room value, rather the value will be updated
|
||||
// after every RATIO number of writes)
|
||||
assign s_axis_full = s_axis_full_int_s[RATIO-1];
|
||||
assign s_axis_room = {s_axis_room_int_s[A_ADDRESS*(RATIO-1)+:A_ADDRESS], {$clog2(RATIO){1'b1}}};
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
// read or slave logic
|
||||
generate
|
||||
if (RATIO_TYPE) begin : small_master
|
||||
|
||||
for (i=0; i<RATIO; i=i+1) begin
|
||||
assign m_axis_ready_int_s[i] = (m_axis_counter == i) ? m_axis_ready : 1'b0;
|
||||
end
|
||||
|
||||
assign m_axis_data = m_axis_data_int_s >> (m_axis_counter*A_WIDTH) ;
|
||||
assign m_axis_tkeep = m_axis_tkeep_int_s >> (m_axis_counter*A_WIDTH/8) ;
|
||||
|
||||
// VALID/EMPTY/ALMOST_EMPTY is driven by the current atomic instance
|
||||
assign m_axis_valid = m_axis_valid_int_s >> m_axis_counter;
|
||||
|
||||
// the FIFO has the same level as the last atomic instance
|
||||
// (NOTE: this is not the real level value, rather the value will be updated
|
||||
// after every RATIO number of reads)
|
||||
assign m_axis_level = {m_axis_level_int_s[A_ADDRESS-1:0], {$clog2(RATIO){1'b0}}};
|
||||
assign m_axis_almost_empty = m_axis_almost_empty_int_s[RATIO-1];
|
||||
assign m_axis_empty = m_axis_empty_int_s[RATIO-1];
|
||||
|
||||
end else begin : big_master
|
||||
|
||||
for (i=0; i<RATIO; i=i+1) begin
|
||||
assign m_axis_ready_int_s[i] = m_axis_ready;
|
||||
end
|
||||
|
||||
for (i=0; i<RATIO; i=i+1) begin
|
||||
assign m_axis_tkeep[i*A_WIDTH/8+:A_WIDTH/8] = (m_axis_tlast_int_s[i:0] == 0) ||
|
||||
(m_axis_tlast_int_s[i]) ?
|
||||
m_axis_tkeep_int_s[i*A_WIDTH/8+:A_WIDTH/8] :
|
||||
{(A_WIDTH/8){1'b0}};
|
||||
end
|
||||
|
||||
assign m_axis_data = m_axis_data_int_s;
|
||||
// if every instance has a valid data, the interface has valid data,
|
||||
// otherwise valid is asserted only if TLAST is asserted
|
||||
assign m_axis_valid = (|m_axis_tlast_int_s) ? |m_axis_valid_int_s : &m_axis_valid_int_s;
|
||||
// if one of the atomic instance is empty, m_axis_empty should be asserted
|
||||
assign m_axis_empty = |m_axis_empty_int_s;
|
||||
assign m_axis_almost_empty = |m_axis_almost_empty_int_s;
|
||||
|
||||
// the FIFO has the same room as the atomic FIFO
|
||||
assign m_axis_level = m_axis_level_int_s[A_ADDRESS-1:0];
|
||||
|
||||
end
|
||||
|
||||
assign m_axis_tlast = (m_axis_valid) ? |m_axis_tlast_int_s : 1'b0;
|
||||
|
||||
endgenerate
|
||||
|
||||
// slave handshake counter
|
||||
|
||||
reg s_axis_tlast_d = 0;
|
||||
always @(posedge s_axis_aclk) begin
|
||||
s_axis_tlast_d <= s_axis_tlast;
|
||||
end
|
||||
|
||||
generate
|
||||
if (RATIO == 1) begin
|
||||
initial begin
|
||||
s_axis_counter = 1'b1;
|
||||
end
|
||||
end else if (RATIO > 1) begin
|
||||
if (RATIO_TYPE) begin
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (!s_axis_aresetn) begin
|
||||
s_axis_counter <= 0;
|
||||
end else begin
|
||||
if (s_axis_ready && s_axis_valid) begin
|
||||
s_axis_counter <= s_axis_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// in case of a small slave, after an active TLAST reset the counter
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (!s_axis_aresetn || s_axis_tlast_d) begin
|
||||
s_axis_counter <= 0;
|
||||
end else begin
|
||||
if (s_axis_ready && s_axis_valid) begin
|
||||
s_axis_counter <= s_axis_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// master handshake sequencer
|
||||
|
||||
generate
|
||||
if (RATIO == 1) begin
|
||||
initial begin
|
||||
m_axis_counter = 1'b0;
|
||||
end
|
||||
end else if (RATIO > 1) begin
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (!m_axis_aresetn) begin
|
||||
m_axis_counter <= 0;
|
||||
end else begin
|
||||
if (m_axis_ready && m_axis_valid) begin
|
||||
m_axis_counter <= m_axis_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,399 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_axis_fifo_asym/util_axis_fifo_asym.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="982116b256fe4badaad1b4def00c83e1"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
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||||
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||||
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|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/util_axis_fifo_asym.v">
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||||
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|
||||
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||||
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</Run>
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<Desc>Default settings for Implementation.</Desc>
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<Step Id="opt_design"/>
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||||
<Step Id="power_opt_design"/>
|
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<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
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</MsgRule>
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<Board/>
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<DashboardSummary Version="1" Minor="0">
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<Dashboards>
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<Dashboard Name="default_dashboard">
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||||
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|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
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|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
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|
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</Gadget>
|
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|
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|
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|
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|
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|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,50 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
global VIVADO_IP_LIBRARY
|
||||
|
||||
adi_ip_create util_axis_fifo_asym
|
||||
adi_ip_files util_axis_fifo_asym [list \
|
||||
"util_axis_fifo_asym.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite util_axis_fifo_asym
|
||||
|
||||
set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_axis_fifo_asym} [ipx::current_core]
|
||||
|
||||
adi_ip_add_core_dependencies [list \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
|
||||
analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
|
||||
]
|
||||
|
||||
adi_add_bus "s_axis" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{
|
||||
{"s_axis_valid" "TVALID"} \
|
||||
{"s_axis_ready" "TREADY"} \
|
||||
{"s_axis_data" "TDATA"} \
|
||||
{"s_axis_tlast" "TLAST"} \
|
||||
}
|
||||
|
||||
adi_add_bus "m_axis" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{
|
||||
{"m_axis_valid" "TVALID"} \
|
||||
{"m_axis_ready" "TREADY"} \
|
||||
{"m_axis_data" "TDATA"} \
|
||||
{"m_axis_tlast" "TLAST"} \
|
||||
}
|
||||
|
||||
adi_add_bus_clock "m_axis_aclk" "m_axis" "m_axis_aresetn"
|
||||
adi_add_bus_clock "s_axis_aclk" "s_axis" "s_axis_aresetn"
|
||||
|
||||
## TODO: Validate RD_ADDRESS_WIDTH
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,145 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ALMOST_EMPTY_THRESHOLD" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ALMOST_FULL_THRESHOLD" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "M_AXIS_REGISTERED" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "M_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "S_ADDRESS_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "S_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "TKEEP_EN" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "TLAST_EN" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } {
|
||||
# Procedure called to update ALMOST_EMPTY_THRESHOLD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } {
|
||||
# Procedure called to validate ALMOST_EMPTY_THRESHOLD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } {
|
||||
# Procedure called to update ALMOST_FULL_THRESHOLD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } {
|
||||
# Procedure called to validate ALMOST_FULL_THRESHOLD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to validate ASYNC_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } {
|
||||
# Procedure called to update M_AXIS_REGISTERED when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } {
|
||||
# Procedure called to validate M_AXIS_REGISTERED
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.M_DATA_WIDTH { PARAM_VALUE.M_DATA_WIDTH } {
|
||||
# Procedure called to update M_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.M_DATA_WIDTH { PARAM_VALUE.M_DATA_WIDTH } {
|
||||
# Procedure called to validate M_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.S_ADDRESS_WIDTH { PARAM_VALUE.S_ADDRESS_WIDTH } {
|
||||
# Procedure called to update S_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.S_ADDRESS_WIDTH { PARAM_VALUE.S_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate S_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.S_DATA_WIDTH { PARAM_VALUE.S_DATA_WIDTH } {
|
||||
# Procedure called to update S_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.S_DATA_WIDTH { PARAM_VALUE.S_DATA_WIDTH } {
|
||||
# Procedure called to validate S_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to update TKEEP_EN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to validate TKEEP_EN
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } {
|
||||
# Procedure called to update TLAST_EN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } {
|
||||
# Procedure called to validate TLAST_EN
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.S_DATA_WIDTH { MODELPARAM_VALUE.S_DATA_WIDTH PARAM_VALUE.S_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.S_DATA_WIDTH}] ${MODELPARAM_VALUE.S_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.S_ADDRESS_WIDTH { MODELPARAM_VALUE.S_ADDRESS_WIDTH PARAM_VALUE.S_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.S_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.S_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.M_DATA_WIDTH { MODELPARAM_VALUE.M_DATA_WIDTH PARAM_VALUE.M_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.M_DATA_WIDTH}] ${MODELPARAM_VALUE.M_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.M_AXIS_REGISTERED { MODELPARAM_VALUE.M_AXIS_REGISTERED PARAM_VALUE.M_AXIS_REGISTERED } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.M_AXIS_REGISTERED}] ${MODELPARAM_VALUE.M_AXIS_REGISTERED}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD { MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ALMOST_EMPTY_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD { MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD PARAM_VALUE.ALMOST_FULL_THRESHOLD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ALMOST_FULL_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.TLAST_EN { MODELPARAM_VALUE.TLAST_EN PARAM_VALUE.TLAST_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.TLAST_EN}] ${MODELPARAM_VALUE.TLAST_EN}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.TKEEP_EN { MODELPARAM_VALUE.TKEEP_EN PARAM_VALUE.TKEEP_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.TKEEP_EN}] ${MODELPARAM_VALUE.TKEEP_EN}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user