initial commit, add dds_par module
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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<spirit:version>1.0</spirit:version>
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<spirit:model>
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<spirit:view>
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<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>cic_comb</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>55312928</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>cic_comb</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>55312928</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>fe1ab863</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:ports>
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<spirit:port>
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<spirit:name>clk</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>ce</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>enable</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_STAGES')) - 1)">0</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>data_in</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">31</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>data_out</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">31</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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</spirit:ports>
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<spirit:modelParameters>
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<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
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<spirit:name>DATA_WIDTH</spirit:name>
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<spirit:displayName>Data Width</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">32</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>SEQ</spirit:name>
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<spirit:displayName>Seq</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SEQ">1</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>STAGE_WIDTH</spirit:name>
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<spirit:displayName>Stage Width</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STAGE_WIDTH">1</spirit:value>
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</spirit:modelParameter>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>NUM_STAGES</spirit:name>
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<spirit:displayName>Num Stages</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_STAGES">1</spirit:value>
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</spirit:modelParameter>
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</spirit:modelParameters>
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</spirit:model>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>cic_int.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>cic_comb.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_17b13b1f</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>cic_int.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>cic_comb.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/cic_comb_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_fe1ab863</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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</spirit:fileSets>
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<spirit:description>CIC building blocks</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>DATA_WIDTH</spirit:name>
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<spirit:displayName>Data Width</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH">32</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>SEQ</spirit:name>
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<spirit:displayName>Seq</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SEQ">1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>STAGE_WIDTH</spirit:name>
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<spirit:displayName>Stage Width</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.STAGE_WIDTH">1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>NUM_STAGES</spirit:name>
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<spirit:displayName>Num Stages</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_STAGES">1</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">cic_comb_v1_0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
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</xilinx:taxonomies>
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<xilinx:displayName>CIC building blocks</xilinx:displayName>
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<xilinx:hideInCatalogGUI>true</xilinx:hideInCatalogGUI>
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
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<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
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<xilinx:coreRevision>1</xilinx:coreRevision>
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<xilinx:coreCreationDateTime>2024-01-14T03:44:04Z</xilinx:coreCreationDateTime>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4a862b9e"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="6b1ddd6f"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e21ac4d3"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="1c2efb84"/>
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</xilinx:packagingInfo>
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</spirit:vendorExtensions>
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</spirit:component>
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