initial commit, add dds_par module
This commit is contained in:
@@ -0,0 +1,23 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := util_dacfifo
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GENERIC_DEPS += ../common/ad_b2g.v
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GENERIC_DEPS += ../common/ad_g2b.v
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GENERIC_DEPS += ../common/ad_mem.v
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GENERIC_DEPS += ../common/ad_mem_asym.v
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GENERIC_DEPS += util_dacfifo.v
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GENERIC_DEPS += util_dacfifo_bypass.v
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XILINX_DEPS += util_dacfifo_constr.xdc
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XILINX_DEPS += util_dacfifo_ip.tcl
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XILINX_DEPS += util_dacfifo_ooc.ttcl
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INTEL_DEPS += util_dacfifo_constr.sdc
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INTEL_DEPS += util_dacfifo_hw.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,457 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>util_dacfifo</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>dma_clk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>dma_clk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.DMA_CLK.ASSOCIATED_RESET">dma_rst</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>dma_rst</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>dma_rst</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>dac_clk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>dac_clk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.DAC_CLK.ASSOCIATED_RESET">dac_rst</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>dac_rst</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>dac_rst</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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||||
</spirit:portMaps>
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||||
</spirit:busInterface>
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||||
</spirit:busInterfaces>
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||||
<spirit:model>
|
||||
<spirit:views>
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||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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||||
<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>util_dacfifo</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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||||
<spirit:name>viewChecksum</spirit:name>
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||||
<spirit:value>71800a14</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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||||
<spirit:language>Verilog</spirit:language>
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||||
<spirit:modelName>util_dacfifo</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
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||||
<spirit:value>fb2fd7ae</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
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||||
<spirit:name>xilinx_xpgui</spirit:name>
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||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>7dfe8a5d</spirit:value>
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||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
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||||
</spirit:views>
|
||||
<spirit:ports>
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||||
<spirit:port>
|
||||
<spirit:name>dma_clk</spirit:name>
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||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
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||||
</spirit:port>
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<spirit:port>
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<spirit:name>dma_rst</spirit:name>
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<spirit:wire>
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||||
<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>dma_valid</spirit:name>
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<spirit:wire>
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||||
<spirit:direction>in</spirit:direction>
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||||
<spirit:wireTypeDefs>
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||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>dma_data</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">127</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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||||
</spirit:vector>
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||||
<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic_vector</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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||||
<spirit:driver>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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</spirit:driver>
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||||
</spirit:wire>
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||||
</spirit:port>
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||||
<spirit:port>
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||||
<spirit:name>dma_ready</spirit:name>
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||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
|
||||
</spirit:port>
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||||
<spirit:port>
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||||
<spirit:name>dma_xfer_req</spirit:name>
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||||
<spirit:wire>
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||||
<spirit:direction>in</spirit:direction>
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||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
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||||
</spirit:port>
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||||
<spirit:port>
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||||
<spirit:name>dma_xfer_last</spirit:name>
|
||||
<spirit:wire>
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||||
<spirit:direction>in</spirit:direction>
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||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dac_clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dac_rst</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dac_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dac_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">127</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dac_dunf</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>dac_xfer_out</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>bypass</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ADDRESS_WIDTH">6</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">128</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>util_dacfifo_ooc.ttcl</spirit:name>
|
||||
<spirit:userFileType>ttcl</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>util_dacfifo_constr.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../common/ad_b2g.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../common/ad_g2b.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../common/ad_mem.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../common/ad_mem_asym.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>util_dacfifo_bypass.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>util_dacfifo.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_3ff18447</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../common/ad_b2g.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
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</spirit:file>
|
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<spirit:file>
|
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<spirit:name>../common/ad_g2b.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
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</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../common/ad_mem.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
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</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../common/ad_mem_asym.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
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</spirit:file>
|
||||
<spirit:file>
|
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<spirit:name>util_dacfifo_bypass.v</spirit:name>
|
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>util_dacfifo.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/util_dacfifo_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_7dfe8a5d</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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</spirit:fileSets>
|
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<spirit:description>util_dacfifo_v1_0</spirit:description>
|
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<spirit:parameters>
|
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<spirit:parameter>
|
||||
<spirit:name>ADDRESS_WIDTH</spirit:name>
|
||||
<spirit:displayName>Address Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDRESS_WIDTH">6</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH">128</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">util_dacfifo_v1_0</spirit:value>
|
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</spirit:parameter>
|
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
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</xilinx:supportedFamilies>
|
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<xilinx:taxonomies>
|
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<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
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</xilinx:taxonomies>
|
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<xilinx:displayName>util_dacfifo_v1_0</xilinx:displayName>
|
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
|
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
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<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
|
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<xilinx:coreRevision>1</xilinx:coreRevision>
|
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<xilinx:coreCreationDateTime>2024-01-14T03:53:57Z</xilinx:coreCreationDateTime>
|
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</xilinx:coreExtensions>
|
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<xilinx:packagingInfo>
|
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<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
|
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1ddd9960"/>
|
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<xilinx:checksum xilinx:scope="ports" xilinx:value="f31d9715"/>
|
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5f16fa27"/>
|
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="d7f0d96a"/>
|
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</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,334 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module util_dacfifo #(
|
||||
|
||||
parameter ADDRESS_WIDTH = 6,
|
||||
parameter DATA_WIDTH = 128
|
||||
) (
|
||||
|
||||
// DMA interface
|
||||
|
||||
input dma_clk,
|
||||
input dma_rst,
|
||||
input dma_valid,
|
||||
input [(DATA_WIDTH-1):0] dma_data,
|
||||
output reg dma_ready,
|
||||
input dma_xfer_req,
|
||||
input dma_xfer_last,
|
||||
|
||||
// DAC interface
|
||||
|
||||
input dac_clk,
|
||||
input dac_rst,
|
||||
input dac_valid,
|
||||
output reg [(DATA_WIDTH-1):0] dac_data,
|
||||
output reg dac_dunf,
|
||||
output reg dac_xfer_out,
|
||||
|
||||
input bypass
|
||||
);
|
||||
|
||||
localparam FIFO_THRESHOLD_HI = {(ADDRESS_WIDTH){1'b1}} - 4;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dma_init = 1'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dma_waddr_g = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_g = 'b0;
|
||||
reg dma_bypass = 1'b0;
|
||||
reg dma_bypass_m1 = 1'b0;
|
||||
reg dma_xfer_req_d1 = 1'b0;
|
||||
reg dma_xfer_req_d2 = 1'b0;
|
||||
reg dma_xfer_out_fifo = 1'b0;
|
||||
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_waddr = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_waddr_m1 = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_waddr_m2 = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_addr_diff = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m1 = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m2 = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_lastaddr = 'b0;
|
||||
reg dac_mem_ready = 1'b0;
|
||||
reg dac_xfer_req_m1 = 1'b0;
|
||||
reg dac_xfer_req = 1'b0;
|
||||
reg dac_xfer_req_d = 1'b0;
|
||||
reg dac_xfer_out_fifo = 1'b0;
|
||||
reg dac_xfer_out_fifo_m1 = 1'b0;
|
||||
reg dac_xfer_out_fifo_d = 1'b0;
|
||||
reg dac_bypass = 1'b0;
|
||||
reg dac_bypass_m1 = 1'b0;
|
||||
|
||||
// internal wires
|
||||
|
||||
wire dma_rst_int_s;
|
||||
wire dma_wren_s;
|
||||
wire dma_xfer_posedge_s;
|
||||
wire dma_ready_bypass_s;
|
||||
wire [(DATA_WIDTH-1):0] dac_data_fifo_s;
|
||||
wire [(DATA_WIDTH-1):0] dac_data_bypass_s;
|
||||
wire [ADDRESS_WIDTH:0] dac_addr_diff_s;
|
||||
wire [(ADDRESS_WIDTH-1):0] dma_waddr_b2g_s;
|
||||
wire [(ADDRESS_WIDTH-1):0] dac_waddr_g2b_s;
|
||||
wire [(ADDRESS_WIDTH-1):0] dac_lastaddr_g2b_s;
|
||||
wire dac_mem_ren_s;
|
||||
wire dac_xfer_posedge_s;
|
||||
wire dac_rst_int_s;
|
||||
|
||||
// internal reset generation
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
dma_xfer_req_d1 <= dma_xfer_req;
|
||||
dma_xfer_req_d2 <= dma_xfer_req_d1;
|
||||
end
|
||||
assign dma_xfer_posedge_s = ~dma_xfer_req_d2 & dma_xfer_req_d1;
|
||||
|
||||
// status register indicating that the module is in initialization phase
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if ((dma_rst == 1'b1) || (dma_xfer_last == 1'b1)) begin
|
||||
dma_init <= 1'b0;
|
||||
end else begin
|
||||
if (dma_xfer_posedge_s == 1'b1) begin
|
||||
dma_init <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// if the module is not in initialization phase, it should go
|
||||
// into reset at a positive edge of dma_xfer_req
|
||||
|
||||
assign dma_rst_int_s = dma_rst | (dma_xfer_posedge_s & ~dma_init);
|
||||
|
||||
// DMA / Write interface
|
||||
|
||||
// write address generation
|
||||
|
||||
assign dma_wren_s = dma_valid & dma_ready;
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if(dma_rst_int_s == 1'b1) begin
|
||||
dma_waddr <= 'b0;
|
||||
dma_waddr_g <= 'b0;
|
||||
dma_xfer_out_fifo <= 1'b0;
|
||||
end else begin
|
||||
if (dma_wren_s == 1'b1) begin
|
||||
dma_waddr <= dma_waddr + 1'b1;
|
||||
end
|
||||
if (dma_xfer_last == 1'b1) begin
|
||||
dma_waddr <= 'b0;
|
||||
dma_xfer_out_fifo <= 1'b1;
|
||||
end
|
||||
dma_waddr_g <= dma_waddr_b2g_s;
|
||||
end
|
||||
end
|
||||
|
||||
ad_b2g #(
|
||||
.DATA_WIDTH (ADDRESS_WIDTH)
|
||||
) i_dma_waddr_b2g (
|
||||
.din (dma_waddr),
|
||||
.dout (dma_waddr_b2g_s));
|
||||
|
||||
// save the last write address
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if (dma_rst_int_s == 1'b1) begin
|
||||
dma_lastaddr_g <= 'b0;
|
||||
end else begin
|
||||
if (dma_bypass == 1'b0) begin
|
||||
dma_lastaddr_g <= (dma_xfer_last == 1'b1)? dma_waddr_b2g_s : dma_lastaddr_g;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// DAC / Read interface
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_xfer_req_m1 <= dma_xfer_req;
|
||||
dac_xfer_req <= dac_xfer_req_m1;
|
||||
dac_xfer_req_d <= dac_xfer_req;
|
||||
end
|
||||
assign dac_xfer_posedge_s = ~dac_xfer_req_d & dac_xfer_req;
|
||||
|
||||
// we can reset the DAC side at each positive edge of xfer_req, even if
|
||||
// sometimes the reset is redundant
|
||||
assign dac_rst_int_s = dac_xfer_req | dac_rst;
|
||||
|
||||
assign dac_addr_diff_s = {1'b1, dac_waddr} - dac_raddr;
|
||||
|
||||
// The memory module is ready if it's not empty
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst_int_s == 1'b1) begin
|
||||
dac_addr_diff <= 'b0;
|
||||
dac_waddr_m1 <= 'b0;
|
||||
dac_waddr_m2 <= 'b0;
|
||||
dac_waddr <= 'b0;
|
||||
dac_mem_ready <= 1'b0;
|
||||
end else begin
|
||||
dac_waddr_m1 <= dma_waddr_g;
|
||||
dac_waddr_m2 <= dac_waddr_m1;
|
||||
dac_waddr <= dac_waddr_g2b_s;
|
||||
dac_addr_diff <= dac_addr_diff_s[ADDRESS_WIDTH-1:0];
|
||||
if (dac_addr_diff > 0) begin
|
||||
dac_mem_ready <= 1'b1;
|
||||
end else begin
|
||||
dac_mem_ready <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ad_g2b #(
|
||||
.DATA_WIDTH (ADDRESS_WIDTH)
|
||||
) i_dac_waddr_g2b (
|
||||
.din (dac_waddr_m2),
|
||||
.dout (dac_waddr_g2b_s));
|
||||
|
||||
// sync lastaddr to dac clock domain
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst_int_s == 1'b1) begin
|
||||
dac_lastaddr_m1 <= 1'b0;
|
||||
dac_lastaddr_m2 <= 1'b0;
|
||||
dac_xfer_out_fifo_m1 <= 1'b0;
|
||||
dac_xfer_out_fifo <= 1'b0;
|
||||
dac_xfer_out_fifo_d <= 1'b0;
|
||||
end else begin
|
||||
dac_lastaddr_m1 <= dma_lastaddr_g;
|
||||
dac_lastaddr_m2 <= dac_lastaddr_m1;
|
||||
dac_lastaddr <= dac_lastaddr_g2b_s;
|
||||
dac_xfer_out_fifo_m1 <= dma_xfer_out_fifo;
|
||||
dac_xfer_out_fifo <= dac_xfer_out_fifo_m1;
|
||||
if (dac_valid)
|
||||
dac_xfer_out_fifo_d <= dac_xfer_out_fifo;
|
||||
end
|
||||
end
|
||||
|
||||
ad_g2b #(
|
||||
.DATA_WIDTH (ADDRESS_WIDTH)
|
||||
) i_dac_lastaddr_g2b (
|
||||
.din (dac_lastaddr_m2),
|
||||
.dout (dac_lastaddr_g2b_s));
|
||||
|
||||
// generate dac read address
|
||||
|
||||
assign dac_mem_ren_s = (dac_bypass == 1'b1) ? (dac_valid & dac_mem_ready) :
|
||||
(dac_valid & dac_xfer_out_fifo);
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst_int_s == 1'b1) begin
|
||||
dac_raddr <= 'b0;
|
||||
end else begin
|
||||
if (dac_mem_ren_s == 1'b1) begin
|
||||
if (dac_lastaddr == 'b0 || dac_raddr != dac_lastaddr) begin
|
||||
dac_raddr <= dac_raddr + 1'b1;
|
||||
end else begin
|
||||
dac_raddr <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// memory instantiation
|
||||
|
||||
ad_mem #(
|
||||
.ADDRESS_WIDTH (ADDRESS_WIDTH),
|
||||
.DATA_WIDTH (DATA_WIDTH)
|
||||
) i_mem_fifo (
|
||||
.clka (dma_clk),
|
||||
.wea (dma_wren_s),
|
||||
.addra (dma_waddr),
|
||||
.dina (dma_data),
|
||||
.clkb (dac_clk),
|
||||
.reb (1'b1),
|
||||
.addrb (dac_raddr),
|
||||
.doutb (dac_data_fifo_s));
|
||||
|
||||
// define underflow
|
||||
// underflow make sense just if bypass is enabled
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst_int_s == 1'b1) begin
|
||||
dac_dunf <= 1'b0;
|
||||
end else begin
|
||||
dac_dunf <= (dac_bypass == 1'b1) ? (dac_valid & dac_xfer_req & ~dac_mem_ren_s) : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// bypass logic
|
||||
|
||||
util_dacfifo_bypass #(
|
||||
.DAC_DATA_WIDTH (DATA_WIDTH),
|
||||
.DMA_DATA_WIDTH (DATA_WIDTH)
|
||||
) i_dacfifo_bypass (
|
||||
.dma_clk(dma_clk),
|
||||
.dma_data(dma_data),
|
||||
.dma_ready(dma_ready),
|
||||
.dma_ready_out(dma_ready_bypass_s),
|
||||
.dma_valid(dma_valid),
|
||||
.dma_xfer_req(dma_xfer_req),
|
||||
.dac_clk(dac_clk),
|
||||
.dac_rst(dac_rst),
|
||||
.dac_valid(dac_valid),
|
||||
.dac_data(dac_data_bypass_s),
|
||||
.dac_dunf(dac_dunf_bypass_s));
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
dma_bypass_m1 <= bypass;
|
||||
dma_bypass <= dma_bypass_m1;
|
||||
end
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_bypass_m1 <= bypass;
|
||||
dac_bypass <= dac_bypass_m1;
|
||||
end
|
||||
|
||||
// the util_dacfifo is always ready for the DMA
|
||||
always @(posedge dma_clk) begin
|
||||
dma_ready <= (dma_bypass == 1'b1) ? dma_ready_bypass_s : 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_valid) begin
|
||||
dac_data <= (dac_bypass == 1'b1) ? dac_data_bypass_s : dac_data_fifo_s;
|
||||
end
|
||||
// this signal along with the dac_valid validate the data coming out from the buffer
|
||||
dac_xfer_out <= (dac_bypass == 1'b1) ? dac_xfer_req : dac_xfer_out_fifo_d;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,441 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
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|
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<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,269 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module util_dacfifo_bypass #(
|
||||
|
||||
parameter DAC_DATA_WIDTH = 64,
|
||||
parameter DMA_DATA_WIDTH = 64
|
||||
) (
|
||||
|
||||
// DMA FIFO interface
|
||||
|
||||
input dma_clk,
|
||||
input [(DMA_DATA_WIDTH-1):0] dma_data,
|
||||
input dma_ready,
|
||||
output reg dma_ready_out,
|
||||
input dma_valid,
|
||||
|
||||
// request and synchronization
|
||||
|
||||
input dma_xfer_req,
|
||||
|
||||
// DAC FIFO interface
|
||||
|
||||
input dac_clk,
|
||||
input dac_rst,
|
||||
input dac_valid,
|
||||
output reg [(DAC_DATA_WIDTH-1):0] dac_data,
|
||||
output reg dac_dunf
|
||||
);
|
||||
|
||||
// supported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
|
||||
|
||||
localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH :
|
||||
DAC_DATA_WIDTH/DMA_DATA_WIDTH;
|
||||
localparam DAC_ADDRESS_WIDTH = 4;
|
||||
localparam DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :
|
||||
(MEM_RATIO == 2) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 1) : (DAC_ADDRESS_WIDTH + 1)) :
|
||||
(MEM_RATIO == 4) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH + 2)) :
|
||||
((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 3) : (DAC_ADDRESS_WIDTH + 3));
|
||||
localparam DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4;
|
||||
localparam DAC_BUF_THRESHOLD_LO = 4;
|
||||
|
||||
reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0;
|
||||
reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0;
|
||||
reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0;
|
||||
reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0;
|
||||
reg dac_mem_rea = 1'b0;
|
||||
reg dma_rst_m1 = 1'b0;
|
||||
reg dma_rst = 1'b0;
|
||||
reg [DMA_ADDRESS_WIDTH-1:0] dma_mem_addr_diff = 'd0;
|
||||
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0;
|
||||
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0;
|
||||
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0;
|
||||
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 'd0;
|
||||
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 'd0;
|
||||
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_raddr_s;
|
||||
wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_s;
|
||||
wire dma_mem_wea_s;
|
||||
wire dac_mem_rea_s;
|
||||
wire [(DAC_DATA_WIDTH-1):0] dac_mem_rdata_s;
|
||||
wire [DMA_ADDRESS_WIDTH:0] dma_address_diff_s;
|
||||
wire dac_mem_empty_s;
|
||||
|
||||
wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s;
|
||||
wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s;
|
||||
wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;
|
||||
wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
|
||||
|
||||
// an asymmetric memory, storage element of the FIFO
|
||||
|
||||
ad_mem_asym #(
|
||||
.A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
|
||||
.A_DATA_WIDTH (DMA_DATA_WIDTH),
|
||||
.B_ADDRESS_WIDTH (DAC_ADDRESS_WIDTH),
|
||||
.B_DATA_WIDTH (DAC_DATA_WIDTH)
|
||||
) i_mem_asym (
|
||||
.clka (dma_clk),
|
||||
.wea (dma_mem_wea_s),
|
||||
.addra (dma_mem_waddr),
|
||||
.dina (dma_data),
|
||||
.clkb (dac_clk),
|
||||
.reb (1'b1),
|
||||
.addrb (dac_mem_raddr),
|
||||
.doutb (dac_mem_rdata_s));
|
||||
|
||||
// DMA reset is brought from dac domain
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
dma_rst_m1 <= dac_rst;
|
||||
dma_rst <= dma_rst_m1;
|
||||
end
|
||||
|
||||
// write address generation for the asymmetric FIFO
|
||||
|
||||
assign dma_mem_wea_s = dma_valid & dma_ready;
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if (dma_rst == 1'b1) begin
|
||||
dma_mem_waddr <= 'h0;
|
||||
dma_mem_waddr_g <= 'h0;
|
||||
end else begin
|
||||
if (dma_mem_wea_s == 1'b1) begin
|
||||
dma_mem_waddr <= dma_mem_waddr + 1'b1;
|
||||
end
|
||||
dma_mem_waddr_g <= dma_mem_waddr_b2g_s;
|
||||
end
|
||||
end
|
||||
|
||||
ad_b2g #(
|
||||
.DATA_WIDTH (DMA_ADDRESS_WIDTH)
|
||||
) i_dma_mem_waddr_b2g (
|
||||
.din (dma_mem_waddr),
|
||||
.dout (dma_mem_waddr_b2g_s));
|
||||
|
||||
// FIFO request data until reaches the high threshold.
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if (dma_rst == 1'b1) begin
|
||||
dma_mem_addr_diff <= 'b0;
|
||||
dma_mem_raddr_m1 <= 'b0;
|
||||
dma_mem_raddr_m2 <= 'b0;
|
||||
dma_mem_raddr <= 'b0;
|
||||
dma_ready_out <= 1'b0;
|
||||
end else begin
|
||||
dma_mem_raddr_m1 <= dac_mem_raddr_g;
|
||||
dma_mem_raddr_m2 <= dma_mem_raddr_m1;
|
||||
dma_mem_raddr <= dma_mem_raddr_m2_g2b_s;
|
||||
dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0];
|
||||
if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
|
||||
dma_ready_out <= 1'b0;
|
||||
end else begin
|
||||
dma_ready_out <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ad_g2b #(
|
||||
.DATA_WIDTH (DAC_ADDRESS_WIDTH)
|
||||
) i_dma_mem_raddr_g2b (
|
||||
.din (dma_mem_raddr_m2),
|
||||
.dout (dma_mem_raddr_m2_g2b_s));
|
||||
|
||||
// relative address offset on DMA domain
|
||||
assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
|
||||
assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
|
||||
((MEM_RATIO == 1) ? (dma_mem_raddr) :
|
||||
(MEM_RATIO == 2) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):1]) :
|
||||
(MEM_RATIO == 4) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):2]) : (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):3])) :
|
||||
((MEM_RATIO == 1) ? (dma_mem_raddr) :
|
||||
(MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) :
|
||||
(MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0}));
|
||||
|
||||
// relative address offset on DAC domain
|
||||
assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ?
|
||||
((MEM_RATIO == 1) ? (dac_mem_waddr) :
|
||||
(MEM_RATIO == 2) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):1]) :
|
||||
(MEM_RATIO == 4) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):2]) : (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):3])) :
|
||||
((MEM_RATIO == 1) ? (dac_mem_waddr) :
|
||||
(MEM_RATIO == 2) ? ({dac_mem_waddr, 1'b0}) :
|
||||
(MEM_RATIO == 4) ? ({dac_mem_waddr, 2'b0}) : ({dac_mem_waddr, 3'b0}));
|
||||
|
||||
assign dac_mem_empty_s = (dac_mem_waddr_s == dac_mem_raddr) ? 1'b1 : 1'b0;
|
||||
assign dac_mem_rea_s = dac_valid & !dac_mem_empty_s;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst == 1'b1) begin
|
||||
dac_mem_raddr <= 'h0;
|
||||
dac_mem_raddr_g <= 'h0;
|
||||
end else begin
|
||||
if (dac_mem_rea_s == 1'b1) begin
|
||||
dac_mem_raddr <= dac_mem_raddr + 1'b1;
|
||||
end
|
||||
dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
|
||||
end
|
||||
end
|
||||
|
||||
// compensate the read latency of the memory
|
||||
always @(posedge dac_clk) begin
|
||||
dac_mem_rea <= dac_mem_rea_s;
|
||||
end
|
||||
|
||||
ad_b2g #(
|
||||
.DATA_WIDTH (DAC_ADDRESS_WIDTH)
|
||||
) i_dac_mem_raddr_b2g (
|
||||
.din (dac_mem_raddr),
|
||||
.dout (dac_mem_raddr_b2g_s));
|
||||
|
||||
// transfer the write address into the DAC's clock domain
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst == 1'b1) begin
|
||||
dac_mem_waddr_m1 <= 'b0;
|
||||
dac_mem_waddr_m2 <= 'b0;
|
||||
dac_mem_waddr <= 'b0;
|
||||
end else begin
|
||||
dac_mem_waddr_m1 <= dma_mem_waddr_g;
|
||||
dac_mem_waddr_m2 <= dac_mem_waddr_m1;
|
||||
dac_mem_waddr <= dac_mem_waddr_m2_g2b_s;
|
||||
end
|
||||
end
|
||||
|
||||
ad_g2b #(
|
||||
.DATA_WIDTH (DMA_ADDRESS_WIDTH)
|
||||
) i_dac_mem_waddr_g2b (
|
||||
.din (dac_mem_waddr_m2),
|
||||
.dout (dac_mem_waddr_m2_g2b_s));
|
||||
|
||||
// define underflow
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst == 1'b1) begin
|
||||
dac_dunf <= 1'b0;
|
||||
end else begin
|
||||
if (dac_valid == 1'b1) begin
|
||||
dac_dunf <= dac_mem_empty_s;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// DAC data output logic - make sure that the data output is zero between
|
||||
// transfers
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_dunf == 1'b1) begin
|
||||
dac_data <= 0;
|
||||
end else begin
|
||||
dac_data <= dac_mem_rdata_s;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,19 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
set_false_path -to [get_registers *dac_bypass_m1*]
|
||||
set_false_path -to [get_registers *dma_bypass_m1*]
|
||||
|
||||
set_false_path -from [get_registers *dac_raddr_g*] -to [get_registers *dma_raddr_m1*]
|
||||
set_false_path -from [get_registers *dma_waddr_g*] -to [get_registers *dac_waddr_m1*]
|
||||
set_false_path -from [get_registers *dma_lastaddr_g*] -to [get_registers *dac_lastaddr_m1*]
|
||||
set_false_path -from [get_registers *dma_xfer_out_fifo*] -to [get_registers *dac_xfer_out_fifo_m1*]
|
||||
|
||||
set_false_path -from [get_registers *dma_mem_waddr_g*] -to [get_registers *dac_mem_waddr_m1*]
|
||||
set_false_path -from [get_registers *dac_mem_raddr_g*] -to [get_registers *dma_mem_raddr_m1*]
|
||||
set_false_path -to [get_registers *dma_rst_m1*]
|
||||
set_false_path -to [get_registers *dac_xfer_req_m1*]
|
||||
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
set_property ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *dac_waddr_m*}] \
|
||||
[get_cells -hierarchical -filter {name =~ *dac_lastaddr_m*}] \
|
||||
[get_cells -hierarchical -filter {name =~ *dac_xfer_out_*}] \
|
||||
[get_cells -hierarchical -filter {name =~ *dma_bypass*}] \
|
||||
[get_cells -hierarchical -filter {name =~ *dac_bypass*}] \
|
||||
[get_cells -hierarchical -filter {name =~ *dac_xfer_req_m*}]
|
||||
|
||||
set_false_path -from [get_cells -hierarchical -filter {name =~ *dma_waddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hierarchical -filter {name =~ *dac_waddr_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hierarchical -filter {name =~ *dma_lastaddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hierarchical -filter {name =~ *dac_lastaddr_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hierarchical -filter {name =~ *dma_xfer_out_fifo* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hierarchical -filter {name =~ *dac_xfer_out_fifo_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hierarchical -filter {name =~ *dac_bypass_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hierarchical -filter {name =~ *dma_bypass_m1* && IS_SEQUENTIAL}]
|
||||
|
||||
# util_dacfifo_bypass CDC false-paths
|
||||
|
||||
set_property ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *dac_mem_*_m*}] \
|
||||
[get_cells -hierarchical -filter {name =~ *dma_mem_*_m*}] \
|
||||
[get_cells -hierarchical -filter {name =~ *dma_rst_m1*}] \
|
||||
|
||||
set_false_path -from [get_cells -hierarchical -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hierarchical -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hierarchical -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hierarchical -filter {name =~ */dma_mem_raddr_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hierarchical -filter {name =~ */dma_rst_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hierarchical -filter {name =~ */dac_xfer_req_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hierarchical -filter {name =~ */dma_xfer_req* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hierarchical -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
|
||||
|
||||
@@ -0,0 +1,48 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
source ../../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create util_dacfifo {UTIL DAC FIFO Interface}
|
||||
ad_ip_files util_dacfifo [list\
|
||||
$ad_hdl_dir/library/common/ad_mem.v \
|
||||
$ad_hdl_dir/library/common/ad_mem_asym.v \
|
||||
$ad_hdl_dir/library/common/ad_b2g.v \
|
||||
$ad_hdl_dir/library/common/ad_g2b.v \
|
||||
util_dacfifo.v \
|
||||
util_dacfifo_bypass.v \
|
||||
util_dacfifo_constr.sdc]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
|
||||
ad_ip_parameter ADDRESS_WIDTH INTEGER 6
|
||||
ad_ip_parameter DATA_WIDTH INTEGER 128
|
||||
|
||||
# interfaces
|
||||
|
||||
ad_interface clock dma_clk input 1 clk
|
||||
ad_interface reset dma_rst input 1 if_dma_clk
|
||||
ad_interface signal dma_xfer_req input 1 xfer_req
|
||||
|
||||
add_interface s_axis axi4stream end
|
||||
set_interface_property s_axis associatedClock if_dma_clk
|
||||
set_interface_property s_axis associatedReset if_dma_rst
|
||||
add_interface_port s_axis dma_valid tvalid Input 1
|
||||
add_interface_port s_axis dma_xfer_last tlast Input 1
|
||||
add_interface_port s_axis dma_ready tready Output 1
|
||||
add_interface_port s_axis dma_data tdata Input DATA_WIDTH
|
||||
|
||||
ad_interface clock dac_clk input 1
|
||||
ad_interface reset dac_rst input 1 if_dac_clk
|
||||
ad_interface signal dac_valid input 1 valid
|
||||
ad_interface signal dac_data output DATA_WIDTH data
|
||||
ad_interface signal dac_xfer_out output 1 xfer_req
|
||||
ad_interface signal dac_dunf output 1 unf
|
||||
|
||||
ad_interface signal bypass input 1 bypass
|
||||
|
||||
@@ -0,0 +1,32 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
# ip
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create util_dacfifo
|
||||
adi_ip_files util_dacfifo [list \
|
||||
"$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
|
||||
"$ad_hdl_dir/library/common/ad_b2g.v" \
|
||||
"$ad_hdl_dir/library/common/ad_g2b.v" \
|
||||
"util_dacfifo.v" \
|
||||
"util_dacfifo_bypass.v" \
|
||||
"util_dacfifo_ooc.ttcl" \
|
||||
"util_dacfifo_constr.xdc"]
|
||||
|
||||
|
||||
adi_ip_properties_lite util_dacfifo
|
||||
|
||||
adi_ip_ttcl util_dacfifo "util_dacfifo_ooc.ttcl"
|
||||
|
||||
ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: setFileUsedIn { out_of_context synthesis implementation } :>
|
||||
<: ;#Component and file information :>
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName $ComponentName :>
|
||||
<: setFileExtension "_ooc.xdc" :>
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation.
|
||||
# These are default values for timing driven synthesis during OOC flow.
|
||||
# These values will be overwritten during implementation with information
|
||||
# from top level.
|
||||
|
||||
create_clock -name dma_clk -period 8 [get_ports dma_clk]
|
||||
create_clock -name dac_clk -period 3.2 [get_ports dac_clk]
|
||||
|
||||
################################################################################
|
||||
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to validate ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user