initial commit, add dds_par module
This commit is contained in:
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := util_do_ram
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GENERIC_DEPS += ../common/ad_mem_asym.v
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GENERIC_DEPS += util_do_ram.v
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XILINX_DEPS += util_do_ram_constr.xdc
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XILINX_DEPS += util_do_ram_ip.tcl
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XILINX_DEPS += util_do_ram_ooc.ttcl
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XILINX_DEPS += ../interfaces/if_do_ctrl.xml
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XILINX_DEPS += ../interfaces/if_do_ctrl_rtl.xml
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XILINX_INTERFACE_DEPS += interfaces
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include ../scripts/library.mk
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File diff suppressed because it is too large
Load Diff
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// Constraints:
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`timescale 1ns/100ps
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module util_do_ram #(
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parameter SRC_DATA_WIDTH = 512,
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parameter DST_DATA_WIDTH = 128,
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parameter LENGTH_WIDTH = 16
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) (
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input wr_request_enable,
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input wr_request_valid,
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output reg wr_request_ready = 1'b0,
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input [LENGTH_WIDTH-1:0] wr_request_length,
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output reg [LENGTH_WIDTH-1:0] wr_response_measured_length = 'h0,
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output reg wr_response_eot = 1'b0,
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input rd_request_enable,
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input rd_request_valid,
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output rd_request_ready,
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input [LENGTH_WIDTH-1:0] rd_request_length,
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output rd_response_eot,
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// Slave streaming AXI interface
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input s_axis_aclk,
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input s_axis_aresetn,
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output reg s_axis_ready = 1'b0,
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input s_axis_valid,
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input [SRC_DATA_WIDTH-1:0] s_axis_data,
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input [SRC_DATA_WIDTH/8-1:0] s_axis_strb,
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input [SRC_DATA_WIDTH/8-1:0] s_axis_keep,
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input [0:0] s_axis_user,
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input s_axis_last,
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// Master streaming AXI interface
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input m_axis_aclk,
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input m_axis_aresetn,
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input m_axis_ready,
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output m_axis_valid,
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output [DST_DATA_WIDTH-1:0] m_axis_data,
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output [DST_DATA_WIDTH/8-1:0] m_axis_strb,
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output [DST_DATA_WIDTH/8-1:0] m_axis_keep,
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output [0:0] m_axis_user,
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output m_axis_last
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);
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// src = s_axis_* = wr
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// dst = m_axis_* = rd
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//
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localparam RAM_LATENCY = 2;
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localparam SRC_ADDR_ALIGN = $clog2(SRC_DATA_WIDTH/8);
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localparam DST_ADDR_ALIGN = $clog2(DST_DATA_WIDTH/8);
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localparam SRC_ADDRESS_WIDTH = LENGTH_WIDTH - SRC_ADDR_ALIGN;
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localparam DST_ADDRESS_WIDTH = LENGTH_WIDTH - DST_ADDR_ALIGN;
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wire wr_enable;
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wire [DST_DATA_WIDTH-1:0] rd_data;
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wire [1:0] rd_fifo_room;
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wire rd_enable;
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wire rd_last_beat;
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wire rd_fifo_s_ready;
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wire rd_fifo_s_valid;
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reg [SRC_ADDRESS_WIDTH-1:0] wr_length = 'h0;
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reg [SRC_ADDRESS_WIDTH-1:0] wr_addr = 'h0;
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reg [DST_DATA_WIDTH-1:0] rd_data_l2 = 'h0;
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reg [DST_ADDRESS_WIDTH-1:0] rd_length = 'h0;
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reg [DST_ADDRESS_WIDTH-1:0] rd_addr = 'h0;
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reg rd_pending = 1'b0;
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always @(posedge s_axis_aclk) begin
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if (~s_axis_aresetn)
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wr_request_ready <= 1'b1;
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else if (wr_request_valid)
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wr_request_ready <= 1'b0;
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else if (wr_response_eot)
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wr_request_ready <= 1'b1;
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end
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always @(posedge s_axis_aclk) begin
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if (wr_request_valid & wr_request_ready)
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wr_length <= wr_request_length[LENGTH_WIDTH-1:SRC_ADDR_ALIGN];
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end
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wire wr_last_beat;
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assign wr_last_beat = s_axis_valid & s_axis_ready & ((wr_addr == wr_length) | s_axis_last);
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always @(posedge s_axis_aclk) begin
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if (~wr_request_enable)
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s_axis_ready <= 1'b0;
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else if (wr_request_valid & wr_request_ready)
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s_axis_ready <= 1'b1;
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else if (wr_last_beat) begin
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s_axis_ready <= 1'b0;
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end
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end
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always @(posedge s_axis_aclk) begin
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if (s_axis_valid & s_axis_ready)
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wr_response_eot <= s_axis_last | (wr_addr == wr_length);
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else
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wr_response_eot <= 1'b0;
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end
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always @(posedge s_axis_aclk) begin
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if (wr_last_beat)
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wr_response_measured_length <= {wr_addr, {SRC_ADDR_ALIGN{1'b1}}};
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end
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reg wr_full = 1'b0;
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// Protect against larger transfers than storage
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always @(posedge s_axis_aclk) begin
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if (wr_request_valid & wr_request_ready)
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wr_full <= 1'b0;
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else if (&wr_addr & (s_axis_valid & s_axis_ready))
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wr_full <= 1'b1;
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end
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// Do not roll over write address
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always @(posedge s_axis_aclk) begin
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if (~wr_request_enable | wr_last_beat)
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wr_addr <= 'h0;
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else if (s_axis_valid & s_axis_ready & (~(&wr_addr)))
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wr_addr <= wr_addr + 1;
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end
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assign wr_enable = s_axis_valid & s_axis_ready & ~wr_full;
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (SRC_ADDRESS_WIDTH),
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.A_DATA_WIDTH (SRC_DATA_WIDTH),
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.B_ADDRESS_WIDTH (DST_ADDRESS_WIDTH),
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.B_DATA_WIDTH (DST_DATA_WIDTH)
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) i_mem (
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.clka (s_axis_aclk),
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.wea (wr_enable),
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.addra (wr_addr),
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.dina (s_axis_data),
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.clkb (m_axis_aclk),
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.reb (1'b1),
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.addrb (rd_addr),
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.doutb (rd_data));
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reg rd_active = 1'b0;
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reg [1:0] rd_req_cnt = 2'b0;
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always @(posedge m_axis_aclk) begin
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if (~rd_request_enable)
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rd_req_cnt <= 2'b0;
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else if (rd_request_valid & rd_request_ready)
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rd_req_cnt <= rd_req_cnt + 2'b1;
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else if (rd_response_eot)
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rd_req_cnt <= rd_req_cnt - 2'b1;
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end
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assign rd_request_ready = ~rd_req_cnt[1];
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always @(posedge m_axis_aclk) begin
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if (rd_request_valid & rd_request_ready)
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rd_length <= rd_request_length[LENGTH_WIDTH-1:DST_ADDR_ALIGN];
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end
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wire rd_early_finish;
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assign rd_early_finish = rd_active & ~rd_request_enable;
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assign rd_last_beat = (rd_addr == rd_length) & rd_enable;
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assign rd_response_eot = (m_axis_last & m_axis_valid & m_axis_ready) || rd_early_finish;
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// Read logic
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always @(posedge m_axis_aclk) begin
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if (~rd_request_enable)
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rd_active <= 1'b0;
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else if (rd_request_valid & rd_request_ready)
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rd_active <= 1'b1;
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else if (rd_last_beat)
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rd_active <= rd_req_cnt == 2;
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end
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assign rd_enable = rd_fifo_s_ready & rd_active &
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(rd_fifo_room >= (m_axis_valid&m_axis_ready ? 1 : RAM_LATENCY));
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always @(posedge m_axis_aclk) begin
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if (~rd_request_enable | rd_last_beat)
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rd_addr <= 'h0;
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else if (rd_enable)
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rd_addr <= rd_addr + 1;
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end
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// Delay read enable with latency cycles
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// <TODO> make this depend on parameter
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reg rd_valid_l1 = 1'b0;
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reg rd_valid_l2 = 1'b0;
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reg rd_last_l1 = 1'b0;
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reg rd_last_l2 = 1'b0;
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always @(posedge m_axis_aclk) begin
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rd_valid_l1 <= rd_enable;
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rd_last_l1 <= rd_last_beat;
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end
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// Extra pipeline to be sucked in by the BRAM/URAM output stage
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always @(posedge m_axis_aclk) begin
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if (rd_valid_l1)
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rd_data_l2 <= rd_data;
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||||
end
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always @(posedge m_axis_aclk) begin
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if (rd_valid_l1)
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rd_valid_l2 <= 1'b1;
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else if (rd_fifo_s_ready)
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||||
rd_valid_l2 <= 1'b0;
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if (rd_valid_l1)
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rd_last_l2 <= rd_last_l1;
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||||
end
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||||
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assign rd_fifo_s_valid = rd_valid_l2;
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||||
// Read datapath to AXIS logic
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||||
util_axis_fifo #(
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||||
.DATA_WIDTH(DST_DATA_WIDTH+1),
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||||
.ADDRESS_WIDTH(2),
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||||
.ASYNC_CLK(0),
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||||
.M_AXIS_REGISTERED(0)
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||||
) i_rd_fifo (
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||||
.s_axis_aclk(m_axis_aclk),
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||||
.s_axis_aresetn(m_axis_aresetn & rd_request_enable),
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||||
.s_axis_valid(rd_fifo_s_valid),
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||||
.s_axis_ready(rd_fifo_s_ready),
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||||
.s_axis_full(),
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||||
.s_axis_data({rd_last_l2,rd_data_l2}),
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||||
.s_axis_room(rd_fifo_room),
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||||
.s_axis_tkeep(),
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||||
.s_axis_tlast(),
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||||
.s_axis_almost_full(),
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||||
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||||
.m_axis_aclk(m_axis_aclk),
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||||
.m_axis_aresetn(m_axis_aresetn & rd_request_enable),
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||||
.m_axis_valid(m_axis_valid),
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||||
.m_axis_ready(m_axis_ready),
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||||
.m_axis_data({m_axis_last,m_axis_data}),
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||||
.m_axis_level(),
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||||
.m_axis_empty(),
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||||
.m_axis_tkeep(),
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||||
.m_axis_tlast(),
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.m_axis_almost_empty());
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endmodule
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@@ -0,0 +1,413 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_do_ram/util_do_ram.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="0bf723676944490a9ab3c4490ea9a05f"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/ad_mem_asym.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_do_ram.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_do_ram_ooc.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="util_do_ram"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/util_do_ram_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="12"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,81 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create util_do_ram
|
||||
adi_ip_files util_do_ram [list \
|
||||
"../common/ad_mem_asym.v" \
|
||||
"util_do_ram_constr.xdc" \
|
||||
"util_do_ram_ooc.ttcl" \
|
||||
"util_do_ram.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite util_do_ram
|
||||
adi_ip_ttcl util_dacfifo "util_do_ram_ooc.ttcl"
|
||||
|
||||
set_property PROCESSING_ORDER LATE [ipx::get_files util_do_ram_constr.xdc \
|
||||
-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
|
||||
-filter {NAME =~ *synthesis*}]]
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:util_cdc:1.0 \
|
||||
analog.com:user:util_axis_fifo:1.0 \
|
||||
}
|
||||
|
||||
set_property display_name "ADI Data Offload RAM Storage" [ipx::current_core]
|
||||
set_property description "Serves as storage for the Data Offload core, using Block RAM or URAM" [ipx::current_core]
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
adi_add_bus "s_axis" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"s_axis_ready" "TREADY"} \
|
||||
{"s_axis_valid" "TVALID"} \
|
||||
{"s_axis_data" "TDATA"} \
|
||||
{"s_axis_strb" "TSTRB"} \
|
||||
{"s_axis_keep" "TKEEP"} \
|
||||
{"s_axis_user" "TUSER"} \
|
||||
{"s_axis_last" "TLAST"}]
|
||||
|
||||
adi_add_bus "m_axis" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
[list {"m_axis_ready" "TREADY"} \
|
||||
{"m_axis_valid" "TVALID"} \
|
||||
{"m_axis_data" "TDATA"} \
|
||||
{"m_axis_strb" "TSTRB"} \
|
||||
{"m_axis_keep" "TKEEP"} \
|
||||
{"m_axis_user" "TUSER"} \
|
||||
{"m_axis_last" "TLAST"}]
|
||||
|
||||
adi_add_bus "wr_ctrl" "slave" \
|
||||
"analog.com:interface:if_do_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:if_do_ctrl:1.0" \
|
||||
[list {"wr_request_enable" "request_enable"} \
|
||||
{"wr_request_valid" "request_valid"} \
|
||||
{"wr_request_ready" "request_ready"} \
|
||||
{"wr_request_length" "request_length"} \
|
||||
{"wr_response_measured_length" "response_measured_length"} \
|
||||
{"wr_response_eot" "response_eot"} \
|
||||
]
|
||||
|
||||
adi_add_bus "rd_ctrl" "slave" \
|
||||
"analog.com:interface:if_do_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:if_do_ctrl:1.0" \
|
||||
[list {"rd_request_enable" "request_enable"} \
|
||||
{"rd_request_valid" "request_valid"} \
|
||||
{"rd_request_ready" "request_ready"} \
|
||||
{"rd_request_length" "request_length"} \
|
||||
{"rd_response_eot" "response_eot"} \
|
||||
]
|
||||
|
||||
adi_add_bus_clock "s_axis_aclk" "s_axis:wr_ctrl" "s_axis_aresetn"
|
||||
adi_add_bus_clock "m_axis_aclk" "m_axis:rd_ctrl" "m_axis_aresetn"
|
||||
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,19 @@
|
||||
###############################################################################
|
||||
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIBSD
|
||||
###############################################################################
|
||||
|
||||
<: setFileUsedIn { out_of_context synthesis implementation } :>
|
||||
<: ;#Component and file information :>
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName $ComponentName :>
|
||||
<: setFileExtension "_ooc.xdc" :>
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation.
|
||||
# These are default values for timing driven synthesis during OOC flow.
|
||||
# These values will be overwritten during implementation with information
|
||||
# from top level.
|
||||
|
||||
create_clock -name s_axis_aclk -period 2.5 [get_ports s_axis_aclk]
|
||||
create_clock -name m_axis_aclk -period 2.5 [get_ports m_axis_aclk]
|
||||
@@ -0,0 +1,55 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DST_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "LENGTH_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SRC_DATA_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } {
|
||||
# Procedure called to update DST_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } {
|
||||
# Procedure called to validate DST_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.LENGTH_WIDTH { PARAM_VALUE.LENGTH_WIDTH } {
|
||||
# Procedure called to update LENGTH_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.LENGTH_WIDTH { PARAM_VALUE.LENGTH_WIDTH } {
|
||||
# Procedure called to validate LENGTH_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } {
|
||||
# Procedure called to update SRC_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } {
|
||||
# Procedure called to validate SRC_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.SRC_DATA_WIDTH { MODELPARAM_VALUE.SRC_DATA_WIDTH PARAM_VALUE.SRC_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SRC_DATA_WIDTH}] ${MODELPARAM_VALUE.SRC_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DST_DATA_WIDTH { MODELPARAM_VALUE.DST_DATA_WIDTH PARAM_VALUE.DST_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DST_DATA_WIDTH}] ${MODELPARAM_VALUE.DST_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.LENGTH_WIDTH { MODELPARAM_VALUE.LENGTH_WIDTH PARAM_VALUE.LENGTH_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.LENGTH_WIDTH}] ${MODELPARAM_VALUE.LENGTH_WIDTH}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user