initial commit, add dds_par module

2024-01-15 09:36:08 +08:00
commit 315a673005
1374 changed files with 465956 additions and 0 deletions
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+###############################################################################
+## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# ip
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+adi_ip_create util_extract
+adi_ip_files util_extract [list \
+  "util_extract.v" ]
+
+adi_ip_properties_lite util_extract
+
+set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_extract} [ipx::current_core]
+
+ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+
+